PC2-5300/PC DDR2 SDRAM Unbuffered DIMM Design Specification Revision 3.1 October 2008

Transcription

1 Page Pin PC2-5300/PC DDR2 SDRAM Unbuffered DIMM Design Specification PC2-5300/PC DDR2 SDRAM Unbuffered DIMM Design Specification Revision 3.1 October 2008

2 JEDED Standard No. 21C Page Product Description...5 Table Product Family Attributes Environmental Requirements...6 Table Environmental Parameters Architecture...7 Table Pin Definition...7 Table Input/Output Functional Description...8 Table Pin DDR2 SDRAM DIMM Pin Assignment...9 Figure Block Diagram: Raw Card Version C, x64 (Populated as 1 physical rank of x16 DDR2 SDRAMs)...12 Figure Block Diagram: Raw Card Version D, x64 (Populated as 1 physical rank of x8 DDR2 SDRAMs)...13 Figure Block Diagram: Raw Card Version E, x64 (Populated as 2 physical ranks of x8 DDR2 SDRAMs)...14 Figure Block Diagram: Raw Card Version F, x72 (Populated as 1 physical rank of x8 DDR2 SDRAMs)...15 Figure Block Diagram: Raw Card Version G, x72 (Populated as 2 physical ranks of x8 DDR2 SDRAMs)...16 Figure Block Diagram: Raw Card Version H, x64 (Populated as 2 physical ranks of x16 DDR2 SDRAMs)...17 Figure Block Diagram: Raw Card Version J, x64 (Populated as 1 physical rank of x8 DDR2 SDRAMs)...18 Figure Block Diagram: Raw Card Version K, x64 (Populated as 2 physical ranks of x8 DDR2 SDRAMs) Component Details...20 Figure DIMM Common landing pattern for x8 and x16-256mb, 512Mb, 1Gb, 2Gb, and 4Gb DDR2 SDRAM Planar Components (Top View)...20 Table x8 Ballout for Common Landing Pattern Using 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb DDR2 SDRAMs (Top View)...21 Table x16 Ballout for Common Landing Pattern Using 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb DDR2 SDRAMs (Top View) Unbuffered DIMM Details...23 Table SDRAM Module Configurations (Reference Designs)...23 Table Input Loading Matrix DDR2 Unbuffered Design File Releases DDR2 DIMM Common Landing Pattern...26 Figure Component Placement On the Common Landing Pattern Component Types and Placement...27 Figure Example Component Placement (Raw Card Version C)...27 Figure Example Component Placement (Raw Card Version D)...27 Figure Example Component Placement (Raw Card Version E)...28 Figure Example Component Placement (Raw Card Version F)...28 Figure Example Component Placement (Raw Card Version G)...29 Figure Example Component Placement (Raw Card Version H)...30 Figure Example Component Placement (Raw Card Version J)...30 Figure Example Component Placement (Raw Card Version K) DIMM Wiring Details Signal Groups General Net Structure Routing Guidelines Explanation of Net Structure Diagrams...32 Release 18 Revision 3.1

3 Page Figure Net Structure Example Signal Net Structures...33 Figure Clock Net Structures (Raw Card Version C) CK1 - CK Figure Clock Net Structures (Raw Card Version D) CK0 - CK Figure Clock Net Structures (Raw Card Version E) CK0 - CK Figure Clock Net Structures (Raw Card Version F) CK0 - CK Figure Clock Net Structures (Raw Card Version G) CK0 - CK Figure Clock Net Structures (Raw Card Version H) CK0-CK Figure Clock Net Structures (Raw Card Version J) CK0 - CK Figure Clock Net Structures (Raw Card Version K) CK0 - CK Net Structure Routing...41 Figure Net Structure Routing for Data (Raw Card Version C) DQ0-DQ63, DQS0-DQS7, DQS0-DQS7, and DM0-DM Figure Net Structure Routing for Data (Raw Card Version D) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM Figure Net Structure Routing for Data (Raw Card Version E) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM Figure Net Structure Routing for Data (Raw Card Version F) DQ0 - DQ63, CB0 - CB7, DQS0 - DQS8, DQS0 - DQS8, and DM0 - DM Figure Net Structure Routing for Data (Raw Card Version G) DQ0 - DQ63, CB0 - CB7, DQS0 - DQS8, DQS0 - DQS8, and DM0 - DM Figure Net Structure Routing for Data (Raw Card Version H) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM Figure Net Structure Routing for Data (Raw Card Version J) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM Figure Net Structure Routing for Data (Raw Card Version K) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM Figure Net Structure Routing for S, CKE and ODT (Raw Card Version C)...49 Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version D)...50 Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version E)...51 Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version F)...52 Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version G)...53 Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version H)...54 Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version J)...55 Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version K)...56 Figure Net Structure Routing for Address and Command (Raw Card Version C) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version C...57 Figure Net Structure Routing for Address and Command (Raw Card Version D) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version D...58 Figure Net Structure Routing for Address and Command (Raw Card Version E) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version E...59 Figure Net Structure Routing for Address and Command (Raw Card Version F) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version F...60 Figure Net Structure Routing for Address and Command (Raw Card Version G) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version G...61 Figure Net Structure Routing for Address and Command (Raw Card Version H)

4 JEDED Standard No. 21C Page A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version H...62 Figure Net Structure Routing for Address and Command (Raw Card Version J) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version J...63 Figure Net Structure Routing for Address and Command (Raw Card Version K) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version K Cross Section Recommendations...65 Figure PCB Electrical Specifications...65 Figure Example Layer Stackup for 6 Layers and 4 mil Traces...65 Figure Example Layer Stackup for 8 Layers and 4 mil Traces Decoupling...66 Table Capacitor Sites to Populate for DRAMs with Greater Than 200pF of On-Die VDDQ/VSSQ Decoupling Capacitance...66 Table Capacitor Sites to Populate for DRAMs with Less Than 200pF of On-Die VDDQ/VSSQ Decoupling Capacitance...67 Figure Test Point Identification (Raw Card Version C)...68 Figure Test Point Identification (Raw Card Versions D and F): Back View...69 Figure Test Point Identification (Raw Card Version E): Front View...70 Figure Test Point Identification (Raw Card Version E) Details A, B, and C: Front View...70 Figure Test Point Identification (Raw Card Version E): Back View...71 Figure Test Point Identification (Raw Card Version E) Details D and E: Back View...72 Figure Test Point Identification (Raw Card Version G): Front, Right Side View...73 Figure Test Point Identification (Raw Card Version G): Front, Left Side View...74 Figure Test Point Identification (Raw Card Version G): Back, Left Side View...75 Figure Test Point Identification (Raw Card Version G): Back, Right Side View...76 Figure Test Point Identification (Raw Card Version H): Back, Left Side View...77 Figure Test Point Identification (Raw Card Version H): Front, Right Side View...78 Figure Test Point Identification (Raw Card Version H): Back, Left Side View...79 Figure Test Point Identification (Raw Card Version H): Back, Right Side View...80 Figure Test Point Identification (Raw Card Version J)...81 Figure Test Point Identification (Raw Card Version K) Serial Presence Detect Serial Presence Detect Component Specification Serial Presence Detect Definition...82 Table Serial Presence Detect, Example Raw Card Version D Product Label DIMM Mechanical Specifications...86 Figure Mechanical Drawing with Keying Positions...86 Figure VLP Mechanical Drawing with Keying Positions...87 Release 18 Revision 3.1

5 Page Product Description This specification defines the electrical and mechanical requirements for 240-pin, 1.8 Volt (V DD )/1.8 Volt (V DDQ ), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM DIMMs). These DDR2 DIMMs are intended for use as main memory when installed in PCs. Reference design examples are included which provide an initial basis for Unbuffered DDR2 DIMM designs. Modifications to these reference designs may be required to meet all system timing, signal integrity and thermal requirements for PC2-3200, PC2-4200, PC2-5300, and PC support. All Unbuffered DIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. This specification largely follows the JEDEC defined 240-pin Unbuffered DDR2 SDRAM DIMM product. (Refer to JEDEC standard JESDTBD-C, Section TBD, at Table Product Family Attributes DIMM Organization x64, x72 ECC Notes DIMM Dimensions (max) mm x 30.00mm x 4mm Refer to MO 237 Pin Count 240 DDR2 SDRAMs Supported 256Mb, 512Mb, 1Gb, 2Gb, 4Gb 68/92-ball FBGA package for x8 and 92-ball FBGA for x16 devices. Capacity Serial PD Voltage Options Interface 128MB - 8GB Consistent with JEDEC JC 45 SPD publication 1.8 Volt V DD /V DDQ All DDR2 modules use a common V DD -V DDQ power plane. They are tied together on the DIMM, but by standard definition are supported on the pinout to accommodate future enhancements. 1.7 Volt to 3.6 Volt VDD SPD SSTL_18 This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. 1. V DD SPD is not tied to V DD or V DDQ on the DDR2 DIMM.

6 JEDED Standard No. 21C Page Environmental Requirements 240-pin Unbuffered DDR2 SDRAM DIMMs are intended for use in standard office environments that have limited capacity for heating and air conditioning. Table Environmental Parameters Symbol Parameter Rating Units Notes T OPR Operating Temperature (ambient) 0 to +55 C 3 H OPR Operating Humidity (relative) 10 to 90 % T STG Storage Temperature -50 to +100 C 1 H STG Storage Humidity (without condensation) 5 to 95 % 1 P BAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. The component maximum case temperature (Tcase) shall not exceed the value specified in the DDR2 DRAM component specification. Release 18 Revision 3.1

7 Page Architecture Table Pin Definition Pin Name Description Pin Name Description A0 - A15 SDRAM address bus CK0 - CK2 SDRAM clocks (positive line of differential pair) BA0 - BA2 SDRAM bank select CK0 - CK2 SDRAM clocks (negative line of differential pair) RAS SDRAM row address strobe SCL I 2 C serial bus clock for EEPROM CAS SDRAM column address strobe SDA I 2 C serial bus data line for EEPROM WE SDRAM write enable SA0 - SA2 I 2 C slave address select for EEPROM S0 - S1 DIMM Rank Select Lines V DD* SDRAM core power supply CKE0 - CKE1 SDRAM clock enable lines V DDQ* SDRAM I/O Driver power supply ODT0 - ODT1 On-die termination control lines V REF SDRAM I/O reference supply DQ0 - DQ63 DIMM memory data bus V SS Power supply return (ground) CB0 - CB7 DIMM ECC check bits V DDSPD Serial EEPROM positive power supply DQS0 - DQS8 DQS0 - DQS8 SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) NC TEST SDRAM data masks/high data strobes (x8-based DM0 - DM8 RESET x72 DIMMs) *The VDD and VDDQ pins are tied common to a single power-plane on these designs. Spare Pins (no connect) Used by memory bus analysis tools (unused on memory DIMMS) Not used on UDIMM

8 JEDED Standard No. 21C Page Table Input/Output Functional Description Symbol Type Polarity Function CK0 - CK2 CK0 - CK2 SSTL Differential crossing CKE0 - CKE1 SSTL Active High CK and CK are differential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing) Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode S0 - S1 SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks RAS, CAS, WE SSTL Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered. ODT0 - ODT1 SSTL When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming this function is Active High enabled in the Extended Mode Register Set (EMRS). V REF Supply Reference voltage for SSTL18 inputs. V DDQ Supply Power supply for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA0 - BA2 SSTL Selects which SDRAM bank of eight is activated. During a Bank Activate command cycle, Address input defines the row address (RA0-RA15) A0 - A15 SSTL During a Read or Write command cycle, Address input defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled.during a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. DQ0 - DQ63, CB0 - CB7 SSTL Data and Check Bit Input/Output pins. DM0 - DM8 SSTL Active High DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. V DD, VSS DQS0 - DQS8 DQS0 - DQS8 Supply SSTL Differential crossing Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. Data strobe for input and output data. For Rawcards using x16 organized DRAMs, DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-15 connect to the UDQS pin of the DRAM SA0 - SA2 SDA SCL These signals are tied at the system planar to either V SS or V DDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor must be connected from the SDA bus line to V DDSPD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to V DDSPD to act as a pullup on the system board. VDDSPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. Release 18 Revision 3.1

9 Page Table Pin DDR2 SDRAM DIMM Pin Assignment (Part 1 of 3) Front Side (left 1-60) Back Side (right ) Front Side (left ) Back Side (right ) Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC 1 V REF V REF 121 VSS VSS 61 A4 A4 181 VDDQ VDDQ 2 V SS V SS 122 DQ4 DQ4 62 VDDQ VDDQ 182 A3 A3 3 DQ0 DQ0 123 DQ5 DQ5 63 A2 A2 183 A1 A1 4 DQ1 DQ1 124 V SS V SS 64 VDD VDD 184 VDD V DD 5 V SS V SS 125 DM0,DQS9 DM0,DQS9 KEY KEY 6 DQS0 DQS0 126 DQS9 DQS9 65 V SS V SS 185 CK0 CK0 7 DQS0 DQS0 127 V SS V SS 66 V SS V SS 186 CK0 CK0 8 V SS V SS 128 DQ6 DQ6 67 V DD V DD 187 V DD V DD 9 DQ2 DQ2 129 DQ7 DQ7 68 Par_In 2 Par_In A0 A0 10 DQ3 DQ3 130 V SS V SS 69 V DD V DD 189 V DD V DD 11 V SS V SS 131 DQ12 DQ12 70 A10/AP A10/AP 190 BA1 BA1 12 DQ8 DQ8 132 DQ13 DQ13 71 BA0 BA0 191 V DDQ V DDQ 13 DQ9 DQ9 133 V SS V SS 72 V DDQ V DDQ 192 RAS RAS 14 V SS V SS 134 DM1,DQS10 DM1,DQS10 73 WE WE 193 S0 S0 15 DQS1 DQS1 135 DQS10 DQS10 74 CAS CAS 194 V DDQ V DDQ 16 DQS1 DQS1 136 V SS V SS 75 V DDQ V DDQ 195 ODT0 ODT0 17 V SS V SS 137 CK1,RFU 1 CK1,RFU 1 76 S1 S1 196 A13 A13 18 Reset 2 Reset CK1,RFU 1 CK1,RFU 1 77 ODT1 ODT1 197 V DD V DD 19 NC NC 139 V SS V SS 78 V DDQ V DDQ 198 V SS V SS 20 V SS V SS 140 DQ14 DQ14 79 V SS V SS 199 DQ36 DQ36 21 DQ10 DQ DQ15 DQ15 80 DQ32 DQ DQ37 DQ37 22 DQ11 DQ V SS V SS 81 DQ33 DQ V SS V SS 23 V SS V SS 143 DQ20 DQ20 82 V SS V SS 202 DM4,DQS13 DM4,DQS13 24 DQ16 DQ DQ21 DQ21 83 DQS4 DQS4 203 DQS13 DQS13 NC = No Connect; NU = Not Usable, RFU = Reserved Future Use 1. CK0, CK0, CK1, CK1, CK2, CK2 (Pins 185, 186, 137, 138, 220, 221) are used for Unbuffered DIMM clocks. CK1, CK1,CK2, CK2 are reserved for future use on registered DIMMs. 2. Par_in, Par_out and Reset pins are intended for register control functions (Pins 18, 55, and 68) and should not be connected anywhere on the UDIMM module. 3. The TEST pin (Pin 102) is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs). 4. NC pins should not be connected to anything, including bussing within the NC group. 5. DQS9-17 are used on UDIMM as DM0-7, but DQS9-17 are unused on UDIMM designs.

10 JEDED Standard No. 21C Page Table Pin DDR2 SDRAM DIMM Pin Assignment (Part 2 of 3) Front Side (left 1-60) Back Side (right ) Front Side (left ) Back Side (right ) Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC 25 DQ17 DQ V SS V SS 84 DQS4 DQS4 204 V SS V SS 26 V SS V SS 146 DM2,DQS11 DM2,DQS11 85 V SS V SS 205 DQ38 DQ38 27 DQS2 DQS2 147 DQS11 DQS11 86 DQ34 DQ DQ39 DQ39 28 DQS2 DQS2 148 V SS V SS 87 DQ35 DQ V SS V SS 29 V SS V SS 149 DQ22 DQ22 88 V SS V SS 208 DQ44 DQ44 30 DQ18 DQ DQ23 DQ23 89 DQ40 DQ DQ45 DQ45 31 DQ19 DQ V SS V SS 90 DQ41 DQ V SS V SS 32 V SS V SS 152 DQ28 DQ28 91 V SS V SS 211 DM5,DQS14 DM5,DQS14 33 DQ24 DQ DQ29 DQ29 92 DQS5 DQS5 212 DQS14 DQS14 34 DQ25 DQ V SS V SS 93 DQS5 DQS5 213 V SS V SS 35 V SS V SS 155 DM3,DQS12 DM3,DQS12 94 V SS V SS 214 DQ46 DQ46 36 DQS3 DQS3 156 DQS12 DQS12 95 DQ42 DQ DQ47 DQ47 37 DQS3 DQS3 157 V SS V SS 96 DQ43 DQ V SS V SS 38 V SS V SS 158 DQ30 DQ30 97 V SS V SS 217 DQ52 DQ52 39 DQ26 DQ DQ31 DQ31 98 DQ48 DQ DQ53 DQ53 40 DQ27 DQ V SS V SS 99 DQ49 DQ V SS V SS 41 V SS V SS 161 NC CB4 100 V SS V SS 220 CK2,RFU 1 CK2,RFU 1 42 NC CB0 162 NC CB5 101 SA2 SA2 221 CK2,RFU 1 CK2,RFU 1 43 NC CB1 163 V SS V SS 102 TEST 3 TEST V SS V SS 44 V SS V SS 164 NC DM8,DQS V SS V SS 223 DM6,DQS15 DM6,DQS15 45 NC DQS8 165 NC DQS DQS6 DQS6 224 DQS15 DQS15 46 NC DQS8 166 V SS V SS 105 DQS6 DQS6 225 V SS V SS 47 V SS V SS 167 NC CB6 106 V SS V SS 226 DQ54 DQ54 48 NC CB2 168 NC CB7 107 DQ50 DQ DQ55 DQ55 49 NC CB3 169 V SS V SS 108 DQ51 DQ V SS V SS 50 V SS V SS 170 V DDQ V DDQ 109 V SS V SS 229 DQ60 DQ60 NC = No Connect; NU = Not Usable, RFU = Reserved Future Use 1. CK0, CK0, CK1, CK1, CK2, CK2 (Pins 185, 186, 137, 138, 220, 221) are used for Unbuffered DIMM clocks. CK1, CK1,CK2, CK2 are reserved for future use on registered DIMMs. 2. Par_in, Par_out and Reset pins are intended for register control functions (Pins 18, 55, and 68) and should not be connected anywhere on the UDIMM module. 3. The TEST pin (Pin 102) is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs). 4. NC pins should not be connected to anything, including bussing within the NC group. 5. DQS9-17 are used on UDIMM as DM0-7, but DQS9-17 are unused on UDIMM designs. Release 18 Revision 3.1

11 Page Table Pin DDR2 SDRAM DIMM Pin Assignment (Part 3 of 3) Front Side (left 1-60) Back Side (right ) Front Side (left ) Back Side (right ) Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC Pin # x64 Non-Parity x72 ECC 51 V DDQ V DDQ 171 CKE1 CKE1 110 DQ56 DQ DQ61 DQ61 52 CKE0 CKE0 172 V DD VDD 111 DQ57 DQ V SS V SS 53 V DD V DD 173 A15 A V SS V SS 232 DM7,DQS16 DM7,DQS16 54 BA2 BA2 174 A14 A DQS7 DQS7 233 DQS16 DQS16 55 Par_Out 2 Par_Out V DDQ V DDQ 114 DQS7 DQS7 234 V SS V SS 56 V DDQ V DDQ 176 A12 A V SS V SS 235 DQ62 DQ62 57 A11 A A9 A9 116 DQ58 DQ DQ63 DQ63 58 A7 A7 178 VDD VDD 117 DQ59 DQ V SS V SS 59 V DD V DD 179 A8 A8 118 V SS V SS 238 V DD SPD V DD SPD 60 A5 A5 180 A6 A6 119 SDA SDA 239 SA0 SA0 120 SCL SCL 240 SA1 SA1 NC = No Connect; NU = Not Usable, RFU = Reserved Future Use 1. CK0, CK0, CK1, CK1, CK2, CK2 (Pins 185, 186, 137, 138, 220, 221) are used for Unbuffered DIMM clocks. CK1, CK1,CK2, CK2 are reserved for future use on registered DIMMs. 2. Par_in, Par_out and Reset pins are intended for register control functions (Pins 18, 55, and 68) and should not be connected anywhere on the UDIMM module. 3. The TEST pin (Pin 102) is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs). 4. NC pins should not be connected to anything, including bussing within the NC group. 5. DQS9-17 are used on UDIMM as DM0-7, but DQS9-17 are unused on UDIMM designs.

12 JEDED Standard No. 21C Page Figure Block Diagram: Raw Card Version C, x64 (Populated as 1 physical rank of x16 DDR2 SDRAMs) S0 DQS0 DQS0 DM0 DQS1 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDQS LDM UDQS UDM I/O 8 I/O CS D0 DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM DQS1 UDQS UDQS UDQS UDM I/O 8 I/O CS D2 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ291 DQ30 DQ31 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D1 DQS6 DQS6 DM6 DQS7 DQS7 DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D3 Serial PD V DD SPD SPD SCL WP A0 A1 A2 SDA V DD /V DDQ V REF V SS D0 - D3 D0 - D3 D0 - D3 SA0 SA1 SA2 BA0 - BA2 A0 - A15 RAS CAS CKE0 WE ODT0 BA0-BA2: SDRAMs D0 - D3 A0-A15: SDRAMs D0 - D3 RAS: SDRAMs D0 - D3 CAS: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 WE: SDRAMs D0 - D3 ODT: SDRAMs D0 - D3 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: 22 Ohms±5%. 4. BAx, Ax, RAS, CAS, WE resistors: 10 Ohms±5% 5. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document Release 18 Revision 3.1

13 Page Figure Block Diagram: Raw Card Version D, x64 (Populated as 1 physical rank of x8 DDR2 SDRAMs) DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0 DM DM DQ15 DM DM CS DQS DQS D0 CS DQS DQS D1 CS DQS DQS D2 CS DQS DQS D3 DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 Serial PD DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DM DM DM CS CS CS CS DQS DQS D4 DQS DQS D5 DQS DQS D6 DQS DQS D7 BA0 - BA2 A0 - A15 RAS CAS CKE0 WE ODT0 BA0-BA2: SDRAMs D0 - D7 A0-A15: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 SCL V DD SPD CKE: SDRAMs D0 - D7 V DD /V DDQ WE: SDRAMs D0 - D7 V REF ODT: SDRAMs D0 - D7 V SS WP A0 A1 A2 SA0 SA1 SA2 SPD SDA D0 - D8 D0 - D8 D0 - D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. BAx, Ax, RAS, CAS, WE resistors: refer to associated topology diagram 5. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document

14 JEDED Standard No. 21C Page Figure Block Diagram: Raw Card Version E, x64 (Populated as 2 physical ranks of x8 DDR2 SDRAMs) DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 V DD SPD V DD /V DDQ V REF V SS BA0 - BA2 A0 - A15 CKE1 CKE0 RAS CAS WE ODT0 ODT1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0 DM CS DQS DQS D0 DM CS DQS DQS D1 DM CS DQS DQS D2 DM CS DQS DQS D3 BA0-BA2: SDRAMs D0 - D15 A0-A15: SDRAMs D0 - D15 CKE: SDRAMs D8 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 WE: SDRAMs D0 - D15 S1 DQ15 SPD D0 - D15 D0 - D15 D0 - D15 CKE: SDRAMs D0 - D7 ODT: SDRAMs D0 - D7 ODT: SDRAMs D8 - D15 DM CS DQS DQS D8 DM CS DQS DQS D9 DM CS DQS DQS D10 DM CS DQS DQS D11 SCL WP A0 Serial PD A1 DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 A2 SA0 SA1 SA2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDA DM CS DQS DQS DM CS DQS DQS D4 D12 DM CS DQS DQS DM CS DQS DQS D5 D13 DM CS DQS DQS DM CS DQS DQS D6 D14 DM CS DQS DQS DM CS DQS DQS D7 D15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associate topology diagram 4. BAx, Ax, RAS, CAS, WE resistors: Refer to associate topology diagram Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document Release 18 Revision 3.1

15 Page Figure Block Diagram: Raw Card Version F, x72 (Populated as 1 physical rank of x8 DDR2 SDRAMs) BA0 - BA2 A0 - A15 RAS CAS CKE0 WE ODT0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0 DM DM DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM DM DM CS CS CS CS CS D0 D1 D2 D3 D8 DQS DQS DQS DQS DQS DQS DQS DQS DQS DQS BA0-BA2: SDRAMs D0 - D8 A0-A15: SDRAMs D0 - D8 V DD SPD RAS: SDRAMs D0 - D8 V DD /V DDQ CAS: SDRAMs D0 - D8 CKE: SDRAMs D0 - D8 V REF WE: SDRAMs D0 - D8 V SS ODT: SDRAMs D0 - D8 SCL DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 WP A0 DQS7 DQS7 DM7 Serial PD A1 A2 SA0 SA1 SA2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SPD D0 - D8 D0 - D8 D0 - D8 SDA DM DM DM DM CS CS CS CS D4 D5 D6 DQS DQS D7 DQS DQS DQS DQS DQS DQS Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, CB, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. BAx, Ax, RAS, CAS, WE resistors: Refer to associate topology diagram 5. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document

16 JEDED Standard No. 21C Page Figure Block Diagram: Raw Card Version G, x72 (Populated as 2 physical ranks of x8 DDR2 SDRAMs) DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 BA0 - BA2 A0 - A15 CKE0 CKE1 RAS CAS WE ODT0 ODT1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ32 D0 D9 DQ33 D4 DQ34 D13 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ40 D1 DQ41 D10 D5 D14 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 S0 S1 DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ48 D2 D11 DQ49 D6 DQ50 D15 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ56 D3 D12 DQ57 D7 DQ58 D16 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS DM CS DQS DQS D8 D17 BA0-BA2: SDRAMs D0 - D17 A0-A15: SDRAMs D0 - D17 CKE: SDRAMs D0 - D8 Serial PD CKE: SDRAMs D9 - D17 RAS: SDRAMs D0 - D17 SCL CAS: SDRAMs D0 - D17 WP WE: SDRAMs D0 - D17 A0 A1 A2 ODT: SDRAMs D0 - D8 ODT: SDRAMs D9 - D17 SA0 SA1 SA2 SDA V DD SPD V DD /V DDQ V REF V SS SPD D0 - D17 D0 - D17 D0 - D17 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, CB, DM/DQS/DQS resistors: Refer to associate topology diagram 4. BAx, Ax, RAS, CAS, WE resistors: Refer to associate topology diagram Release 18 Revision 3.1

17 Page Figure Block Diagram: Raw Card Version H, x64 (Populated as 2 physical ranks of x16 DDR2 SDRAMs) S1 S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D0DQ32 DQ33 D0 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D4 DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS DQ32 D2DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D6 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ291 DQ30 DQ31 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D1 D1DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 LDQS LDQS LDM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 UDQS UDQS UDM DQ56 I/O 8 DQ57 I/O 9 DQ58 0 DQ59 1 DQ60 2 DQ61 3 DQ62 4 DQ63 5 CS CS DQ32 DQ33 DQ34 D3 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM UDQS UDQS UDM I/O 8 I/O CS D7 Serial PD V DD SPD SPD SCL WP A0 A1 A2 SDA V DD /V DDQ V REF V SS D0 - D7 D0 - D7 D0 - D7 SA0 SA1 SA2 BA0 - BA2 A0 - A15 RAS CAS CKE0 CKE1 WE ODT0 ODT1 BA0-BA2: SDRAMs D0 - D7 A0-A15: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D3 CKE: SDRAMs D4 - D7 WE: SDRAMs D0 - D7 ODT: SDRAMs D0 - D3 ODT: SDRAMs D4 - D7 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: 22 Ohms±5%. 4. BAx, Ax, RAS, CAS, WE resistors: 10 Ohms±5% 5. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document

18 JEDED Standard No. 21C Page Figure Block Diagram: Raw Card Version J, x64 (Populated as 1 physical rank of x8 DDR2 SDRAMs) DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0 DM DM DQ15 DM DM CS DQS DQS D0 CS DQS DQS D1 CS DQS DQS D2 CS DQS DQS D3 DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 Serial PD DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DM DM DM CS CS CS CS DQS DQS D4 DQS DQS D5 DQS DQS D6 DQS DQS D7 BA0 - BA2 A0 - A15 RAS CAS CKE0 WE ODT0 BA0-BA2: SDRAMs D0 - D7 A0-A15: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 SCL V DD SPD CKE: SDRAMs D0 - D7 V DD /V DDQ WE: SDRAMs D0 - D7 V REF ODT: SDRAMs D0 - D7 V SS WP A0 A1 A2 SA0 SA1 SA2 SPD SDA D0 - D8 D0 - D8 D0 - D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. BAx, Ax, RAS, CAS, WE resistors: refer to associated topology diagram 5. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document Release 18 Revision 3.1

19 Page Figure Block Diagram: Raw Card Version K, x64 (Populated as 2 physical ranks of x8 DDR2 SDRAMs) DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 V DD SPD V DD /V DDQ V REF V SS BA0 - BA2 A0 - A15 CKE1 CKE0 RAS CAS WE ODT0 ODT1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0 DM CS DQS DQS D0 DM CS DQS DQS D1 DM CS DQS DQS D2 DM CS DQS DQS D3 BA0-BA2: SDRAMs D0 - D15 A0-A15: SDRAMs D0 - D15 CKE: SDRAMs D8 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 WE: SDRAMs D0 - D15 S1 DQ15 SPD D0 - D15 D0 - D15 D0 - D15 CKE: SDRAMs D0 - D7 ODT: SDRAMs D0 - D7 ODT: SDRAMs D8 - D15 DM CS DQS DQS D8 DM CS DQS DQS D9 DM CS DQS DQS D10 DM CS DQS DQS D11 SCL WP A0 Serial PD A1 DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 A2 SA0 SA1 SA2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDA DM CS DQS DQS DM CS DQS DQS D4 D12 DM CS DQS DQS DM CS DQS DQS D5 D13 DM CS DQS DQS DM CS DQS DQS D6 D14 DM CS DQS DQS DM CS DQS DQS D7 D15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associate topology diagram 4. BAx, Ax, RAS, CAS, WE resistors: Refer to associate topology diagram Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document

20 JEDED Standard No. 21C Page Component Details Figure DIMM Common landing pattern for x8 and x16-256mb, 512Mb, 1Gb, 2Gb, and 4Gb DDR2 SDRAM Planar Components (Top View) Maximum Package Keepout: 12.3mm A B C D E F G H J K L M N Maximum Package Keepout: 21.9mm P R T U V W Y AA AB 0.8mm 0.8mm Release 18 Revision 3.1

21 Page Table x8 Ballout for Common Landing Pattern Using 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb DDR2 SDRAMs (Top View) NC NC A NC NC B C V DD NC V SS D V SSQ NC V DDQ NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC V DD NU VSS H V SSQ DQS V DDQ DQ6 V SSQ DM J DQS V SSQ DQ7 V DDQ DQ1 V DDQ K V DDQ DQ0 V DDQ DQ4 V SSQ DQ3 L DQ2 V SSQ DQ5 V DDL V REF V SS M V SSDL CK V DD CKE WE N RAS CK ODT BA2 BA0 BA1 P CAS CS A10 A1 R A2 A0 V DD V SS A3 A5 T A6 A4 A7 A9 U A11 A8 V SS V DD A12 A14 V A15 A13 W Y NC NC AA NC NC NC NC AB NC NC

22 JEDED Standard No. 21C Page Table x16 Ballout for Common Landing Pattern Using 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb DDR2 SDRAMs (Top View) NC NC A NC NC B C V DD NC V SS D V SSQ UDQS V DDQ UDQ6 V SSQ UDM E UDQS V SSQ UDQ7 V DDQ UDQ1 V DDQ F V DDQ UDQ0 V DDQ UDQ4 V SSQ UDQ3 G UDQ2 V SSQ UDQ5 V DD NC V SS H V SSQ LDQS V DDQ LDQ6 V SSQ LDM J LDQS V SSQ LDQ7 V DDQ LDQ1 V DDQ K V DDQ LDQ0 V DDQ LDQ4 V SSQ LDQ3 L LDQ2 V SSQ LDQ5 V DDL V REF V SS M V SSDL CK V DD CKE WE N RAS CK ODT BA2 BA0 BA1 P CAS CS A10 A1 R A2 A0 V DD V SS A3 A5 T A6 A4 A7 A9 U A11 A8 V SS VDD A12 A14 V A15 A13 W Y NC NC AA NC NC NC NC AB NC NC Release 18 Revision 3.1

23 Page Unbuffered DIMM Details Table SDRAM Module Configurations (Reference Designs) Raw Card Version DIMM Capacity DIMM Organization SDRAM Density SDRAM Organization # of SDRAMs SDRAM Package Type # of Physical Ranks # of Banks in SDRAM # Address bits row/col 128MB 16 Meg x Megabit 16 Meg x ball FBGA /9 256MB 32 Meg x Megabit 32 Meg x ball FBGA /10 C 512MB 64 Meg x 64 1 Gigabit 64 Meg x ball FBGA /10 1GB 128 Meg x 64 2 Gigabit 128 Meg x ball FBGA /10 2GB 256 Meg x 64 4 Gigabit 256 Meg x ball FBGA /10 256MB 32 Meg x Megabit 32 Meg x /92-ball FBGA /10 512MB 64 Meg x Megabit 64 Meg x /92-ball FBGA /10 D 1GB 128 Meg x 64 1 Gigabit 128 Meg x /92-ball FBGA /10 2GB 256 Meg x 64 2 Gigabit 256 Meg x /92-ball FBGA /10 4GB 512 Meg x 64 4 Gigabit 512 Meg x /92-ball FBGA /10 512MB 64 Meg x Megabit 32 Meg x /92-ball FBGA /10 1GB 128 Meg x Megabit 64 Meg x /92-ball FBGA /10 E 2GB 256 Meg x 64 1 Gigabit 128 Meg x /92-ball FBGA /10 4GB 512 Meg x 64 2 Gigabit 256 Meg x /92-ball FBGA /10 8GB 1 Gig x 64 4 Gigabit 512 Meg x /92-ball FBGA /10 256MB 32 Meg x Megabit 32 Meg x /92-ball FBGA /10 512MB 64 Meg x Megabit 64 Meg x /92-ball FBGA /10 F 1GB 128 Meg x 72 1 Gigabit 128 Meg x /92-ball FBGA /10 2GB 256 Meg x 72 2 Gigabit 256 Meg x /92-ball FBGA /10 4GB 512 Meg x 72 4 Gigabit 512 Meg x /92-ball FBGA /10 512MB 64 Meg x Megabit 32 Meg x /92-ball FBGA /10 1GB 128 Meg x Megabit 64 Meg x /92-ball FBGA /10 G H 2GB 256 Meg x 72 1 Gigabit 128 Meg x /92-ball FBGA /10 4GB 512 Meg x 72 2 Gigabit 256 Meg x /92-ball FBGA /10 8GB 1 Gig x 72 4 Gigabit 512 Meg x /92-ball FBGA /10 256MB 32 Meg x Megabit 16 Meg x /92-ball FBGA /9 512MB 64 Meg x Megabit 32 Meg x /92-ball FBGA /10 1GB 128 Meg x 64 1 Gigabit 64 Meg x /92-ball FBGA /10 2GB 256 Meg x 64 2 Gigabit 128 Meg x /92-ball FBGA /10 4GB 512 Meg x 64 4 Gigabit 256 Meg x /92-ball FBGA /10 1. The 68/92-ball designation indicates maximum ball count for the package. Some package may implement fewer or no mechanical support balls, at the package extremities, resulting in lower ball count. Please consult DRAM suppliers data sheet for mechanical support ball information.

24 JEDED Standard No. 21C Page Table SDRAM Module Configurations (Reference Designs) (Continued) Raw Card Version DIMM Capacity DIMM Organization SDRAM Density SDRAM Organization # of SDRAMs SDRAM Package Type # of Physical Ranks # of Banks in SDRAM # Address bits row/col 256MB 32 Meg x Megabit 32 Meg x /92-ball FBGA /10 512MB 64 Meg x Megabit 64 Meg x /92-ball FBGA /10 J 1GB 128 Meg x 64 1 Gigabit 128 Meg x /92-ball FBGA /10 2GB 256 Meg x 64 2 Gigabit 256 Meg x /92-ball FBGA /10 4GB 512 Meg x 64 4 Gigabit 512 Meg x /92-ball FBGA /10 512MB 64 Meg x Megabit 32 Meg x /92-ball FBGA /10 1GB 128 Meg x Megabit 64 Meg x /92-ball FBGA /10 K 2GB 256 Meg x 64 1 Gigabit 128 Meg x /92-ball FBGA /10 4GB 512 Meg x 64 2 Gigabit 256 Meg x /92-ball FBGA /10 8GB 1 Gig x 64 4 Gigabit 512 Meg x /92-ball FBGA /10 1. The 68/92-ball designation indicates maximum ball count for the package. Some package may implement fewer or no mechanical support balls, at the package extremities, resulting in lower ball count. Please consult DRAM suppliers data sheet for mechanical support ball information. Release 18 Revision 3.1

25 Page Table Input Loading Matrix Signal Names Input Device Raw Card Version C Raw Card Version D Raw Card Version E Raw Card Version F Raw Card Version G Raw Card Version H CK/CK SDRAM CS/CKE/ODT SDRAM Addr/RAS/CAS/BA/WE SDRAM DQ/DQS/DQS/DM SDRAM CB/DQS8/DQS8/DM8 SDRAM 1 2 SCL/SDA/SA EEPROM Six SDRAMs or equivalent using padding capacitors. 2. For Raw Card Version C CK0 has only a 82 Ohm termination. 5.1 DDR2 Unbuffered Design File Releases Reference design file updates will be released as needed. This DDR2 Unbuffered DIMM specification will reflect the most recent design files, but may also be updated to reflect clarifications to the specification only; in these cases the design files will not be updated. The following table outlines the most recent design file releases. Note: Future design file releases will include both a date and a revision label. All changes to the design file are also documented within the "read-me" file. Raw Card Version Specification Revision Applicable Gerber File Notes C 1.0 C1.0 Raw Card Version C - R1.0 Release D 2.0 D2.0 Raw Card Version D - R3.1 Release E 2.0 E2.0 Raw Card Version E - R3.1 Release F 2.0 F2.0 Raw Card Version F - R3.1 Release G 2.0 G2.0 Raw Card Version G - R3.1 Release H 1.0 H1.0 Raw Card Version H - R1.0 Release J 3.0 Raw Card Version J K 3.0 Raw Card Version K

26 JEDED Standard No. 21C Page DDR2 DIMM Common Landing Pattern The DDR2 raw cards are designed using a common landing pattern to support two different package ball-out options. The two types supported are the centered and the offset ballout. The common landing pattern is a superset of both ballout schemes. The diagrams shown below illustrate the ball mapping graphically. Figure Component Placement On the Common Landing Pattern A B C NC NC NC NC A B C NC NC NC NC D VDD NC VSS VSSQ UDQS VDDQ D VDD NC VSS VSSQ NC VDDQ A NC NC NC NC E UDQ6 VSSQ UDM UDQS VSSQ UDQ7 E UDQ6 VSSQ UDM UDQS VSSQ UDQ7 B F VDDQ UDQ1 VDDQ VDDQ UDQ0 VDDQ F VDDQ UDQ1 VDDQ VDDQ UDQ0 VDDQ C G UDQ4 VSSQ UDQ3 UDQ2 VSSQ UDQ5 G UDQ4 VSSQ UDQ3 UDQ2 VSSQ UDQ5 D H VDD NC VSS VSSQ LDQS VDDQ H VDD NC VSS VSSQ LDQS VDDQ E VDD NU VSS VSSQ DQS VDDQ J LDQS VSSQ LDQ6 VSSQ LDM LDQ7 J LDQS VSSQ LDQ6 VSSQ LDM LDQ7 F NU, DQ6 NC DM DQS VSSQ DQ7 K VDDQ DQ1 VDDQ VDDQ LDQ0 VDDQ K VDDQ DQ1 VDDQ VDDQ LDQ0VDDQ G VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ L LDQ4 VSSQ LDQ3 LDQ2 VSSQ LDQ5 L LDQ4 VSSQ LDQ3 LDQ2 VSSQ LDQ5 H DQ4 VSSQ DQ3 DQ2 VSSQ DQ5 M VDDL VREF VSS VSSDL CK VDD M VDDL VREF VSS VSSDL CK VDD J VDDL VREF VSS VSSDL CK VDD N CKE WE RAS CK ODT N CKE WE RAS CK ODT K CKE WE RAS CK ODT P CAS CS BA2 BA0 BA1 P CAS CS BA2 BA0 BA1 L BA2 BA0 BA1 CAS CS R A10 A1 A2 A0 VDD R A10 A1 A2 A0 VDD M A10 A1 A2 A0 VDD T A6 A4 VSS A3 A5 T A6 A4 VSS A3 A5 N VSS A3 A5 A6 A4 U A7 A9 A11 A8 VSS U A7 A9 A11 A8 VSS P A7 A9 A11 A8 VSS V A15 A13 VDD A12 A14 V A15 A13 VDD A12 A14 R VDD A12 A14 A15 A13 W W T Y Y U AA NC NC NC NC AA NC NC NC NC V AB NC NC NC NC W NC NC NC NC Common Landing Pattern (Top View) x4, x8, x16 Design x4, x8 Design Release 18 Revision 3.1

27 Page Component Types and Placement Components shall be positioned on the PCB to meet the minimum and maximum trace lengths required for DDR SDRAM signals. Bypass capacitors for DDR SDRAM devices must be located near the device power pins. The following layouts suggest placement for the Raw Card Versions C, D, E, F, G and H. Exact spacing is not provided, but should be based on manufacturing constraints and signal routing constraints imposed by this design guide. Figure Example Component Placement (Raw Card Version C) FRONT (2X) SIDE SPD (2) ±0.10 Figure Example Component Placement (Raw Card Version D) FRONT SIDE SPD (2X) ±0.10 (2)

28 JEDED Standard No. 21C Page Figure Example Component Placement (Raw Card Version E) FRONT SPD (2X) (2) BACK SIDE ±0.10 Figure Example Component Placement (Raw Card Version F) FRONT SPD (2X) SIDE ±0.10 (2) Release 18 Revision 3.1

29 Page Figure Example Component Placement (Raw Card Version G) FRONT SPD (2X) (2) BACK SIDE ±0.10

30 JEDED Standard No. 21C Page Figure Example Component Placement (Raw Card Version H) FRONT (2X) (2) BACK SIDE ±0.10 Figure Example Component Placement (Raw Card Version J) FRONT SIDE 3.18 SPD 18.3 Release 18 Revision 3.1

31 Page Figure Example Component Placement (Raw Card Version K) FRONT SIDE SPD BACK

32 JEDED Standard No. 21C Page DIMM Wiring Details 6.1 Signal Groups This specification categorizes DDR2 SDRAM timing-critical signals into four groups. The following table summarizes the signals contained in each group. Signal Group Signals In Group Raw Card Version Page Clock CK0 - CK2, CK0 - CK2 C, D, E, F, G, H, J, K 33, 34, 35, 36, 37, 38, 39, 40 Data, DM, DQS/DQS DQ [63:0]; CB [7:0]; DQS [8:0], DQS [8:0], DM [8:0] C, D, E, F, G, H, J, K 41, 42, 43, 44, 45, 46, 47, 48 S0, ODT0, CKE0 C, D, F, J 49, 50, 52, 55 S, ODT,CKE S0 - S1, ODT0 - ODT1, CKE0 - CKE1 E, G, H, K 51, 53, 54, 56 Address/Control Ax, BAx, RAS, CAS, WE C, D, E, F, G, H, J, K 57, 58, 59, 60, 61, 62, 63, General Net Structure Routing Guidelines Net structures and lengths must satisfy signal quality and setup/hold time requirements for the memory interface. Net structure diagrams for each signal group are shown in the following sections. Each diagram is accompanied by a trace length table that lists the minimum and maximum allowable lengths for each trace segment and/or net. The general routing requirements are as follows Test points are required on all signal groups. 6.3 Explanation of Net Structure Diagrams The net structure routing diagrams provide a reference design example for each raw card version. These designs provide an initial basis for unbuffered DIMM designs. The diagrams should be used to determine individual signal wiring on a DIMM for any supported configuration. Only transmission lines (represented as cylinders and labeled with trace length designators TL ) represent physical trace segments. All other lines are zero in length. To verify DIMM functionality, a full simulation of all signal integrity and timing is required. The given net structures and trace lengths are not inclusive for all solutions. Once the net structure has been determined, the permitted trace lengths for the net structure can be read from the table below each net structure routing diagram. Some configurations require the use of multiple net structure routing diagrams to account for varying load quantities on the same signal. All diagrams define one load as one SDRAM input. Figure Net Structure Example A typical data net structure is shown in the following diagram. DIMM Connector TL0 R0 TL1 Release 18 Revision 3.1

33 Page Signal Net Structures Figure Clock Net Structures (Raw Card Version C) CK1 - CK2 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality (Slew rate and crossing point) Rise/fall time SDRAM component edge skew. CK0, CK0 TL0 R1 C1 TL1 DIMM CK1, CK1 Connector CK2, CK2 TL0 TL1 R1 Test point across resistor R1 C1 Table Trace Lengths for Clock Net Structures Clock Nets TL0 TL1 Min Max Min Max Min Max Min Max Min Max Min Max R1 C1 Notes CK0/CK ±5% 1, 2 CK1/CK1 CK2/CK ±5% 1.5±0.25pF 1 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. CK0/CK0 not used on the DIMM.

34 JEDED Standard No. 21C Page Figure Clock Net Structures (Raw Card Version D) CK0 - CK2 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality (Slew rate and crossing point) Rise/fall time SDRAM component edge skew R1 C1 TL1C Test point at CK and CK use split point vias C2 DIMM CK Connector CK TL0 TL1B TL1C For CK0/CK0 SDRAM and length, not present Test point at CK and CK use split point vias R1 TL1A Test point at CK and CK use split point vias R1 C1 Table Trace Lengths for Clock Net Structures Clock Nets TL0 TL1A TL1B TL1C R1 C1 C2 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Ohms pf pf Note CK0/CK ±5% 1±0.25 2± CK1/CK1 CK2/CK ±5% 1±0.25 1± All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. Release 18 Revision 3.1

35 Page Figure Clock Net Structures (Raw Card Version E) CK0 - CK2 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality (Slew rate and crossing point) Rise/fall time SDRAM component edge skew R1 TL1 DIMM CK Connector CK TL0 TL1 Note 2 R1 C1 Note 2 TL1 R1 Table Trace Lengths for Clock Net Structures Clock Nets TL0 TL1 R1 C1 Min Max Min Max Min Max Min Max Min Max Min Max Ohms pf Notes CK0/CK ±5% 1.5±0.25% 1, 2 CK1/CK ±5% 1 CK2/CK ±5% 1 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. For CK0, CK0 these DRAMs are not placed. Capacitor C1 is placed instead. segments are not present where DRAMs are omitted.

36 JEDED Standard No. 21C Page Figure Clock Net Structures (Raw Card Version F) CK0 - CK2 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality (Slew rate and crossing point) Rise/fall time SDRAM component edge skew R1 C1 TL1C Test point at CK and CK use split point vias C1 DIMM CK Connector CK TL0 TL1B TL1C Test point at CK and CK use split point vias R1 TL1A Test point at CK and CK use split point vias R1 C1 Table Trace Lengths for Clock Net Structures Clock Nets CK0/CK0 CK1/CK1 CK2/CK2 TL0 TL1A TL1B TL1C R1 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Ohms ±5% 1± All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. C1 pf Note Release 18 Revision 3.1

37 Page Figure Clock Net Structures (Raw Card Version G) CK0 - CK2 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality (Slew rate and crossing point) Rise/fall time SDRAM component edge skew R1 TL1 DIMM CK Connector CK TL0 TL1 R1 TL1 R1 Table Trace Lengths for Clock Net Structures Clock Nets TL0 TL1 R1 Min Max Min Max Min Max Min Max Ohms Notes CK0/CK ±5% 1 CK1/CK ±5% 1 CK2/CK ±5% 1 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters.

38 JEDED Standard No. 21C Page Figure Clock Net Structures (Raw Card Version H) CK0-CK2 CK0 CK0 TL0 R1 R1 TL1 C1 DIMM CK1, CK2 Connector CK1, CK2 TL0 TL1 R1 TL1 R1 Table Trace Lengths for Clock Net Structures Clock Nets TL0 TL1 C1 R1 Min Max Min Max Min Max Min Max Min Max pf Ohms Notes CK1/CK ± ±5% 1 CK2/CK ± ±5% 1 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. Release 18 Revision 3.1

39 Page Figure Clock Net Structures (Raw Card Version J) CK0 - CK2 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality (Slew rate and crossing point) Rise/fall time SDRAM component edge skew R1 C1 TL1C Test point at CK and CK use split point vias C2 DIMM CK Connector CK TL0 TL1B TL1C For CK0/CK0 SDRAM and length, not present Test point at CK and CK use split point vias R1 TL1A Test point at CK and CK use split point vias R1 C1 Table Trace Lengths for Clock Net Structures Clock Nets TL0 TL1A TL1B TL1C R1 C1 C2 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Ohms pf pf Note CK0/CK ±5% 1±0.25 2± CK1/CK1 CK2/CK ±5% 1±0.25 1± All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters.

40 JEDED Standard No. 21C Page Figure Clock Net Structures (Raw Card Version K) CK0 - CK2 SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality (Slew rate and crossing point) Rise/fall time SDRAM component edge skew R1 TL1 DIMM CK Connector CK TL0 TL1 Note 2 R1 C1 Note 2 TL1 R1 Table Trace Lengths for Clock Net Structures Clock Nets TL0 TL1 R1 C1 Min Max Min Max Min Max Min Max Min Max Min Max Ohms pf Notes CK0/CK ±5% 1.5±0.25% 1, 2 CK1/CK ±5% 1 CK2/CK ±5% 1 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. For CK0, CK0 these DRAMs are not placed. Capacitor C1 is placed instead. segments are not present where DRAMs are omitted. Release 18 Revision 3.1

41 Page Net Structure Routing Figure Net Structure Routing for Data (Raw Card Version C) DQ0-DQ63, DQS0-DQS7, DQS0-DQS7, and DM0-DM7 DIMM Connector TL0A R1 TL1 2 VIAs Test point at this VIA DIMM Connector 3 VIAs TL0A TL0B R1 TL1 Test point at this VIA Table Trace Lengths for DQ, DQS and DM Net Structures Total VIAs TL0A TL0B TL1 Total R1 In Trace Min Max Min Max Min Max Min Max Min Max Min Max Ohms Notes ±5% 1, 2, ±5% 1, 2, 3 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. Signals with 3 VIAs are shortened by 2.5mm to compensate for the additional delay caused by the extra VIA. 3. These signals must be referenced to ground.

42 JEDED Standard No. 21C Page Figure Net Structure Routing for Data (Raw Card Version D) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 DIMM Connector TL0 R1 TL1 Table Trace Lengths for DQ, DQS0 - DQS7, DQS0 - DQS7 and DM0 - DM7 Net Structures TL0 TL1 Total R1 Min Max Min Max Min Max Ohms Notes ±5% 1, 2, 3 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1. 3. These signals must be referenced to ground. Release 18 Revision 3.1

43 Page Figure Net Structure Routing for Data (Raw Card Version E) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 For DQ0, DQ4, DQ59, and DQ63 test point on trace 4mm from SDRAM pin DIMM Connector TL0 R1 TL1 On pre-production modules, for DQS0, DQS0, DQS7, and DQS7 there is an opening in the solder mask 10mm from SDRAM pin Table Trace Lengths for DQ, DQS0 - DQS7, DQS0 - DQS7 and DM0 - DM7 Net Structures TL0 TL1 Total R1 Notes Min Max Min Max Min Max Min Max Ohms ±5% 1, 2 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. These signals are referenced to ground.

44 JEDED Standard No. 21C Page Figure Net Structure Routing for Data (Raw Card Version F) DQ0 - DQ63, CB0 - CB7, DQS0 - DQS8, DQS0 - DQS8, and DM0 - DM8 DIMM Connector TL0 R1 TL1 Table Trace Lengths for DQ, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 Net Structures TL0 TL1 Total R1 Min Max Min Max Min Max Ohms Notes ±5% 1, 2, 3 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1. 3. These signals must be referenced to ground. Table Trace Lengths for CB, DQS8, DQS8, and DM8 Net Structures TL0 TL1 Total R1 Min Max Min Max Min Max Ohms Notes ±5% 1, 2, 3 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1. 3. The DQS, DQS, and DM signals associated with the CB should be matched to the CB length within a tolerance of ± 0.3 millimeters. 4. These signals must be referenced to ground. Release 18 Revision 3.1

45 Page Figure Net Structure Routing for Data (Raw Card Version G) DQ0 - DQ63, CB0 - CB7, DQS0 - DQS8, DQS0 - DQS8, and DM0 - DM8 For DQ0, DQ4, DQ59, and DQ63 test point on trace 4mm from SDRAM pin DIMM Connector TL0 R1 TL1 On pre-production modules, for DQS0, DQS0, DQS7, and DQS7 there is an opening in the solder mask 10mm from SDRAM pin Table Trace Lengths for DQ, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 Net Structures TL0 TL1 Total R1 Notes Min Max Min Max Min Max Min Max Ohms ±5% 1, 2 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. These signals are referenced to ground. Table Trace Lengths for CB, DQS8, DQS8, and DM8 Net Structures TL0 TL1 Total R1 Notes Min Max Min Max Min Max Min Max Ohms ±5% 1, 2, 3 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. These signals are referenced to ground. 3. The DQS, DQS, and DM signals associated with the CB are matched to the CB length within a tolerance of ± 0.3 millimeters.

46 JEDED Standard No. 21C Page Figure Net Structure Routing for Data (Raw Card Version H) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 DIMM Connector TL0 R1 TL1 Table Trace Lengths for DQ, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 Net Structures TL0 TL1 Total R1 Notes Min Max Min Max Min Max Min Max Ohms ±5% 1, 2 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. These signals are referenced to ground. Release 18 Revision 3.1

47 Page Figure Net Structure Routing for Data (Raw Card Version J) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 DIMM Connector TL0 R1 TL1 Table Trace Lengths for DQ, DQS0 - DQS7, DQS0 - DQS7 and DM0 - DM7 Net Structures TL0 TL1 Total R1 Min Max Min Max Min Max Ohms Notes ±5% 1, 2, 3 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. Total Min and Total Max refer to the min and max respectively of TL0 + TL1. 3. These signals must be referenced to ground.

48 JEDED Standard No. 21C Page Figure Net Structure Routing for Data (Raw Card Version K) DQ0 - DQ63, DQS0 - DQS7, DQS0 - DQS7, and DM0 - DM7 For DQ0, DQ4, DQ59, and DQ63 test point on trace 4mm from SDRAM pin DIMM Connector TL0 R1 TL1 On pre-production modules, for DQS0, DQS0, DQS7, and DQS7 there is an opening in the solder mask 10mm from SDRAM pin Table Trace Lengths for DQ, DQS0 - DQS7, DQS0 - DQS7 and DM0 - DM7 Net Structures TL0 TL1 Total R1 Notes Min Max Min Max Min Max Min Max Ohms ±5% 1, 2 1. All distances are given in millimeters and must be kept within a tolerance of ± 0.3 millimeters. 2. These signals are referenced to ground. Release 18 Revision 3.1

49 Page Figure Net Structure Routing for S, CKE and ODT (Raw Card Version C) TL1 Test point at this VIA DIMM Connector TL0 TL0A C1 TL1 Test point at this VIA Table Trace Lengths for S, CKE, and ODT Net Structures TL1 C1 Signal TL0 TL0A Notes pf Min Max Min Max Min Max S ±5% 1 CKE ±5% 1 ODT ±5% 1 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters.

50 JEDED Standard No. 21C Page Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version D) DIMM Connector TL0 TL0B TL0A C1 Table Trace Lengths for S, CKE, and ODT Net Structures Signal CKE0, S0, ODT0 TL0 TL0A TL0B Min Max Min Max Min Max Min Max Min Max Min Max Min Max ±5% 1 C1 pf Notes 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. Release 18 Revision 3.1

51 Page Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version E) DIMM Connector TL0A TL0B TL1 C1 TL1 Test point at edge of module Table Trace Lengths for S, CKE, and ODT Net Structures Signal TL0A TL0B TL1 Min Max Min Max Min Max Min Max C1 pf Notes CKE ±5% 1 CKE ±5% 1 S ±5% 1 S ±5% 1 ODT ±5% 1 ODT ±5% 1 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters.

52 JEDED Standard No. 21C Page Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version F) DIMM Connector TL0 TL0A TL7 TL0B C1 TL7 C2 Table Trace Lengths for S, CKE, and ODT Net Structures TL0 TL0A TL0B TL7 C1 C2 Notes pf pf Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max ±5% 24±5% 1 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. Release 18 Revision 3.1

53 Page Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version G) Test point at via in middle of segment on end DRAM DIMM Connector TL0A TL0B C1 TL1 Table Trace Lengths for S, CKE, and ODT Net Structures Signal TL0A TL0B TL0A + TL0B TL1 Min Max C1 pf Notes CKE ±5% 1, 2, 3, 4 CKE ±5% 1, 2, 3, 4 S ±5% 1, 2, 3, 4 S ±5% 1, 2, 3, 4 ODT ±5% 1, 2, 3, 4 ODT ±5% 1, 2, 3, 4 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. 2. Test points are located in segments. 3. TL1,,, and are on the same layer and are stripline. 4. TL0 segments are routed with 0.15 millimeter traces.

54 JEDED Standard No. 21C Page Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version H) DIMM Connector TL0 C1 TL1 Table Trace Lengths for S, CKE, and ODT Net Structures Signal TL0 TL1 Min Max Min Max Min Max Min Max Min Max C1 ohm Notes CKE0, CKE1, S0, S1, ODT0, ODT pf±5% 1, 2, 3, 4 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. 2. Test points are located in segments. 3. TL1,, and are on the same layer and are stripline. 4. TL0 segments are routed with 0.15 millimeter traces. Release 18 Revision 3.1

55 Page Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version J) DIMM Connector TL0 TL0B TL0A C1 Table Trace Lengths for S, CKE, and ODT Net Structures Signal CKE0, S0, ODT0 TL0 TL0A TL0B Min Max Min Max Min Max Min Max Min Max Min Max Min Max ±5% 1 C1 pf Notes 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters.

56 JEDED Standard No. 21C Page Figure Net Structure Routing for S, CKE, and ODT (Raw Card Version K) DIMM Connector TL0A TL0B TL1 C1 TL1 Test point at edge of module Table Trace Lengths for S, CKE, and ODT Net Structures Signal TL0A TL0B TL1 Min Max Min Max Min Max Min Max C1 pf Notes CKE ±5% 1 CKE ±5% 1 S ±5% 1 S ±5% 1 ODT ±5% 1 ODT ±5% 1 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. Release 18 Revision 3.1

57 Page Figure Net Structure Routing for Address and Command (Raw Card Version C) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version C Test point at this VIA TL1 DIMM Connector TL0 R1 TL0A TL1 Test point at this VIA Table Trace Lengths for Address and Command Net Structures TL0 TL0A TL0 + TL0A TL1 Min Max Min Max Min Max Min Max Min Max Min Max R1 Ohms Notes ±5% 1, 2 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. 2. The total length of TL0 and TL0A must be within this limit.

58 JEDED Standard No. 21C Page Figure Net Structure Routing for Address and Command (Raw Card Version D) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version D Test point at the extreme right DRAM Test points are available for RAS, CAS, WE, A0 and A5 DIMM Connector TL0 R1 TL1 Table Trace Lengths for Address and Command Net Structures TL0 TL1 TL0+TL1 R1 Ohms Notes Min Max Min Max Min Max Min Max Min Max Min Max Min Max ± 5% 1, 2 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. 2. TL0 and TL1 include TBD compensation per via when applicable. Release 18 Revision 3.1

59 Page Figure Net Structure Routing for Address and Command (Raw Card Version E) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version E Test point at this VIA DIMM Connector TL0 R1 TL1 Table Trace Lengths for Address and Command Net Structures TL0 TL1 TL0 + TL1 Min Max Min Max Min Max Min Max Min Max Min Max Min Max R1 Ohms Notes ±5% 1 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters.

60 JEDED Standard No. 21C Page Figure Net Structure Routing for Address and Command (Raw Card Version F) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version F Test point at the extreme right DRAM DIMM Connector TL0 R1 TL1 (ECC) Test point at the extreme right DRAM Table Trace Lengths for Address and Command Net Structures TL0 TL1 TL0+TL1 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max R1 Ohms Notes ±5% 1, 2 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. 2. The total length of TL0 and TL1 must be within this limit. Release 18 Revision 3.1

61 Page Figure Net Structure Routing for Address and Command (Raw Card Version G) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version G Test point at this VIA DIMM Connector TL0 R1 TL1 (ECC) (ECC) Table Trace Lengths for Address and Command Net Structures Signal TL0 TL1 TL0 + TL1 Min Max Min Max Min Max Min Max Min Max Min Max Min Max R1 Ohms Notes A0, A10, A12, A13, A4, A7, A8, BA0, BA2 A1, A11, A14, A15, A2, A5, A6, A9, BA1, CAS, RAS, WE ±5% ±5% 1 A ±5% 1 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters.

62 JEDED Standard No. 21C Page Figure Net Structure Routing for Address and Command (Raw Card Version H) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version H DIMM Connector TL0 R1 TL1 Release 18 Revision 3.1

63 Page Figure Net Structure Routing for Address and Command (Raw Card Version J) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version J Test point at the extreme right DRAM Test points are available for RAS, CAS, WE, A0 and A5 DIMM Connector TL0 R1 TL1 Table Trace Lengths for Address and Command Net Structures TL0 TL1 TL0+TL1 R1 Ohms Notes Min Max Min Max Min Max Min Max Min Max Min Max Min Max ± 5% 1, 2 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. 2. TL0 and TL1 include TBD compensation per via when applicable.

64 JEDED Standard No. 21C Page Figure Net Structure Routing for Address and Command (Raw Card Version K) A0 - A15, BA0 - BA2, RAS, CAS, WE for Raw Card Version K Test point at this VIA DIMM Connector TL0 R1 TL1 Table Trace Lengths for Address and Command Net Structures TL0 TL1 TL0 + TL1 Min Max Min Max Min Max Min Max Min Max Min Max Min Max R1 Ohms Notes ±5% 1 1. All distances are given in millimeters and should be kept within a tolerance of ± 0.3 millimeters. Release 18 Revision 3.1

65 Page Cross Section Recommendations DIMM printed circuit board designs (Raw Cards C, D, E, F H, J, and K) use six-layers of glass epoxy material. Raw Card G uses an eight-layer PCB. The PCB stackup must be designed with 4-mil wide traces. Note: The PCB edge connector contacts shall be gold-plated and not chamfered. Figure PCB Electrical Specifications Parameter Min Max Units Trace velocity: S0 (outer layers) ps/mm Trace velocity: S0 (inner layers) ps/mm Trace impedance: Z0 (all layers) Ohms Figure Example Layer Stackup for 6 Layers and 4 mil Traces 0.10mm 0.12mm 0.62mm 0.12mm 0.10mm Signal Layer 1 Signal Layer 3 Signal Layer 4 Signal Layer 6 Ground Layer 2 Voltage Layer 5 Figure Example Layer Stackup for 8 Layers and 4 mil Traces 0.10mm 0.25mm 0.13mm 0.14mm 0.36mm 0.14mm 0.10mm Signal Layer 1 Signal Layer 3 Signal Layer 5 Signal Layer 6 Signal Layer 8 Split Plane Layer 1 Split Plane Layer 2 Split Plane Layer 3 Note: The 8-layer stackup is only used in Raw Card G

66 JEDED Standard No. 21C Page Decoupling Decoupling capacitor locations have been provided to accommodate different memory component outlines. Differing DRAM package solutions may require adjustment of the capacitor form factor. The number of capacitor sites that must be populated varies depending on DRAM die decoupling design. All Vref decoupling locations (sites) should be populated with 100nF capacitors. The tables below should be used as a minimum requirement for populating the capacitor sites on different DIMM designs. These tables are not a substitute for proper power delivery design. Decoupling capacitor values vary by module and may be staggered to achieve the best overall impedance vs. frequency response. Depending on the DRAM package size, not all placements may be possible. Table should be used when DRAM devices populated on the DIMM have greater than 200pF (x8 devices) of ondie VDDQ/VSSQ DRAM capacitance (>400pF for x16 devices). Table should be used as a baseline for DRAM devices that have less 200pF of on-die VDDQ/VSSQ DRAM capacitances (<400pF for x16 devices). Table Raw Card Version Capacitor Sites to Populate for DRAMs with Greater Than 200pF of On-Die VDDQ/VSSQ Decoupling Capacitance Sites Above DRAMs Between DRAMs 2 Below DRAMs 2 C All sites populated Not required 15 Sites populated All sites populated D All sites populated Not required All sites populated All sites populated E All sites populated Not required Half the sites populated Half the sites populated F All sites populated Not required All sites populated All sites populated G All sites populated Not required Half the sites populated Half the sites populated H All sites populated Not required Half the sites populated Half the sites populated J All sites populated Not required Half the sites populated Half the sites populated K All sites populated Not required Half the sites populated Half the sites populated 1. Recommended values for bulk decoupling are 1.0µf, 2.2µf, 3.3µf, and 4.7µf. 2. Recommended values for decoupling are 0.01µf, 0.022µf, 0.047µf, 0.1µf, and 0.22µf. Release 18 Revision 3.1

67 Page Table Raw Card Version Capacitor Sites to Populate for DRAMs with Less Than 200pF of On-Die VDDQ/VSSQ Decoupling Capacitance Sites Above DRAMs 2 Between DRAMs 2 Below DRAMs 2 C All sites populated All sites populated All sites populated All sites populated D All sites populated All sites populated All sites populated All sites populated E All sites populated All sites populated All sites populated All sites populated F All sites populated All sites populated All sites populated All sites populated G All sites populated All sites populated All sites populated All sites populated H All sites populated All sites populated All sites populated All sites populated J All sites populated All sites populated All sites populated All sites populated K All sites populated All sites populated All sites populated All sites populated 1. Recommended values for bulk decoupling are 1.0µf, 2.2µf, 3.3µf, and 4.7µf. 2. Recommended values for decoupling are 0.01µf, 0.022µf, 0.047µf, 0.1µf, and 0.22µf.

68 JEDED Standard No. 21C Page Figure Test Point Identification (Raw Card Version C) Raw Card Version C is a single-sided design. All test points are vias accessible from the back side. All SDRAM locations on this raw card have essentially the same test points and therefore any can be used as probe point. The following figure of the backside of the card identifies these test points for the memory component on the left when viewed form the front. Release 18 Revision 3.1

69 Page Figure Test Point Identification (Raw Card Versions D and F): Back View The figure below shows test point locations for Raw Card D and Raw Card F. The differences between the board files are that Raw Card D is non-ecc and Raw Card F is ECC. One picture is shown from Raw Card D. The same image from Raw Card F would look identical. The test points identified are available for all DRAM locations. The test points are the vias closest to the DRAM pins. It most cases the vias exist because of the routing requirements. In some cases the vias are added specifically to provide a test point close to the DRAM pin. DQ and DQS pins are in the latter category. All probing is from the back of the board. Ground is in green. VDD is in red. The blue area is VREF. This is a backside view of the board. The DRAM outlines are present for convenience. No components are placed on this side of the board. The test points are repeated for each DRAM site. The address, command and control signals would remain the same. The DQ and DQS pins would reflect a different byte lane.

70 JEDED Standard No. 21C Page Figure Test Point Identification (Raw Card Version E): Front View For Raw Card E, the test points are spread across the module. The first figure indicates the areas where the test points are located. The subsequent figures provide a more detailed view of where the specific test points can be identified. Figure Test Point Identification (Raw Card Version E) Details A, B, and C: Front View Detail A Detail B Detail C Release 18 Revision 3.1

71 Page Figure Test Point Identification (Raw Card Version E): Back View The figure below indicates the back side of the areas where the test points are located. The subsequent figures provide a more detailed view of where the specific test points can be identified.

72 JEDED Standard No. 21C Page Figure Test Point Identification (Raw Card Version E) Details D and E: Back View Detail D Detail E Release 18 Revision 3.1

73 Page Figure Test Point Identification (Raw Card Version G): Front, Right Side View The figure below indicates the majority of the test points that can be accessed from the front side of the module. The address and command nets are accessible at the split point on the 8-component side. The control nets for the second rank can also be accessed from this side; although, only the vias are available. One DQ net, DQ59, is available at this edge of the module, as are the associated strobes. For production modules, it will be necessary to scrape the soldermask away to allow electrical access to the strobes. Clock nets CK2, CK2 are accessible at the termination resistor.

74 JEDED Standard No. 21C Page Figure Test Point Identification (Raw Card Version G): Front, Left Side View On the front, left side of the module, an additional DQ net and associated strobes are accessible, as indicated below. Release 18 Revision 3.1

75 Page Figure Test Point Identification (Raw Card Version G): Back, Left Side View The figure below identifies the majority of the test points found on the front, right side of the module. One exception from the back, left side view is a different DQ net, DQ63. The associated strobes are not accessible from this side.

76 JEDED Standard No. 21C Page Figure Test Point Identification (Raw Card Version G): Back, Right Side View The figure below shows an additional DQ net, DQ4, found on the back, right side of the module. Release 18 Revision 3.1