Address Summary Table: 1GB 2GB 4GB Module Configuration 128M x M x M x 64
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1 1GB WD3UN01G / WL3UN01G 2GB WD3UN02G / WL3UN02G 4GB WD3UN04G / WL3UN04G Features: 240-pin Unbuffered Non-ECC for DDR3-1066, DDR3-1333, DDR and DDR3-166 JEDEC standard V DDL =1.35V (1.2V-1.45V); VDD=1.5V (+/ V) power supply Single rank 1GB, 2GB and 4GB module. Modules are built with x DDR3 SDRAM devices in FBGA-2(7+4) Pb-Free package Programmable CAS latency of 7, 9, 11and 13. Fixed burst length of and burst chop of 4 via the mode register Adjustable data-output drive strength Bi-directional differential data strobe On-die termination using ODT pin SPD (Serial Presence Detect) with EEPROM Fly-by topology All contacts are gold plated ROHS compliant Figure 1: Available profile Standard: 1.11" Description: The following specification covers the family of One-Rank Unbuffered Non-ECC DDR3 modules using x FBGA SDRAMs. Please reference Figure 1 for available layout configurations and the product ordering guide on the final page of this specification for available options including speed grade and silicon manufacturer. Speed Grades: Speed Grade Data Rate (MHz) Clock/Data Rate Latency Module Speed CL7 CL9 CL11 CL ns/1066MTs PC ns/1333MTs PC ns/1600MTs PC ns/166MTs PC Address Summary Table: 1GB 2GB 4GB Module Configuration 12M x M x M x 64 Device Configuration 12M x ( components) 256M x ( components) 512M x ( components) Refresh K K K Device bank Address (BA0-BA2) (BA0-BA2) (BA0-BA2) Row Addressing A0-A13 A0-A14 A0-A14 Column Addressing A0-A9 A0-A9 A0-A9 Module Rank *Specifications are for reference purposes only and are subject to change by Wintec without notice. 2014Wintec Industries, Inc. 1
2 X64 DIMM Pin Configurations: Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF DQ NC 162 NC 2 DQ VSS 122 DQ4 43 NC DM4 3 DQ0 123 DQ NC 4 DQS4# 204 NC 4 DQ NC 165 NC 5 DQS VSS 125 DM0 46 NC DQ3 6 DQS0# 126 NC TEST 7 DQ DQ39 7 DQS NC 16 RESET# DQ35 20 VSS 12 DQ6 KEY DQ44 9 DQ2 129 DQ7 49 NC 169 NC 90 DQ DQ45 10 DQ CKE0 170 VDD 91 DQ VSS 131 DQ12 51 VDD 171 NC DM5 12 DQ 132 DQ13 52 BA2 172 NC/A14 93 DQS5# 213 NC 13 DQ NC 173 VDD 94 DQS VSS 134 DM1 54 VDD 174 A DQ46 15 DQS1# 135 NC 55 A A9 96 DQ DQ47 16 DQS A7 176 VDD 97 DQ VSS 137 DQ14 57 VDD 177 A 9 21 DQ52 1 DQ10 13 DQ15 5 A5 17 A6 99 DQ4 219 DQ53 19 DQ A4 179 VDD 100 DQ VSS 140 DQ20 60 VDD 10 A DM6 21 DQ DQ21 61 A2 11 A1 102 DQS6# 222 NC 22 DQ VDD 12 VDD 103 DQS VSS 143 DM2 63 CK1/NC 13 VDD DQ54 24 DQS2# 144 NC 64 CK1#/NC 14 CK0 105 DQ DQ55 25 DQS VDD 15 CK0# 106 DQ VSS 146 DQ22 66 VDD 16 VDD DQ60 27 DQ1 147 DQ23 67 VREFCA 17 NC 10 DQ56 22 DQ61 2 DQ NC 1 A0 109 DQ VSS 149 DQ2 69 VDD 19 VDD DM7 30 DQ DQ29 70 A BA1 111 DQS7# 231 NC 31 DQ BA0 191 VDD 112 DQS DM3 72 VDD 192 RAS# DQ62 33 DQS3# 153 NC 73 WE# 193 S0# 114 DQ5 234 DQ63 34 DQS CAS# 194 VDD 115 DQ DQ30 75 VDD 195 ODT VDDSPD 36 DQ DQ31 76 NC 196 A SA0 237 SA1 37 DQ NC 197 VDD 11 SCL 23 SDA 3 15 NC 7 VDD 19 NC 119 SA NC 159 NC 79 NC VTT 240 VTT 40 NC DQ NC 1 DQ DQ37 NC - No Connect; NF No Function; NU Not Usable; RFU Reserved Future Use TEST (pin 167) used by memory bus analysis tools. 2014Wintec Industries, Inc. 2
3 Pin Locations: Pin1 Pin4 Pin49 Pin120 Pin121 Pin16 Pin169 Pin pin DIMM Pin Description: Pin Name Description Pin Name Description A0-A14 Address input (Multiplexed) CK0, CK0#, CK1, CK1# Clock input BA0-BA2 Bank select address S0# Chip Select RAS# Row address strobe SCL Serial clock CAS# Column address strobe SDA Serial Data I/O WE# Write enable SA0-SA2 Address in EEPROM CKE0 Clock Enable VDD Power supply DQ0 DQ63 Data input/output VREF Power supply for reference DQS0 DQS7 Data strobe input/output VSS Ground DM0 DM7 Data mask VDDSPD Serial EEPROM power supply ODT0 On-die termination line VTT I/O Termination Supply RESET# Reset Pin NC No Connection 2014Wintec Industries, Inc. 3
4 Input/Output Functional Description: Symbol Type Function CK[1:0] CK[1:0]# CKE0 S0# SSTL ODT0 RAS#, CAS#, WE# VREF VDDQ BA[2:0] A0-A14 DQ[63:0] DM[7:0] VDD, VSS DQS[7:0] DQS#[7:0] SA[2:0] - SDA - SCL - VDDSPD RESET# - CK and CK# are differential clock inputs. All the DDR3 SDRAM address/control inputs are SSTL sampled on the crossing of positive edge of CK and negative edge of CK#. Output data is reference to the crossing of CK and CK#. CKE HIGH activates, and CKE Low deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE SSTL POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue. These input signals also disable all output (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When S0 is high, all register outputs (except CKE, ODT and Chip select) remain in the previous state. SSTL On-Die Termination control signal When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the SSTL operation to be executed by the SDRAM Supply Reference voltage for SSTL15 command/address inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise Supply immunity SSTL Select which SDRAM bank of four or eight is activated During a Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke auto-precharge operation at the end of the burst read or write cycle. If AP is high, auto-precharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If SSTL AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge SSTL Data and Check Bit Input/Output pins SSTL Masks write data when high, issued concurrently with input data Supply Power and ground for the DDR SDRAM input buffers and core logic SSTL Positive line of the differential data strobe for input and output data SSTL Negative line of the differential data strobe for input and output data These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. Supply EEPROM supply is operable from 3.0V to 3.6V The RESET# pin is connected to the RST# pin on each DRAM. When low, all DRAMs are set to a know state 2014Wintec Industries, Inc. 4
5 Functional Block Diagram: One Rank 12M x 64 (1GB), 256M x 64 (2GB), or 512M x 64 (4GB) DDR3 Unbuffered DIMM (x organization) S0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DQ[0:7] U1 DQ[32:39] U5 DQS1 DQS1# DM1 DQS5 DQS5# DM5 DQ[:15] U2 DQ[40:47] U6 DQS2 DQS2# DM2 DQS6 DQS6# DM6 DQ[16:23] U3 DQ[4:55] U7 DQS3 DQS3# DM3 DQS7 DQS7# DM7 DQ[24:31] U4 DQ[56:63] U BA0-BA2 A0-A13 RAS# CAS# WE# CKE0 ODT0 RESET# BA0-BA2 to U1 U A0-A13 to U1 U RAS# to U1 U CAS# to U1 U WE# to U1 U CKE to Rank 0 ODT to Rank 0 RESET# to U1 U9 CK0 CK0# Rank 0 SCL WP VDDSPD VDD/VDDQ VREF VREF CA SERIAL PD A0 A1 A2 To SPD To U1 U To U1 U To U1 U To U1 U SDA SA0 SA1 GND Notes: 1. ball on each DDR3 component is connected to an external 240 Ohm resistor that is tied to ground. Used for the calibration of the component s on-die termination and output driver. 2014Wintec Industries, Inc. 5
6 Absolute Maximum Ratings: Exposure to stresses greater than these absolute maximum rating conditions for extended periods may affect reliability of the module. Symbol Parameter Min Max Units V DD, V DD Q V DD and V DD Q supply voltage relative to V SS V V IN, V OUT Voltage on any pin relative to V SS V T STG Storage temperature (T case ) C T OPR Operating Temperature (ambient) C Note: 1. Operating Temperature T OPR is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD The Normal Temperature range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-5 C under all operating conditions 3. Some applications require operation of the extended temperature range between 5 C and 95 C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9us. It is also possible to specify a component with 1X refresh (trefi to 7.us) in the extended temperature range. b) If self-refresh option is required in the extended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional auto self-refresh mode (MR2 A6 = 1b and MR2 A7 = 0b) DC Operating Conditions: Parameter Symbol Min Typical Max Units Supply Voltage V DD V V DDL V Ground V SS V Input High Voltage V IH,CA V REF V DD V Input Low Voltage V IL,CA V SS - V REF V 2014Wintec Industries, Inc. 6
7 Electrical Characteristics and AC Timings: V DD = +1.5V ± 0.075V, V DD Q = +1.5V ± 0.075V, V SS = 0V DDR3-00,1066,1333, 1600MTs, 64-bit Parameter Symbol Unit DDR DDR DDR DDR3-166 Min. Max. Min. Max. Min. Max. Min. Max. Average Clock period tck ns Average high pulse width tch tck Average low pulse width tcl tck DQS,DQS# to DQ skew tdqsq ps DQ output hold time tqh tck DQ low-impedance time tlz ps DQ high-impedance time thz ps DQ and DM input hold time tds ps DQ and DM input setup time tdh ps DQ and DM input pulse width tdipw ps Read Preamble trpre tck Read Postamble trpst tck Output high time tqsh tck Output low time tqsl tck Write preamble twpre tck Write postamble twpst tck DQS output access time from CK,CK# tdqsck ps DQS input low/high pulse width tdqsl/h tck Write command to 1 st DQS latching tdqss tck transition 0.25 DQS falling edge to CK setup time tdss tck DQS falling edge hold time from CK tdsh tck Internal Read to Precharge command delay trtp Internal write to read command delay twtr Write recovery time twr ns Mode register set command cycle time tmrd tck CAS# A to CAS# B command period tccd nck Auto Precharge write recovery+ Precharge time tdal WR+roundup(tRP/tCK(avg)) nck Active to Precharge command tras ns Active bank A to Active bank B command trrd ns Address and control input setup time tis ps Address and control input hold time tih ps Four activate window for 2KB page size tfaw ns Control and address input pulse width tipw ps 2014Wintec Industries, Inc. 7
8 V DD = +1.5V ± 0.075V, V DD Q = +1.5V ± 0.075V, V SS = 0V DDR3-00,1066,1333, 1600MTs, 64-bit Parameter Symbol DDR DDR DDR DDR3-166 Unit Min. Max. Min. Max. Min. Max. Average periodic refresh interval trefi Read command to 1 st data taa ns 5 Internal read or write delay time trcd ns 5 PRE command period trp ns 5 ACT to ACT command period trc ns 5 ODT turn-on (Power- down mode) taonpd ps ODT turn-on taon ps 225 ODT turn-off taof tck Note: The timing parameters are applicable to all 3 chip manufacturers Samsung, Micron, Infineon. 2014Wintec Industries, Inc.
9 Physical Dimensions Standard: 1.11" Height DDR3 Unbuffered DIMM One physical rank, components x organised 0.12/(3.04) 0.171/(4.34) 1./(47.4) 2.3/(71.9) Pin121 Pin16 Pin169 Pin /(3.0) 0.106/(2.7) Max BACK SIDE 5.250/(133.35±0.15) 1.12/(30.03) 0.6/(17.32) 0.364/(9.22) 0.050±0.004/ (1.27±0.1) SIDE Pin1 Pin4 Pin49 Pin /(1.0) 2.12/(53.94) 0.031/(0.0) 4./(123.94) FRONT SIDE Note: 1. Dimensions are in inches/(mm) 2. Outline dimensions and tolerances are in accordance with the JEDEC standard 2014Wintec Industries, Inc. 9
10 Ordering Guide: DDR3-1066, 1333, 1600, 166MTs One-Rank x, Unbuffered Non-ECC UDIMM WD3UN/WL3UN XXX YYY ZZ- AAA DDR3-00,1066,1333, 1600MTs, 64-bit W D3 L3 UN Wintec 1.5V DDR3 SDRAM 1.35V DDR3 SDRAM Unbuffered Non-ECC, X, -Chips, 1-Rank XXX YYY ZZ 01G 1GB 10J CL=7 S Samsung A A-Die 02G 2GB 13L CL=9 M Micron B B-Die 04G 4GB 16N CL=11 H Hynix C C-Die 1P CL=13 D D-Die Q Q-Die AAA Customer reference Configuration/Availability: Density Part Number Speed DRAM/Die 1GB WD(L)3UN01G 10J, 13L, 16N, 1P ZZ 2GB WD(L)3UN02G 10J, 13L, 16N, 1P ZZ 4GB WD(L)3UN04G 10J, 13L, 16N, 1P ZZ Customer Reference - AAA Example: WD3UN02G13LSQ-AAA 240-Pin DDR3 2GB 1.5V CL9 Non-ECC UDIMM 1.11 Samsung Q-Die for AAA Contact Us: Wintec Industries OEM Group 675 Sycamore Drive Milpitas, CA Ph: Fax: oemsales@wintecind.com Wintec Industries, Inc. 10
11 Revision History: Revision 1.0 (July 2012) Initial Release Revision 1.1 (January 2014) Typo corrections About Wintec Industries, Inc. Wintec, founded in 19, is headquartered in Milpitas, California. Wintec, a leading third party memory module manufacturer, specializes in a variety of module design and manufacturing, such as memory module, flash module, Handspring module, modem module, game module, etc. Besides a complete line of DDR, SDR, and EDO/FPM legacy memory modules, Wintec also distribute CPU, motherboard, peripherals, PC software, and consumer Flash products (such as MMC, SD, SMC, Compact Flash, PC Card, etc.). With excellent design engineering and manufacturing capability, Wintec provides a wide range of design and manufacturing services for our valuable customers from concept design to final product delivery. Wintec is ISO9001-certified. Important Notice Wintec Industries, Inc. makes no representations or warranties with respect to the contents of this User Guide and specifically disclaims any implied warranties of any product design for any particular purpose. Wintec Industries, Inc. reserves the rights to revise this publication and to make changes from time to time in the content hereof without obligation of Wintec Industries, Inc. to notify any person or organization of such revisions or changes 2014Wintec Industries, Inc. 11
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