Early Developments: From Difference Engine to IBM 701

Transcription

1 February 3, , L1-1 February 3, , L1-2 Early Developments: From Difference Engine to IBM 701 Laboratory for Computer Science M.I.T.

2 Charles Babbage Lucasian Professor of Mathematics Cambridge University, February 3, , L1-3 Difference Engine 1823 Analytic Engine 1833 The forerunner of modern digital computer! Application? Mathematical Tables - Astronomy Nautical Tables - Navy Background Any continuous function can be approximated by a polynomial --- Weierstrass Technology mechanical - gears, Jacquard s loom, simple calculators Difference Engine A machine to compute mathematical tables Weierstrass: - Any continuous function can be approximated by a polynomial - Any Polynomial can be computed from difference tables An example, f (n) = n 2 +n+41 d1(n) = f(n) - f(n-1) = 2n d2(n) = d1(n) - d1(n-1) = 2 f(n) = f(n-1) + d1(n) = f(n-1) + (d1(n-1) + 2) n d2(n) d1(n) 2 4 f(n) February 3, , L1-4 all you need is an adder!

3 February 3, , L1-5 Difference Engine Babbage s paper is published The paper is read by Scheutz & his son in Sweden Babbage gives up the idea of building it; (he is onto Analytic Engine!) Scheutz displays his machine at the Paris World Fare - Can compute any 6th degree polynomial - Speed: 33 to digit numbers per minute! Now the machine is at the Smithsonian Analytic Engine Babbage s paper is published conceived during a hiatus in the development of the difference engine Inspiration:Jacquard Looms looms controlled by punched cards The set of cards with fixed punched holes dictated the pattern of weave program The same set of cards could be used with different colored threads numbers Babbage dies - the machine remains unrealized. It is not clear if the analytic engine could be built even today using only mechanical technology February 3, , L1-6

4 Analytic Engine The first conception of a general purpose computer February 3, , L The store in which all variables to be operated upon, as well as all those quantities which have arisen from the results of the operations are placed. 2. The mill into which the quantities about to be operated upon are always brought. The program Operation variable1 variable2 variable3 An operation in the mill required feeding two punched cards and producing a new punched card for the store. An operation to alter the sequence was also provided! The first programmer Ada Byron aka Lady Lovelace February 3, , L1-8 Babbage s ideas had a lot of influence later, primarily because of Luigi Menabrea, who published notes of Babbage s lectures in Italy Lady Lovelace, who translated Menabrea s notes in English and thoroughly expanded them.... Analytic Engine weaves algebraic patterns... Ada s tutor was Babbage himself! In the early twentieth century - the focus shifted to analog computers but Harvard Mark I built in 1944 is very close in spirit to the Analytic Engine.

5 Linear Equation Solver John Atanasoff, Iowa State University February 3, , L s: Atanasoff built the Linear Equation Solver. It had 300 tubes! Application: Linear and Integral differential equations Background: Vannevar Bush s Differential Analyzer --- an analog computer Technology: Tubes and Electromechanical relays Atanasoff decided that the correct mode of computation was by electronic digital means. ENIAC 1946, 48 EDVAC 1948 concept only February 3, , L1-10 ENIAC and EDVAC The first conception of a stored program computer Players brought together by the WW-2 effort - Eckert & Mauchley, University of Pennsylvania - John von Neumann, Princeton University Application: Ballistic calculations angle = f (location, tail wind, cross wind, air density, temperature, weight of shell, propellant charge,... ) Technology: tubes, relays, electromechanical delays, mercury delay lines,... Developed the concept of stored program computer program can be manipulated as data

6 Stored Program Computer Program = A sequence of instructions How to control instruction sequencing? February 3, , L1-11 manual control calculators automatic control external (paper tape) Harvard Mark I, 1944 Zuse s Z1, WW2 internal plug board ENIAC 1946 read-only memory ENIAC 1948 read-write memory EDVAC 1947 (concept ) The same storage can be used to store program and data EDSAC 1950 Maurice Wilkes Technology Issues February 3, , L1-12 ENIAC EDVAC 18,000 tubes 4,000 tubes digit numbers 2000 word storage mercury delay lines ENIAC had many asynchronous parallel units but only one was active at a time BINAC : Two processors that checked each other for reliability. Didn t work well because processors never agreed

7 The Spread of Ideas February 3, , L1-13 ENIAC & EDVAC had immediate impact brilliant engineering: Eckert & Mauchley lucid paper: Burks, Goldstein & von Neumann IAS Princeton Bigelow EDSAC Cambridge Wilkes MANIAC Los Alamos Metropolis JOHNIAC Rand ILLIAC Illinois Argonne SWAC UCLA-NBS UNIVAC - the first commercial computer, 1951 Alan Turing s direct influence on these developments is still being debated by historians. Dominant Problem: Reliability February 3, , L1-14 Mean time between failures (MTBF) MIT s Whirlwind with an MTBF of 20 min. was perhaps the most reliable machine! Reasons for unreliability: 1. Vacuum Tubes 2. Storage medium acoustic delay lines mercury delay lines Williams tubes Selections CORE J. Forrester 1954

8 Commercial Activity February 3, , L1-15 IBM s SSEC Selective Sequence Electronic Calculator 150 word store. Instructions, constraints, and tables of data were read from paper tapes. 66 Tape reading stations! Tapes could be glued together to form a loop! Data could be output in one phase of computation and read in the next phase of computation. And then there was IBM 701 February 3, , L1-16 IBM machines were sold in IBM a cheaper, drum based machine, more than 120 were sold in 1954 and there were orders for 750 more! Users stopped building their own machines. Question: Answer: Why was the IBM late getting into computer technology? Their revenues were doubling every 4-5 years in 40 s and 50 s even without computers!

9 Software Developments February 3, , L1-17 up to 1955 Libraries of numerical routines Floating point operations Transcendental functions Matrix manipulation, equation solvers, High level Languages - Fortran 1956 Operating Systems - Assemblers, Loaders, Linkers, Compilers Accounting programs to keep track of usage and charges Machines required experienced operators Most users could not be expected to understand these programs, much less write them Machines had to be sold with a lot of resident software Technology Factors that Influence Computer Architecture February 3, , L1-18 Applications Computer Architecture Software Compatibility Software played almost no role in defining an architecture before mid fifties. special-purpose versus general-purpose machines

10 Microprocessors Economics In mid nineties Designing a state-of-the-art microprocessor requires a huge design team Pentium ~300 engineers PentiumPro ~ 500 engineers February 3, , L1-19 Huge investments in fabrication lines need to sell 2 to 4 million units to be profitable Continuous improvements are needed to improve yeilds and clock speed price drops to one tenth in 2-3 years Fast new processors also require new peripheral chips (memory controller, I/O) $$$ Cost of launching a new ISA is prohibitive and the advantage is not so clear! Compatibility February 3, , L1-20 Essential for portability and competition Its importance increases with the market size but it is also the most regressive force What does compatibility mean? Instruction Set Architecture (ISA) compatibility The same assembly program can run on any upward compatible model then IBM 360/ now Intel x86 System and application software developers expect more than ISA compatibility (API s) applications operating system proc + mem + I/O Wintel Java?

11 Technology-Driven Views of Computer Architecture - 1 Implement an (old) ISA in new technology using new micro-architectures February 3, , L1-21 An iterative process select some new features design datapaths and control estimate cost measure performance on simulators Sought after expertise Understanding of micro-architectures Hardware and circuit design Simulation, verification & testing Back-end compilers and performance evaluation Technology-Driven Views of Computer Architecture - 2 February 3, , L1-22 # transistors per chip 100M 1M time What exciting things can we do with the latest technology. Consider a 64-bit RISC processor,1997 vintage: 4-way superscaler, I & D L1 caches, L2 controller out-of-order and speculative execution,... 6M trans. Will future billion transister chip contain more of the same (i.e., mostly caches)? multiprocessors (i.e., SMP s sans DRAM)? full systems = processor(s)+dram+i/o?

12 Language-Driven View of Computer Architecture Since software is the most costly activity, design machines to support high-level languages February 3, , L1-23 Language designers consider abstractions for - expressiveness - enhanced programmability - portability - insulation from small changes in hardware Architects provide hardware mechanisms to support these abstractions in a cost effective manner The field is littered with some instructive and spectacular failures of language-driven architectures e.g., Stack machines, Lisp Machines,... Language/ Compiler/ System software designer My view Architect/Hardware designer February 3, , L1-24 Need mechanisms Decompose each to support important mechanism into essential abstractions micro-mechanisms and determine its feasibility and cost effectiveness Determine compilation Propose mechanisms and strategy; new language features for performance abstractions Architects main concerns are cost-performance, performance, and efficiency in supporting a broad class of software systems.

13 February 8, , L2-1 Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 Laboratory for Computer Science M.I.T. Importance of Technology February 8, , L2-2 New technologies not only provide greater speed, size and reliability at lower cost, but more importantly these dictate the kinds of structures that can be considered and thus come to shape our whole view of what a computer is. Bell & Newell Page 1

14 Technology is the dominant factor in computer design February 8, , L2-3 Technology Transistors Integrated circuits VLSI (initially) Laser disk, CD s Technology Core memories magnetic tapes disks Technology ROMs, RAMs VLSI Packaging Low Power Computers Computers Computers But Software... February 8, , L2-4 As people write programs and use computers, our understanding of programming and program behavior improves. This has profound though slower impact on computer architecture Technology Software Computer Architecture Modern architects cannot avoid paying attention to compiling issues. Page 2

15 Computers in mid 50 s February 8, , L2-5 Hardware was expensive Programmer s view of the machine was inseparable from the actual hardware implementation Example: IBM a drum machine with 44 instructions Load the contents of location 1234 into the distribution; put it also into the upper accumulator; set lower accumulator to zero; and then go to location 1009 for the next instruction. Good programmers optimized the placement of instructions on the drum to reduce latency 2. Branch on distribution digit equal to 8 Computers in mid 50 s (cont) February 8, , L2-6 Stores were small (1000 words) and 10 to 50 times slower than the processor 1. Instruction execution time was totally dominated by the memory reference time. More memory references per instruction longer execution time per instruction 2. The ability to design complex control circuits to execute an instruction was the central concern as opposed to the speed of decoding or ALU. 3. No resident system-software because there was no place to keep it! Page 3

16 February 8, , L2-7 The Earliest Instruction Sets Single Accumulator - A carry-over from the calculators. LOAD x AC M[x] STORE x M[x] (AC) ADD x AC (AC) + M[x] SUB x MUL x Involved a quotient register DIV x SHIFT LEFT SHIFT RIGHT AC 2 (AC) JUMP x PC x JGE x if (AC) 0 then PC x LOAD ADR x AC Extract address field(m[x]) STORE ADR x Typically less than 2 dozen instructions! Programming a Single Accumulator Machine February 8, , L2-8 C i A i + B i 1 i n A LOOP LOAD N JGE DONE ADD ONE STORE N F1 LOAD A F2 ADD B F3 STORE C JUMP LOOP DONE HLT How to modify the addresses A, B and C? B C N - n ONE 1 code Page 4

17 Self-modifying Code C i A i + B i 1 i n February 8, , L2-9 LOOP LOAD N JGE DONE ADD ONE STORE N F1 LOAD A F2 ADD B F3 STORE C LOAD ADR F1 ADD ONE STORE ADR F1 modify the LOAD ADR F2 program ADD ONE for the next STORE ADR F2 iteration LOAD ADR F3 ADD ONE STORE ADR F3 JUMP LOOP DONE HLT Each iteration involves total book- -keeping instruction fetches operand fetches 10 8 stores 5 4 Memory February 8, , L2-10 Bottleneck Processor Early Solutions fast local storage in the processor, i.e., 8-16 registers as opposed to one accumulator indexing capability to reduce book keeping instructions complex instructions to reduce instruction fetches compact instructions, i.e., implicit address bits for operands, to reduce fetches Page 5

18 Processor State February 8, , L2-11 The information held in the processor at the end of an instruction to provide the processing context for the next instruction. e.g. Program Counter, Registers,... Programmer visible state of the processor plays a crucial role in computer organization for both software reasons: hardware reasons: efficient use if the processing of an instruction can be interrupted than the state has to be saved and restored Index Registers Tom Kilburn, Manchester University, mid 50 s One or more specialized registers to simplify address calculation February 8, , L2-12 Modify existing instructions LOAD x, IX AC M[x + (IX)] ADD x, IX AC (AC) + M[x + (IX)]... Add new instructions to manipulate index registers JZi x, IX if (IX)=0 then PC x else IX (IX) + 1 LOADi x, IX IX M[x] (truncated to fit IX)... Index registers have accumulator-like characteristics Page 6

19 C i A i + B i Using Index Registers 1 i n February 8, , L2-13 LOADi -n, IX LOOP JZi DONE, IX LOAD LASTA, IX ADD LASTB, IX STORE LASTC, IX JUMP LOOP DONE HALT A LASTA Program does not modify itself Efficiency has improved dramatically (ops / iter) with index regs without index regs instruction fetch 5 (2) 17 (14) operand fetch 2 10 (8) store 1 5 (4) Costs: Instructions are 1 to 2 bits longer Index registers with ALU-like circuitry Complex control Indexing vs. Index Registers February 8, , L2-14 LOAD x, IX Suppose instead of registers, memory locations are used to implement index registers. Arithmetic operations on index registers can be performed by bringing the contents to the accumulator Most book keeping instructions will be avoided but each instruction will implicitly cause several fetches and stores complex control circuitry Page 7

20 Operations on Index Registers February 8, , L2-15 To increment index register by k AC (IX) AC (AC) + k IX (AC) new instruction new instruction also the AC must be saved and restored. It may be better to increment IX directly INCi k, IX IX (IX) + k More instructions to manipulate index register STOREi x, IX M[x] (IX) (extended to fit a word)... IX begins to look like an accumulator several index registers several accumulators General Purpose Registers Support for Subroutine Calls February 8, , L2-16 Main Program call F(a1,...) a1 a2 F: Subroutine F call F(b1,...) b1 b2 return A special subroutine jump instruction M: JSR F F M + 1 and jump to F+1 Page 8

21 Indirect Addressing and Subroutine Calls Caller M JSR F arg result M+3 5 Events: Execute M Execute F+1 Execute S1 Execute S2 Execute S3 F F+1 Subroutine S1 LOAD (F) inc F by 1 S2 STORE(F) inc F by 1 Indirect addressing LOAD (x) means AC M[M[x]]... Indirect addressing almost eliminates the need to write self-modifying code (location F still needs to be modified) Problems with recursive procedure calls S3 JUMP (F) February 8, , L2-17 fetch arg store result Recursive Procedure Calls and Reentrant Codes February 8, , L2-18 Indirect Addressing through a register LOAD R 1, (R 2 ) Load register R 1 with the contents of the word whose address is contained in register R 2 registers PC SP memory Pure Code Data Stack Page 9

22 Evolution of Addressing Modes February 8, , L Single accumulator, absolute address LOAD x 2. Single accumulator, index registers LOAD x, IX 3. Indirection LOAD (x) 4. Multiple accumulators, index registers, indirection LOAD R, IX, x or LOAD R, IX, (x) the meaning? R M[M[x] + (IX)] or R M[M[x + (IX)]] 5. Indirect through registers LOAD R I, (R J ) 6. The works LOAD R I, R J, (R K ) R J = index, R K = base address Variety of Instruction Formats February 8, , L2-20 Two address formats: the destination is same as one of the operand sources (Reg x Reg) to Reg R I (R I ) + (R J ) (Reg x Mem) to Reg R I (R I ) + M[x]... x could be specified directly or via a register; effective address calculation for x could include indexing, indirection,... Three operand formats: One destination and up to two operand sources per instruction (Reg x Reg) to Reg R I (R J ) + (R K ) (Reg x Mem) to Reg R I (R J ) + M[x]... many different possible formats! Page 10

23 Data formats: Bytes, Half words, words and double words Some issues Byte addressing Big Endian vs. Little Endian February 8, , L2-21 Data Formats and Memory Addresses Word alignment Suppose the memory is organized in 32-bit words. Can a word address begin only at 0, 4, 8,...? Some Problems February 8, , L2-22 Should all addressing modes be provided for every operand? regular vs. irregular instruction formats Separate instructions to manipulate Accumulators Index registers Base registers A large number of instructions Instructions contained implicit memory references -- several contained more than one very complex control Page 11

24 Compatibility Problem at IBM February 8, , L2-23 By early 60 s, IBM had 4 incompatible lines of computers! Each system had its own Instruction set I/O system and Secondary Storage: magnetic tapes, drums and disks assemblers, compilers, libraries,... market niche business, scientific, real time,... IBM 360 IBM 360 : Design Premises Amdahl, Blaauw and Brooks, 1964 February 8, , L2-24 The design must lend itself to growth and successor machines General method for connecting I/O devices Total performance - answers per month rather than bits per microsecond programming aids Machine must be capable of supervising itself without manual intervention Built-in hardware fault checking and locating aids to reduce down time Simple to assemble systems with redundant I/O devices, memories etc. for fault tolerance Some problems required floating point words larger than 36 bits Page 12

25 February 8, , L2-25 IBM 360: A General-Purpose Register Machine Processor State 16 General-Purpose 32-bit Registers - may be used as index and base registers - Register 0 has some special properties 4 Floating Point 64-bit Registers A Program Status Word (PSW) PC, Condition codes, Control flags A 32-bit machine with 24-bit addresses No instruction contains a 24-bit address! Data Formats 8-bit bytes, 16-bit half-words, 32-bit words, 64-bit doublewords IBM 360: Implementation February 8, , L2-26 Model Model 70 Storage 8K - 64 KB 256K KB Datapath 8-bit 64-bit Circuit Delay 30 nsec/level 5 nsec/level Local Store Main Store Transistor Registers Control Store Read only 1µsec Conventional circuits IBM 360 instruction set architecture completely hid the underlying technological differences between various models. With minor modifications it survives till today Page 13

26 February 10, , L3-- 1 Instruction Set Evolution in the Sixties: GPR, Stack, and Load-Store Architectures Laboratory for Computer Science M.I.T. The Sixties February 10, , L3-- 2 Hardware costs started dropping - memories beyond 32K words seemed likely - separate I/O processors - large register files Systems software development became essential - Operating Systems - I/O facilities Separation of Programming Model from implementation become essential - family of computers Page 1

27 February 10, , L3-- 3 Issues for Architects in the Sixties Stable base for software development Support for operating systems -- processes, multiple users, I/O Implementation of high-level languages -- recursion,... Impact of large memories on instruction size How to organize the processor state from the programming point of view Architectures for which fast implementations could be developed February 10, , L3-- 4 Three Different Directions in the Sixties A family of computers based on a common ISA IBM 360, a General Register Machine A machine with only a high-level language programming interface Burrough s 5000, a stack machine A pipelined machine with a fast clock (Supercomputer) CDC 6600, a Load/Store architecture Page 2

28 February 10, , L3-- 5 IBM 360: A General-Purpose Register Machine Processor State 16 General-Purpose 32-bit Registers - may be used as index and base registers - Register 0 has some special properties 4 Floating Point 64-bit Registers A Program Status Word (PSW) PC, Condition codes, Control flags A 32-bit machine with 24-bit addresses No instruction contains a 24-bit address! Data Formats 8-bit bytes, 16-bit half-words, 32-bit words, 64-bit doublewords February 10, , L3-- 6 IBM 360: Some Addressing Modes RR opcode R1 R2 R1 (R1) op (R2) RX opcode R1 X2 B2 D2 R1 (R1) op M[(X2) + (B2) + D2] a 24-bit address is formed by adding the 12-bit displacement (D) to a base register (B) and an Index register (X), if desired The most common formats for arithmetic & logic instructions, as well as Load and Store instructions Page 3

29 February 10, , L3-- 7 IBM 360: Character String Operations opcode length B1 D1 B2 D2 SS format: store to store instructions M[(B1) + D1] M[(B1) + D1] op M[(B2) + D2] iterate length times most operations on decimal and character strings use this format MVC move characters MP multiply two packed decimal strings CLC compare two character strings... a lot of memory operations per instruction complicates exception & interrupt handling February 10, , L3-- 8 IBM 360: Branches & Condition Codes Arithmetic and logic instructions set condition codes equal to zero greater than zero overflow carry... I/O instructions also set condition codes - channel busy All conditional branch instructions are based on testing these condition code registers (CC s) RX and RR formats BC_ branch conditionally BAL_ branch and link, i.e., R15 (PC)+1 for subroutine calls CC s must be part of the PSW Page 4

30 The Burrough s B5000: An ALGOL Machine, Robert Barton, 1960 February 10, , L3-- 9 Machine implementation can be completely hidden if the programmer is provided only a high-level language interface. Stack machine organization because stacks are convenient for: 1. expression evaluation; 2. subroutine calls, recursion, nested interrupts; 3. accessing variables in block-structured languages. B6700, a later model, had many more innovative features tagged data virtual memory multiple processors and memories Evaluation of Expressions February 10, , L / (a + b * c) / (a + d * c - e) + - a * + e b c a * d c Reverse Polish a b c * + a d c * + e - / Page 5

31 A Stack Machine February 10, , L a push b push c pop c b b a a b a A Stack machine has a stack as a part of the processor state. typical operations: Processor push pop Main stack + Store *... Instructions like + implicitly : specify the top 2 elements of the stack as operands. Hardware organization of the stack February 10, , L Stack is part of the processor state stack must be bounded and small number of Registers and not the size of main memory Conceptually stack is unbounded a part of the stack is included in the processor state; the rest is kept in the main memory Page 6

32 Stack Operations and Implicit Memory References February 10, , L Suppose the top 2 elements of the stack are kept in registers and the rest is kept in the memory. Each push operation 1 memory reference. pop operation 1 memory reference. No Good! Better performance can be gotten by keeping the top N elements in registers and by making memory references only when register stack overflows or underflows. Issue - when to Load/Unload registers? February 10, , L Stack Size and Memory References a b c * + a d c * + e - / program stack memory refs (size = 2) push a R0 a push b R0 R1 b push c R0 R1 R2 c, ss(a) * R0 R1 sf(a) + R0 push a R0 R1 a push d R0 R1 R2 d, ss push c R0 R1 R2 R3 c, ss * R0 R1 R2 sf + R0 R1 sf push e R0 R1 R2 e,ss - R0 R1 sf / R0 4 stores, 4 fetches (implicit) Page 7

33 February 10, , L Stack Size and Expression Evaluation a b c * + a d c * + e - / a and c are loaded twice not the best use of registers! push a R0 push b R0 R1 push c R0 R1 R2 * R0 R1 + R0 push a R0 R1 push d R0 R1 R2 push c R0 R1 R2 R3 * R0 R1 R2 + R0 R1 push e R0 R1 R2 - R0 R1 / R0 February 10, , L Register Usage in a GPR Machine (a + b * c)/(a + (d * c) - e) Load R0 a Load R1 c Load R2 b Mul R2 R1 Add R2 R0 Load R3 d Mul R3 R1 Add R3 R0 Load R0 e Sub R3 R0 Div R2 R3 More control over register usage since registers can be named explicitly Load Ri m Load Ri (Rj) Load Ri (Rj) (Rk) - eliminates unnecessary Loads and Stores - fewer Registers but instructions may be longer! Page 8

34 Procedure Calls Storage for procedure calls also follows a stack discipline However, there is a need to access variables beyond the current stack frame - lexical addressing < ll, d > - display registers to speed up accesses to stack frames R February 10, , L Proc P Proc Q Proc R Q R Q automatic loading of display registers? 3 2 ll = 1 Q R Q P display stack static dynamic registers links link February 10, , L Stack Machines -- Essential features In addition to push, pop, + etc., the instruction set must provide the capability to refer to any element in the data area jump to any instruction in the code area move any element in the stack frame to the top machinery to carry out +, -, etc. SP DP a PC b c.. push a push b push c * + push e / stack data code Page 9

35 February 10, , L Stack versus GPR Organization Amdahl, Blaauw and Brooks, The performance advantage of push down stack organization is derived from the presence of fast registers and not the way they are used. 2. Surfacing of data in stack which are profitable is approximately 50% because of constants and common subexpressions. 3. Advantage of instruction density because of implicit addresses is equaled if short addresses to specify registers are allowed. 4. Management of finite depth stack causes complexity. 5. Recursive subroutine advantage can be realized only with the help of an independent stack for addressing. 6. Fitting variable length fields into fixed width word is awkward. Stack Machines Died by 1980 February 10, , L Stack programs are not smaller if short (Register) addresses are permitted. 2. Modern compilers can manage fast register space better than the stack discipline. 3. Lexical addressing is a useful abstract model for compilers but hardware support for it (i.e. display) is not necessary. GPR s and caches are better than stack and displays Early language-directed architectures often did not take into account the role of compilers! B5000, B6700, HP 3000, ICL 2900, Symbolics 3600 Page 10

36 CDC 6600 Seymour Cray, 1964 A fast pipelined machine with 60-bit words February 10, , L Ten functional units Floating Point adder, multiplier, divider Integer adder, multiplier... Hardwired control (no microcoding) Dynamic scheduling of instructions using a scoreboard Ten Peripheral Processors for Input/Output - a fast time-shared 12-bit integer ALU Very fast clock Novel freon-based technology for cooling CDC 6600: Datapath February 10, , L Operand Regs 8 x 60-bit Central Memory Address Regs Index Regs 8 x 18-bit 8 x 18-bit oprnd addr result addr operand result 10 Functional Units IR Inst. Stack 8 x 60-bit Page 11

37 CDC 6600: A Load/Store Architecture February 10, , L Separate instructions to manipulate three types of reg bit data registers (X) 8 18-bit address registers (A) 8 18-bit index registers (B) All arithmetic and logic instructions are reg-to-reg opcode i j k Ri (Rj) op (Rk) Only Load and Store instructions refer to memory! opcode i j disp Ri M[(Rj) + disp] Touching address registers 1 to 5 initiates a load 6 to 7 initiates a store - very useful for vector operations CDC6600: Vector Addition February 10, , L B0 - n loop: JZE B0, exit A0 B0 + a0 A1 B0 + b0 X6 X0 + X1 A6 B0 + c0 B0 B0 + 1 jump loop load X0 load X1 store X6 Page 12

38 Krste 6.823, L4--1 Seventies, Eighties, Nineties: Convergence from Mainframes & Supercomputers to Microprocessors Krste Asanovic Laboratory for Computer Science M.I.T. The Seventies Supercomputers (synonymous with Vector Machines) dominated the high-end scientific computing market Cray-1 CDC, Fujitsu, NEC, Hitachi Krste 6.823, L4--2 Mainframes were thriving in enterprise computing IBM 370 and its clones, Burroughs, UNIVAC, DEC,... Minicomputers (cheaper versions of mainframes) created a large new market: departmental computing DEC PDP-11 & VAX Wang, Data General, Prime,... Microprocessors appeared, and first personal computers In 1971: Intel 4004 (4-bit, 750kHz) By 1979: Motorola (32-bit, 8MHz) Page 1

39 Seventies Technology Krste 6.823, L4--3 Supercomputers and mainframes used mostly ECL - expensive - hot liquid cooling (plumbing!) - low density (SSI & MSI) chips - MTBF in days Minicomputers used mostly TTL technology - cheaper - air cooled - medium density (MSI & LSI) chips - very reliable, i.e., MTBF in weeks All machines except supercomputers used MOSFETs for memory chips Software in the Seventies Krste 6.823, L4--4 Most programming was done in high-level languages Fortran, COBOL, Basic, Lisp, Pascal, Simula, C,... Time-sharing and interactive computing came into widespread use (screens versus punched cards) Most companies used proprietary Operating Systems IBM OS370, MVS,... DEC VMS,... Unix, a portable OS, was beginning to be used on minicomputers in universities Internet ( , FTP, TCP/IP,...) came into existence Page 2

40 Seventies General-Purpose Architectures Krste 6.823, L4--5 (minicomputers and mainframes for business processing) Characteristics: Complex Instruction Sets: Microcoded Control Very Little Instruction Pipelining Caches Virtual Memory (IBM 360->370, DEC PDP-11->VAX) Sources of Complexity in ISAs Addressing modes Variable-length fields Macro-instructions - loop control - function call Regularity - most addressing mode for each operand - most operators for each data type Krste 6.823, L4--6 Microprogramming made it possible to implement large and complex instruction sets at a reasonable cost Page 3

41 Krste 6.823, L4--7 VAX: A Complex Instruction Set Addressing Mode Syntax Length in bytes Literal #value 1 (6-bit signed value) Immediate #value 1 + immediate Register Rn 1 Register deferred (Rn) 1 Byte/word/long disp(rn) 1 + displacement displacement 1 + displacement displacement deferred Scaled (Indexed) base mode (Rx) 1 + base addressing mode Autoincrement (Rn)+ 1 Autodecrement -(Rn) 1 1 deferred ADDL3 R1, 737 (R2), #456 R1 <-- M[(R2)+737] ( ) + (1+ 4) = 10 bytes! Supercomputers Krste 6.823, L4--8 Applications: Military research (nuclear weapons, cryptography) Scientific research Weather forecasting Oil exploration Industrial design (car crash simulation) 70s-80s, Supercomputer == Vector Machine Page 4

42 Vector Supercomputers Krste 6.823, L4--9 (Epitomized by Cray-1, 1976) Scalar Unit + Vector Extensions Load/Store Architecture Vector Registers Vector Instructions Hardwired Control Highly Pipelined Functional Units Interleaved Memory System No Data Caches No Virtual Memory Vector Programming Model Krste 6.823, L4--10 Page 5

43 Vector Code Example Krste 6.823, L4--11 # C code for (i=0; i<64; i++) C[i] = A[i] + B[i]; # Scalar Code li r4, #64 loop: ld f1, 0(r1) ld f2, 0(r2) fadd f3, f1, f2 st f3, 0(r3) add r1, r1, #1 add r2, r2, #1 add r3, r3, #1 sub r4, #1 bnez r4, loop # Vector Code li vlr, #64 lv v1, r1, #1 lv v2, r2, #1 faddv v3, v1, v2 sv v3, r3, #1 Vector Arithmetic Execution V3 <- V1 * V2 Krste 6.823, L4--12 V1 V2 V3 -> Pipelined Execution -> Page 6

44 Krste 6.823, L4--13 Vector Memory Execution Chaining Krste 6.823, L4--14 Chaining Path Page 7

45 Cray-1 (1976) Krste 6.823, L4--15 Single Port Memory 16 banks of 64-bit words + 8-bit SECDED 80MW/sec data load/store 320MW/sec instruction buffer refill (A 0 ) (A 0 ) ( (A h ) + j k m ) 64 T Regs ( (A h ) + j k m ) 64 T Regs 64-bitx16 4 Instruction Buffers memory bank cycle 50 ns 64 Element Vector Registers S i T jk A i B jk V0 V1 V2 V3 V4 V5 V6 V7 S0 S1 S2 S3 S4 S5 S6 S7 A0 A1 A2 A3 A4 A5 A6 A7 NIP LIP V i V j V k S j S k S i A j A k A i CIP V. Mask V. Length FP Add FP Mul FP Recip Int Add Int Logic Int Shift Pop Cnt Addr Add Addr Mul processor cycle 12.5 ns (80MHz) Krste 6.823, L4--16 Microprocessors in the Seventies Initial target was embedded control First micro, 4-bit 4004 from Intel, designed for a desktop printing calculator Constrained by what could fit on single chip Single accumulator architectures 8-bit micros used in hobbyist personal computers Micral, Altair, TRS-80, Apple-II Little impact on conventional computer market until VISICALC spreadsheet for Apple-II (6502, 1MHz) First killer business application for personal computers Page 8

46 Intel 4004, 1971 Krste 6.823, L bit accumulator architecture 8µm pmos 2,300 transistors 3 x 4 mm 2 750kHz clock 8-16 cycles/inst. Krste 6.823, L4--18 DRAM in the Seventies Dramatic progress in MOSFET memory technology 1970, Intel introduces first DRAM (1Kbit 1103) 1979, Fujitsu introduces 64Kbit DRAM => By mid-seventies, obvious that PCs would soon have > 64KBytes physical memory Page 9

47 Microprocessor Evolution Krste 6.823, L4--19 Rapid progress in size and speed through 70s Fueled by advances in MOSFET technology and expanding markets Intel i432 Most ambitious seventies micro; started in released bit capability-based object-oriented architecture Instructions variable number of bits long Severe performance, complexity, and usability problems Intel 8086 (1978, 8MHz, 29,000 transistors) Stopgap 16-bit processor, architected in 10 weeks Extended accumulator architecture, assembly-compatible with bit addressing through segmented addressing scheme Motorola (1979, 8MHz, 68,000 transistors) First production microprocessor with microcode 32-bit general purpose register architecture (24 address pins) 8 address registers, 8 data registers Intel 8086 Krste 6.823, L4--20 Class Register Purpose Data: AX,BX general purpose CX string and loop ops only DX mult/div and I/O only Address: SP stack pointer BP base pointer (can also use BX) SI,DI index registers Segment: CS code segment SS stack segment DS data segment ES extra segment Control: IP instruction pointer (lower 16 bit of PC) FLAGS C, Z, N, B, P, V and 3 control bits Typical format R (R) op M[X], many addressing modes Not a GPR organization! Page 10

48 The Eighties: Microprocessor Revolution Personal Computer revolution Huge business and consumer market for spreadsheets, word processing and games Based on inexpensive 8-bit and 16-bit micros: Zilog Z80, Mostek 6502, Intel 8088/86, Krste 6.823, L4--21 Minicomputers replaced by workstations Distributed network computing and high-performance graphics for scientific and engineering applications (Sun, Apollo, HP, ) Based on powerful 32-bit microprocessors with virtual memory, caches, pipelined execution, hardware floating-point Massively Parallel Processors (MPPs) appear Use many cheap micros to approach supercomputer performance (Sequent, Intel, Parsytec) IBM PC, 1981 Hardware Team from IBM building PC prototypes in 1979 Motorola chosen initially, but was late IBM builds stopgap prototypes using 8088 boards from Display Writer word processor 8088 is 8-bit bus version of 8086 Estimated sales of 25,000 (>200,000,000 sold) Software Microsoft negotiates to provide OS for IBM. Later buys and modifies QDOS from Seattle Computer Products. Open System Standard processor, Intel 8088 Standard interfaces Standard OS, MS-DOS IBM permits cloning and third-party software Krste 6.823, L4--22 Page 11

49 Krste 6.823, L4--23 Writable Control Store (WCS) Implement control store with RAM not ROM MOS memories now almost as fast as control store (core memories were 10x slower) Bug-free microprograms difficult to write WCS provided as option on several minicomputers Allowed users to change microcode for each process WCS failed Little or no programming tools support Hard to fit software into small space Microcode control tailored to original ISA, less useful for others Large WCS part of processor state - expensive context switches Protection difficult if user can change microcode Virtual memory required restartable microcode Krste 6.823, L4--24 Reduced Instruction Set Computers (Cocke, IBM; Patterson, UC Berkeley; Hennessy, Stanford) Compilers have difficulty using complex instructions VAX: 60%of microcode for 20% of instructions, only responsible for 0.2% execution time IBM retargets 370 compiler to use ISA subset - generated code faster! Simple instruction sets don t need microcode Use fast memory near processor as cache, not microcode storage Design ISA for simple pipelined implementation Fixed length, fixed format instructions Load/store architecture with up to one memory access/instruction Few addressing modes, synthesize others with code sequence Register-register ALU operations Delayed branch Page 12

50 MIPS R2000 (One of first commercial RISCs, 1986) Krste 6.823, L4--25 Load/Store architecture 32x32-bit GPR (R0 is wired), HI & LO SPR (for multiply/divide) 74 instructions Fixed instruction size (32 bits), only 3 formats PC-relative branches, register indirect jumps Only base+displacement addressing mode No condition bits, compares write GPRs, branches test GPRs Delayed loads and branches Five-stage instruction pipeline Fetch, Decode, Execute, Memory, Write Back CPI of 1 for register-to-register ALU instructions 8 MHz clock Tightly-coupled off-chip FP accelerator (R2010) RISC/CISC Comparisons Krste 6.823, L4--26 Time = Instructions * Cycles * Time Program Program Instruction Cycle R2000 vs VAX 8700 [Bhandarkar and Clark, 91] R2000 has ~2.7x advantage with equivalent technology Intel vs Intel i860 (both 1989) Same company, same CAD tools, same process i x faster - even more on some floating-point tasks DEC nvax vs Alpha (both 1992) Same company, same CAD tools, same process Alpha 2-4x faster Page 13

51 VLIW (Very Long Instruction Word) Krste 6.823, L4--27 Multiple parallel operations packed into single long instruction add r1, r2, r3 sub r5, r1, r3 ld r4, (r3) jmp #1499 FPS AP-120B, first commercial VLIW Scientific libraries coded by hand Fisher & Ellis, Yale, early 80s Proposed wide machines with simple control logic Develop compiler techniques to schedule parallel code Yale ideas commercialized by Multiflow Trace-28 executed 28 operations per cycle Trace-28 had 1024-bit instructions Intel i860 (1989) First dual issue microprocessor using 64-bit LIW The Nineties Krste 6.823, L4--28 Big companies regain control, alliances common Microprocessor design requires huge investment Distinction between workstation and PC disappears Parallel microprocessor-based SMPs take over lowend server and supercomputer market MPPs have limited success in supercomputing market High-end mainframes and vector supercomputers survive killer micro onslaught 64-bit addressing becomes essential at high-end In 1999, 4GB DRAM costs <$5,000 Page 14

52 ISA De-Emphasized Krste 6.823, L4--29 Few major companies in general-purpose market Intel x86 Sun SPARC, SGI MIPS, HP PA-RISC (all RISCs) IBM/Apple/Motorola introduce PowerPC (another RISC) Digital introduces Alpha (another RISC) Software compatibility makes ISA change expensive 64-bit addressing added to RISC instruction sets Short vector multimedia extensions added to all ISAs, but without compiler support Focus on microarchitecture (superscalar, out-of-order) CISC (x86) thriving RISC advantage shrinks with superscalar and out-of-order execution Krste 6.823, L4--30 Pentium Pro vs MIPS R10000 External Bus Interface Execution Units D-cache I-cache Page 15

53 Krste 6.823, L4--31 Looking Forward New technologies 1-10 billion transistor chips technically feasible Merged logic/dram process - system on a chip Wireless networks Cheap sensors New platforms Hand-held/wearable computers Ubiquitous embedded computers Huge servers New applications? Page 16