We briefly explain an instruction cycle now, before proceeding with the details of addressing modes.

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1 Addressing Modes This is an important feature of computers. We start with the known fact that many instructions have to include addresses; the instructions should be short, but addresses tend to be long. Addressing modes are a solution to this problem. Using addressing modes, a short instruction may specify a long address. The idea is that the instruction no longer includes the full address (also called the effective address, or EA), but instead contains a number, normally called a displacement, that s closely related to the address. Another field, an addressing mode, is also added to the instruction. The addressing mode is a code that tells the control unit how to obtain the effective address from the displacement. It is more accurate to say that the addressing mode is a rule of calculation, or a function, that uses the displacement as its main argument, and other hardware components such as the PC, the registers, and memory locations as secondary arguments,and produces the EA as a result. The notation EA = f M (Disp,PC, Regs, Mem), where the subscript M indicates the mode. The various addressing modes are specified in figure 2.7a and 2.7b. For different modes there are different functions, but the idea is the same. Before any individual modes are discussed, it may be useful to look at some of the facts. Up until the mid 1970s, memories were expensive, and computers supported small memories. A typical memory size in a second generation computer was 16K 32K words (24 48 bits/word), and in an early third generation computer, 32K 64K words (48 60 bits/word). Today, with much lower hardware prices, modern computers can access much larger memories. Most of the early microprocessors could address 64K bytes, and most of today s microprocessors can address between 32M words and a few tera words (usually 8 bit words, bytes). As a result, those computers must handle long addresses. Since 1M (1 mega) is defined as 1024K = = 220, an address in a 1M memory is 20 bits long. In a 32M memory, an address is 25 bits long. The Motorola microprocessor and the Intel generate 32 bit addresses, and can thus physically address 4G (giga) bytes. (their virtual address space, though, is 64 tera bytes, = 246.) We briefly explain an instruction cycle now, before proceeding with the details of addressing modes. Review of Instruction Cycle To understand the details of the various addressing modes presented in this section, it is imperative that we understand the basic operation cycle of the computer. The control unit of a computer is designed to go through an instruction cycle that is divided into following major phases: 1. Fetch an instruction from memory. 2. Decode the instruction. 3. Read the EA from memory if the instruction has an indirect address. 4. Execute the instruction. There is one register in the computer called the program counter or PC that keeps track of the instructions in the program stored in memory. PC holds the address of the instruction to be executed next and is incremented each time an instruction is fetched from memory. Value addition: A Quick View Various Addressing Modes with Examples The most common names for addressing modes (names may differ among architectures) Addressing modes Example Instruction Meaning When used Register Add R4,R3 R4 < R4 + R3 When a value is in a register Immediate Add R4, #3 R4 < R4 + 3 For constants Add R4, R4 < R4 +

2 Add R4, Displacement 100(R1) Register deffered Indexed Direct Memory deferred Autoincrement Autodecrement Scaled R4 < R4 + Mem[100+R1] Add R4,(R1) R4 < R4 + M[R1] Add R3, (R1 + R2) Add R1, (1001) Add Add R1, (R2)+ Add R1, (R2) R3 < R3 + Mem[R1+R2] R1 < R1 + Mem[1001] R1 < R1 + Mem[Mem[R3]] R1 < R1 +Mem[R2] R2 < R2 + d R2 < R2 d R1 < R1 + Mem[R2] Accessing local variables Accessing using a pointer or a computed address Useful in array addressing: R1 base of array R2 index amount Useful in accessing static data If R3 is the address of a pointer p, then mode yields *p Useful for stepping through arrays in a loop. R2 start of array d size of an element Same as autoincrement. Both can also be used to implement a stack as push and pop Used to index arrays. May be Add R1, R1<applied to any base addressing 100(R2)[R3] R1+Mem[100+R2+R3*d] mode in some machines. Notation: < assignment Mem the name for memory: Mem[R1] refers to contents of memory location whose address is given by the contents of R1 Source: Self Implied Mode In this mode the operands are specified implicitly in the definition of the instruction. Like, the instruction complement accumulator is an implied mode instruction because the operand in the accumulator register is implied in the definition of the instruction. In fact, all register reference instructions that use an accumulator are implied mode instructions. Zero address instructions in a stack organized computer are implied mode instructions since the operands are implied to be on top of the stack. Instructions such as HLT or EI (enable all interrupts) are good examples. Those instructions do not use any modes, but the manufacturer s literature refers to them often as using the implicit or implied mode.

3 Figure 2.7a: Various Addressing Modes Figure 2.7b: Various Addressing Modes Reference: s07/lectures_07/lecture_1.ppt Immediate Mode

4 In this mode the operand value is part of instruction and does not need a memory reference. Operand value is stored in the address field. For e.g. consider the instruction: ADD 5 means the following: Add 5 to contents of accumulator 5 is operand No memory reference is required to fetch data. This results in a faster instruction. Figure 2.8: Immediate Mode This mode (refer figure 2.8) is used when the instruction requires the value of a constant, not the contents of a memory location. An ADD instruction, for example, is often written ADD R3, XY and it adds the contents of location XY to register 3. If, however, the programmer wants to add the number 67 to register 3, the same instruction can be used in the immediate mode, where it is typically written ADD R3, # 67. The number sign (or hash sign) # is usually used to indicate the immediate mode. Assuming that the code of this mode is 2, the instruction above will be assembled into [opcode, 3, 2, 67], where 3 is the register number, 2 is the mode, and 67 is the immediate operand. The immediate quantity (the number to be used by the instruction) should be small enough to fit in the displacement field. This mode always generates an absolute instruction and it is different from all the other modes because it does not involve any effective address (EA). We say that in this mode, the operand is located in the instruction, not in memory Register Mode Operand (effective address EA) is held in register (R) named in address field (refer figure 2.9), that is EA = R. It uses only limited number of registers Very small address field is needed, therefore this results in: A shorter instruction length and Instruction fetch is faster and takes lesser time This does not requires any memory access Instruction execution is very fast It is faster to acquire an operand than the memory addressing Very limited address space is required as this mode saves address field in the instruction Multiple registers helps in improving the performance of the mode This mode can be utilized efficiently by good assembly programming or compiler writing.

5 Figure 2.9: Register Mode In this mode (refer figure 2.9) the operands are in registers that reside within the CPU. The particular register is selected from a register field in the instruction. A k bit field can specify any one of 2 k registers Register Indirect Mode It is indirect addressing because instruction specifies a register which contains the memory address of the operand Operand is in memory cell pointed to by contents of register R. It saves instruction bits since register address is shorter than the memory address It requires one fewer memory access than the indirect addressing This mode is slower in acquiring an operand as compared to both the register addressing and memory addressing modes. Figure 2.10: Register Indirect Mode In this mode (refer figure 2.10), the register contains the effective address and it points to the operand in memory. The advantage of such instruction is that the address field of the instruction uses fewer bits to select a register than would have been required to specify a memory address directly. Value addition: Interesting Fact Nova Minicomputer

6 Nova Minicomputer In the Nova minicomputer, memory locations are special. Locations are auto increment and locations are auto decrement. When any of those locations is accessed by an indirect instruction, the computer first either increments or decrements that location (depending on the operation to be executed), then uses it to calculate the effective address. Source: Direct Address Mode Address field in this addressing mode contains address of the operand Effective address (EA) = address field (A) For e.g. consider: ADD A is executed as follows: _ Add contents of cell A to accumulator _ Looks in memory at address A for operand Single memory reference is required to access data No additional calculations are required to work out effective address This addressing mode requires a limited address space only. Figure 2.11a: Direct Addressing Mode This is the case (refer figure 2.11a) where the displacement field is large enough to contain the effective address. There is no need for any calculations, and the effective address is simply the displacement. The definition of this simple mode is EA Displacement, but this is not a very useful mode because it does not result in a short instruction (it is like not having an addressing mode at all). Nevertheless, if the assembler cannot assemble an instruction using any other mode, it has to use the direct mode. The advantage offered by this mode is that there is no need to calculate the address, as it is there in the instruction itself. Value addition: Interesting Facts Obsolete addressing modes The addressing modes listed here were used in the time frame, but are no

7 The addressing modes listed here were used in the time frame, but are no longer available on most current computers. This list is by no means complete; there have been many other interesting and peculiar addressing modes used from time to time, e.g. absolute plus logical OR of two or three index registers. Multi level memory indirect The IBM 1620, the Data General Nova, and the NAR 2 each have such a multi level memory indirect, and could enter such a infinite address calculation loop. The memory indirect addressing mode on the Nova influenced the invention of indirect threaded code. The DEC PDP 10 computer with 18 bit addresses and 36 bit words allowed multi level indirect addressing with the possibility of using an index register at each stage as well. Memory mapped registers On some computers, the registers were regarded as occupying the first 8 or 16 words of memory (e.g. ICL 1900, DEC PDP 10). This meant that there was no need for a separate "Add register to register" instruction you could just use the "add memory to register" instruction. Memory indirect, autoincrement On some early minicomputers (e.g. DEC PDP 8, Data General Nova), there were typically 16 special memory locations. When accessed via memory indirect addressing, 8 would automatically increment after use and 8 would automatically decrement after use. This made it very easy to step through memory in loops without using any registers. Zero page The Motorola 6800 family and MOS Technology 6502 family of processors were series of CISC microprocessors with very few internal registers. Arithmetic and logical instructions were mostly performed against values in memory as opposed to internal registers. As a result, many instructions required a two byte (16 bit) location to memory. Given that opcodes on these processors were only one byte (8 bit) in length, memory addresses could make up a significant part of code size. Direct page The zero page address mode was enhanced in several descendants of the MOS Technology 6502, including the WDC 65816, the MOS Technology 65CE02, and the Motorola The new mode, known as "direct page" addressing, added the ability to move the 256 byte zero page memory window from the start of memory (offset address $0000) to a new location within the first 64KB of memory. The MOS 65CE02 allowed the direct page to be moved to any 256 byte boundary within the first 64KB of memory by storing an 8 bit offset value in the new B (block) register, equivalent to the 8 bit 6809 DP (direct page) register. Source:

8 Figure 2.11b: Comparing Direct and Indirect Addressing Mode Indirect Address Mode The address field of an instruction specifies the address of a memory location say A, that contains the address of the operand. That is look in A, find address of A and look there for operand For e.g. consider: ADD (A) is executed as follows: It add contents of cell pointed to by contents of A to accumulator Large address space: When the abbreviated address is used large physical memory can be addressed with a relatively small number of bits. It is slow to acquire an operand in this mode because of an additional memory access. The instruction in this may be nested, multilevel, cascaded e.g. EA = (((A))), that is it gives an address at a given address and so on Therefore, it may require multiple memory accesses to find an operand Hence it may become slower as compared to others due to multiple level of indirection.

9 Figure 2.12a: Indirect Addressing Mode This is a more complex mode (refer figure 2.11b and 2.12a), requiring the control unit to work harder in order to calculate the effective address (EA). The rule of calculation is EA=Mem[disp] meaning, the control unit should fetch the content of the memory location whose address is disp., and that content is the effective address (EA). Obviously, this mode is slower than the ones discussed so far, since it involves a memory read. The effective address (EA) has to be read from memory (in Step 4 of the fetch execute cycle) before execution of the instruction can start. A simple example is LC Obj. Code. Opc m disp 24 xxx TO DC The at instructs the assembler to use the indirect mode (other symbols, such as a dollar sign, may be used by different assemblers). The value of TO (address 124) is the indirect address and, in the simplest version of the indirect mode, it has to be small enough to fit in the displacement field. This is one reason why several versions of this mode exist (see below). The effective address (EA) in our example is 11387, the content of memory location 124. What s the use of this mode? As this is a discussion of computer organization, and not of assembly language programming, a complete answer cannot be provided here. However, we can mention a common case where this mode is used, namely a return from a procedure. When a procedure is called, the return address has to be saved. Most computers save the return address in the stack, but some old computers save it in the first word of the procedure (in which case the first executable instruction of the procedure should be stored in the second word). If the latter method is used, a return from the procedure is done by a jump to the memory location whose address is contained in the first word of the procedure. This is therefore a classical, simple application of the indirect mode. If the procedure name is P, then an instruction such as specifies the indirect mode) can easily

10 accomplish the job. Incidentally, if the return address is saved in the stack, a special instruction, such as RET, is necessary to return from the procedure. Such an instruction should jump to the memory location whose address is contained at the top of the stack, and also remove that address from the stack. Thus, a RET instruction uses a combination of the indirect and stack modes. Common extensions of the indirect mode combine it with either the relative or the index modes. The JMP instruction above could be assembled into xxx 3 99, since the value of TO relative to the JMP instruction is = 99. We assume that the size of the JMP instruction is one word and that mode 3 is the combination indirect relative. A combination indirect index can also be used and, in fact, the (now obsolete) 6502 microprocessor used two such combinations, a preindexed indirect (that can only be used with index register X), and a post indexed one (that can only be used with index register Y). Their definitions are (refer figure 2.12b): Pre indexed indirect: Effective Address = Mem[disp + X], Post indexed indirect: Effective Address = Mem[disp] + Y. Figure 2.12b: Indirect Addressing Mode (Pre Indexed and Post Indexed) Source: In the former version, the indexing (disp + X) is done first, followed by the indirect operation (the memory read). In the latter version, the indirect is done first and the indexing (... + Y) follows. The two instructions LDA ($80,X) and LDA ($80),Y are typical examples. The dollar sign $ stands for hexadecimal and the parentheses imply the indirect mode. It is interesting to note that in order to keep the instructions short, there is no mode field in the 6502 instructions, and the mode is implied in the opcode. Thus, an instruction may have several opcodes, one for each valid mode. The two instructions above have opcodes of A1 and B1 (hexadecimal), respectively Relative Address Mode Relative addressing mode is a version of displacement addressing Here the register R in use is the program counter (PC) register Therefore, the effective address (EA) = operand address (A) + (PC) In this mode, the displacement field is set by the assembler to the distance between the instruction and its operand. This is a useful mode that is often selected by the assembler as a first choice when the user does not explicitly specify any other mode. It also results in an instruction that does not require relocation by the loader. Using the concept of a function mentioned earlier, the definition of this mode is Effective address (EA) = Disp + PC. This means that, at run time, before the instruction can be executed, the control unit has to add the displacement and the PC to obtain the EA. The control unit can easily do that, and the only problem is to figure out the displacement in the first place. This is done by the compiler (or assembler) in a simple way. The compiler maintains a variable called the location counter (LC) that points to the instruction currently being compiled. Also, at run time, the PC always contains

11 the address of the next instruction. Therefore the expression above can be written as Disp = EA PC, which implies Disp = EA (LC + size of current instruction) = EA LC size of current instruction Example: The simple JUMP instruction JMP B. We assume that the JMP instruction is assembled and loaded into memory location 57, and that the value of symbol B is address 19. The expression above implies the displacement should be: Disp = = 39. Notice that the displacement is negative. A little thinking shows that the displacement is negative whenever the operand precedes the instruction. Thus, in this mode, the displacement should be a signed number. Since the sign uses one of the displacement bits, the maximum value of a signed displacement is only half that of an unsigned one. An 8 bit displacement, for instance, is in the range [0, 255] if it is unsigned, but in the shifted interval [ 128, +127] if it is signed. The ranges have the same size, but the maximum values are different. This example also illustrates the absolute nature of this mode. The displacement is essentially the distance between the instruction and its operand, and this distance does not depend on the start address of the program. We say that this mode generates position independent code and an instruction using it does not have to be relocated Indexed Addressing Mode A represents the address part R represents the index part Therefore, we calculate the effective address (EA) = A + R This addressing mode is good for accessing arrays as the effective address is calculated as stated above. Therefore, it becomes easier to access an array (after we know the address of first array index) by the increment operation on the value of R i.e. R++ This mode is especially useful in loops, when the same operation is performed on the elements of an array. It uses an index register, which can normally be any general purpose register (although on some computers only certain registers can be used as index registers). The effective address function in this mode is Effective Address = Address part + Index. This mode should be explicitly specified by the instruction as it is not automatically selected by the assembler. For example: LOD R1,0(R5). The displacement is 0, and the index register is R5. Before the loop starts, R5 should be set to some value, most likely the beginning address of the array. R5 should be incremented in each iteration, so that it points to the next array element. The loop becomes: LOD R5, M Load the start address of the array LUP LOD R1,0(R5) Load the next array element into R1.. INC R5 Update the index register CMP R5,#LEN Compare it with the length of the array. BLT LUP Branch on Less Than.

12 . LEN EQU 25 LEN is the array size ARY RES LEN ARY is the array itself M DAT ARY Location M contains the value of symbol ARY Exercise 2.3: What instruction can be used instead of LOD R5, M above, to load the value of ARY? The index mode can also be used in a different way, as in LOD R1, ARY(R5) where ARY is the start address of the array and R5 is initialized to 0. In this case, the index register really contains the index of the current array element used. This form can be used if the start address of array ARY fits in the displacement field Autoincrement or Autodecrement Mode This is a powerful version of the index mode. The control unit uses the index register to calculate the effective address, then increments or decrements the register. This is an example of a powerful addressing mode, because an instruction using this mode can do the work of two instructions. The PDP 11 instruction CLR (R5)+ is executed by (1) using R5 as an index (it contains the effective address, so it points to the operand in memory), (2) executing the instruction (clear the operand, a memory word), and (3) finally, increment the index register so that it points to the next word in memory. Without this mode (autoincrement and autodecrement), another instruction would be needed, to increment the register. Similarly, the instruction INC (R5) starts by decrementing the index register, then using it as an index, pointing to the memory word that is to be incremented. In the DEC PDP 11, memory is physically divided into bytes, and a word consists of two consecutive bytes. The instructions above operate on a word and, therefore, the index is updated by 2, not by 1, so it points to the next/previous word. In an instruction such as CLRB (clear a byte), the register is updated by Base Register Addressing Mode The formula for calculating the function Effective Address (EA) = Base Register + Address Part In this mode, content of base register is added to the address part of the instruction to obtain the effective address. It is quiet similar to the indexed addressing mode with a difference that here contents of base register is used instead of the index register. Displacement Addressing is a very powerful mode of addressing that combines the capabilities of direct addressing and register indirect addressing, which is broadly categorized as displacement addressing: EA = A + (R) Displacement addressing (see figure 2.13) requires that the instruction have two address fields, at least one of which is explicit. The value contained in one address field (value = A) is used

13 directly. The other address field, or an implicit reference based on opcode, refers to a register whose contents are added to A to produce the effective address. Figure 2.13: Displacement Addressing Diagram Three of the most common use of displacement addressing as discussed above are: Relative addressing Base register addressing Indexing A Numerical Example For each possible mode, calculate the effective address and the operand that must be loaded into AC. Use the instruction defined in Figure Table 8.1 shows the tabular list of the numerical example. Address MEMORY 300Load to AC Mode 301 Address = Next instruction PC = 300 R1 = 500 XR = 100 AC Figure 2.14: Numerical example for addressing modes

14 Source: Self Table 2.1: Tabular List of Numerical example Tabular list of numerical example Addressing mode Effective address Content of AC Direct address Immediate operand Indirect address Relative address Indexed address Register 500 Register indirect Autoincrement * Autodecrement * Autodecrement decrements R1 prior the execution Value addition: Did You Know Various Pentium Addressing Modes 1. Virtual or effective address is offset into segment Starting address + offset = linear address This goes through page translation if paging is enabled 2. 9 addressing modes are available in Pentium Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative Source: Self Value addition: Image Pentium Addressing Mode Calculation

15 Source: William Stallings, Computer Organization and Architecture, MacMillan Publishing Company, 1993 Value addition: Did You Know PowerPC Addressing Modes v Load / store architecture Indirect 1. Instruction includes 16 bit displacement to be added to base register (may be general purpose register) 2. Can replace base register content with new address Indirect indexed 1. Instruction references base register and indexed register(both may be general purpose register) 2. Effective Address is a sum of contents v Branch address Absolute Relative Indirect v Arithmetic Operands in registers or part of instruction Floating point is register only Source: Self Value addition: Image PowerPC Addressing Modes with Diagram

16 Source: William Stallings, Computer Organization and Architecture, MacMillan Publishing Company, 1993 Value addition: Image for Instruction Formats and Addressing Modes for Source: Self