Memory Basics. Course Outline. Introduction to Digital Logic. Copyright 2000 N. AYDIN. All rights reserved. 1. Introduction to Digital Logic.

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1 Introduction to Digital Logic Prof. Nizamettin AYDIN ourse Outline. Digital omputers, Number Systems, Arithmetic Operations, Decimal, Alphanumeric, and Gray odes. inary Logic, Gates, oolean Algebra, Standard Forms. ircuit Optimization, Two-Level Optimization, Map Manipulation, Multi-Level ircuit Optimization 4. Additional Gates and ircuits, Other Gate Types, Exclusive-OR Operator and Gates, High-Impedance Outputs 5. Implementation Technology and Logic Design, Design oncepts and Automation, The Design Space, Design Procedure, The major design steps 6. Programmable Implementation Technologies: Read-Only Memories, Programmable Logic Arrays, Programmable Array Logic,Technology mapping to programmable devices 7. ombinational Functions and ircuits 8. Arithmetic Functions and ircuits 9. Sequential ircuits Storage Elements and Sequential ircuit Analysis. Sequential ircuits, Sequential ircuit Design State Diagrams, State Tables. ounters, register cells, buses, & serial operations. Sequencing and ontrol, path and ontrol, Algorithmic State Machines (ASM). asics Introduction to Digital Logic Overview Lecture asics definitions Random Access (RAM) Static RAM (SRAM) integrated circuits ells and slices ell arrays and coincident ion Arrays of SRAM integrated circuits Dynamic RAM (DRAM) integrated circuits DRAM Types Synchronous (SDRAM) Double- Rate (DDR SRAM) RAMUS DRAM (RDRAM) Arrays of DRAM integrated circuits 4 Definitions Definitions (ontinued) A collection of storage cells together with the necessary circuits to transfer information to and from them. Organization the basic architectural structure of a memory in terms of how data is accessed. Random Access (RAM) a memory organized such that data can be transferred to or from any cell (or collection of cells) in a time that is not dependent upon the particular cell ed. A vector of bits that identifies a particular memory element (or collection of elements). 5 Typical data elements are: bit a single binary digit byte a collection of eight bits accessed together word a collection of binary bits whose size is a typical unit of access for the memory. It is typically a power of two multiple of bytes (e.g., byte, bytes, 4 bytes, 8 bytes, etc.) a bit or a collection of bits to be stored into or accessed from memory cells. Operations operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc.). 6 opyright N. AYDIN. All rights reserved.

2 Organization Organized as an indexed array of words. Value of the index for each word is the memory address. Often organized to fit the needs of a particular computer architecture. Some historically significant computer architectures and their associated memory organization: Digital Equipment orporation PDP-8 used a -bit address to address 496 -bit words. IM 6 used a 4-bit address to address 6,777,6 8-bit bytes, or 4,94,4 -bit words. Intel 88 (8-bit predecessor to the 886 and the current Intel processors) used a 6-bit address to address 65,56 8-bit bytes. lock Diagram A basic memory system is shown here: k address lines are decoded to address k words of memory. Each word is n bits. Read and are single control lines defining the simplest of memory operations. k Lines k Read n Input Lines n Unit k s n its per n n Output Lines 7 8 Organization Example Example memory contents: A memory with address bits & 8 data bits has: k = and n = 8 so = 8 addresses labeled to 7. = 8 words of 8-bit data inary Decimal ontent asic Operations operations require the following: data written to, or read from, memory as required by the operation. specifies the memory location to operate on. The address lines carry this information into the memory. Typically: n bits specify locations of n words. An operation Information sent to the memory and interpreted as control information which specifies the type of operation to be performed. Typical operations are READ and WRITE. Others are READ followed by WRITE and a variety of operations associated with delivering blocks of data. Operation signals may also specify timing info. 9 asic Operations (continued) Operation Timing Read an operation that reads a data value stored in memory: Place a valid address on the address lines. Wait for the read data to become stable. an operation that writes a data value to memory: Place a valid address on the address lines and valid data on the data lines. Toggle the memory write control line Sometimes the read or write line is defined as a clock with precise timing information (e.g. Read lock, Strobe). Otherwise, it is just an interface signal. Sometimes memory must acknowledge that it has completed the Most basic memories are asynchronous Storage in latches or storage of electrical charge No clock ontrolled by control inputs and address Timing of signal changes and data observation is critical to the operation Read timing: Read cycle operation. lock ns T T T T4 T valid 65 ns valid opyright N. AYDIN. All rights reserved.

3 Operation Timing RAM Integrated ircuits timing: lock input ns T T T T4 T valid 75 ns cycle valid ritical times measured with respect to edges of write pulse (--): must be established at least a specified time before - and held for at least a specified time after - to avoid disturbing stored contents of other addresses must be established at least a specified time before - and held for at least a specified time after - to write correctly Types of random access memory Static information stored in latches Dynamic information stored as electrical charges on capacitors harge leaks off Periodic refresh of charge required Dependence on Power Supply Volatile loses stored information when power turned off Non-volatile retains information when power turned off 4 Static RAM ell Array of storage cells used to implement static RAM Storage ell SR Latch input for control Dual Rail Inputs and Dual Rail S R Outputs and Static RAM it Slice Represents all circuitry that is required for n -bit words S Multiple s R ontrol Lines: i one for each word Read / it Lines: n S R S R n it (b) Symbol it Read (a) Logic diagram 5 6 n - -it RAM I ell Arrays and oincident ion 4-to-6 Decoder To build a RAM I from a RAM slice, we need: Decoder decodes the n address lines to n word lines A -state buffer on the data permits RAM Is to be combined into a RAM with c n words A A A A input 6 x RAM (a) Symbol A A A A put hip it arrays can be very large => Large decoders Large fanouts for the bit lines The decoder size and fanouts can be reduced by approximately n by using a coincident ion in a -dimensional array Uses two decoders, one for words and one for bits becomes Row it becomes olumn See next slide for example A and A used for Row A and A for olumn (b) lock diagram 7 8 opyright N. AYDIN. All rights reserved.

4 ell Arrays and oincident ion (continued) RAM Is with > it/ A A Row decoder -to-4 Decoder put Row 4 8 it olumn decoder 5 9 it -to-4 Decoder with 6 4 it olumn 7 5 it length can be quite high. To better balance the number of words and word length, use Is with > bit/word See Figure 9-8 for example put bits put bits Row s 4 rows olumn s pairs of columns Enable A A hip 9 Making Larger Memories Making Wider Memories Using the lines, we can make larger memories from smaller ones by tying all address, data, and lines in parallel, and using the decoded higher order address bits to control. Using the 4- by -it memory from before, we construct a 6- by -it memory. A A Decoder D D D S D S In Out To construct wider memories from narrow ones, we tie the address and control lines in parallel and keep the data lines separate. For example, to make a 4- word by 4-bit memory from 4, 4-word by -bit memories Note: oth 6x and 4x4 memories take 4-chips and hold 6 bits of data. In Out Dynamic RAM (DRAM) Dynamic RAM (continued) asic Principle: Storage of information on capacitors. harge and discharge of capacitor to change stored value Use of transistor as switch to: Store charge harge or discharge See next slide for circuit, hydraulic analogy, and al model. D (a) T D D model To Pump (b) (c) (d) Stored Stored (e) Read Read (h) (f) (g) 4 opyright N. AYDIN. All rights reserved. 4

5 Dynamic RAM - it Slice Dynamic RAM - lock Diagram is driven by -state drivers Sense amplifier is used to change the small voltage change on into H or L In the electronics,,, and the sense amplifier are connected to make destructive read into non-destructive read n D D it D model D model (a) Logic diagram Sense amplifier Read n D D D (b) Symbol it lock Diagram See Figure 9-4 in text Refresh ontroller and Refresh ounter Read and Operations Application of row address Application of column address Why is the address split? Why is the row address applied first? 5 6 Dynamic RAM Read Timing DRAM Types lock RAS AS Output ns T T T T4 T Row Hi-Z olumn 65 ns Read cycle valid Types to be discussed Synchronous DRAM (SDRAM) Double Rate SDRAM (DDR SDRAM) RAMUS DRAM (RDRAM) Justification for effectiveness of these types DRAM often used as a part of a memory hierarchy (See details in chapter 4) Reads from DRAM bring data into lower levels of the hierarchy Transfers from DRAM involve multiple consecutively addressed words Many words are internally read within the DRAM Is using a single row address and captured within the memory This read involves a fairly long delay 7 8 DRAM Types (continued) Synchronous DRAM Justification for effectiveness of these types (continued) These words are then transferred out over the memory data bus using a series of clocked transfers These transfers have a low delay, so several can be done in a short time The column address is captured and used by a synchronous counter within the DRAM to provide consecutive column addresses for the transfers burst read the resulting multiple word read from consecutive addresses 9 Transfers to and from the DRAM are synchronize with a clock Synchronous registers appear on: input put put olumn address counter for addressing internal data to be transferred on each clock cycle beginning with the column address counts up to column address + burst size Example: data path width: word = 4 bytes urst size: 8 words = bytes clock frequency: 5 ns Latency time (from application of row address until first word available): 4 clock cycles Read cycle time: (4 + 8) x 5 ns = 6 ns andwidth: /(6 x -9 ) = 5 Mbytes/sec opyright N. AYDIN. All rights reserved. 5

6 Double Rate Synchronous DRAM Transfers data on both edges of the clock Provides a transfer rate of data words per clock cycle Example: Same as for synchronous DRAM Read cycle time = 6 ns andwidth: ( x )/(6 x -9 ) =.66 Mbytes/sec RAMUS DRAM (RDRAM) Uses a packet-based bus for interaction between the RDRAM Is and the memory bus to the processor The bus consists of: A -bit row address bus A 5-bit column address bus A 6 or 8-bit (for error correction) data bus The bus is synchronous and transfers on both edges of the clock Packets are 4-clock cycles long giving 8 transfers per packet representing: A -bit row address packet A -bit column address packet A 8 or 44-bit data packet Multiple memory banks are used to permit concurrent memory accesses with different row addresses The electronic design is sophisticated permitting very fast clock speeds Arrays of DRAM Integrated ircuits Similar to arrays of SRAM Is, but there are differences typically handled by an I called a DRAM controller: Separation of the address into row address and column address and timing their application Providing RAS and AS and timing their application Performing refresh operations at required intervals Providing status signals to the rest of the system (e.g., indicating whether or not the memory is active or is busy performing refresh) opyright N. AYDIN. All rights reserved. 6