Chapter 5. Internal Memory. Yonsei University

Transcription

1 Chapter 5 Internal Memory

2 Contents Main Memory Error Correction Advanced DRAM Organization 5-2

3 Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory(ram) Read-write memory Electrically, byte level Electrically Volatile Read-only memory(rom) Programmable ROM(PROM) Read-only memory Not possible Mask Erasable PROM(EPROM) Flash memory Electrically Erasable PROM(EEPROM) Read-mostly memory UV light, chip level Electrically, block level Electrically, byte level Electrically Nonvolatile 5-3

4 Memory Cell Operation 5-4

5 RAM Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic DRAM requires periodic charge refreshing to maintain data storage 5-5

6 DRAM Bits stored as charge in capacitors Charges leak Need refreshing even when it is powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower 5-6

7 DRAM 5-7

8 DRAM Operation Address line active when bit read or written Transistor switch closed (current flows) Write Voltage to bit line High for 1 low for 0 Then signal address line Transfers charge to capacitor Read Address line selected transistor turns on Charge from capacitor fed via bit line to sense amplifier Compares with reference value to determine 0 or 1 Capacitor charge must be restored 5-8

9 SRAM Bits stored as on/off switches No charges to leak No refreshing needed when it is powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache 5-9

10 SRAM 5-10

11 SRAM Operation Transistor arrangement gives stable logic state State 1 C 1 high, C 2 low T 1 T 4 off, T 2 T 3 on State 0 C 2 high, C 1 low T 2 T 3 off, T 1 T 4 on Address line transistors T 5 T 6 is switch Write apply value to B & compliment to B Read value is on line B 5-11

12 SRAM vs DRAM Both volatile Power needed to preserve data Dynamic cell Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units Static Faster Cache 5-12

13 Read Only Memory (ROM) Permanent storage Applications Microprogramming Library subroutines Systems programs (BIOS) Function tables Problems The data insertion step includes a large fixed cost No room for error Written during manufacture Very expensive for small runs 5-13

14 Types of ROM Written during manufacture Very expensive for small runs Programmable (once) PROM Needs special equipment to program Read mostly Erasable Programmable (EPROM) Erased by UV Electrically Erasable (EEPROM) Takes much longer to write than read Flash memory Erase whole memory electrically 5-14

15 Programmable ROM (PROM) Nonvolatile & Written only once Writing is performed electrically and may be performed by a supplier or customer at a time later than the original chip fabrication Needs special equipment to program 5-15

16 Read Mostly Memory (RMM) Read operations are far more frequent than write operations But for which nonvolatile storage is required EPROM EEPROM Flash 5-16

17 EPROM Erasable Programmable Storage cell must be erased by UV before written operation Read and written electrically More expensive than PROM Advantage of multiple update capability 5-17

18 Electrically Erasable PROM(EEPROM) A read-mostly memory that can be written into at any time without erasing prior contents Takes much longer to write than read Advantage Nonvolatility with the flexibility of being updatable in place using ordinary bus control, address, data lines 5-18

19 Flash Memory Erase whole memory electrically Entire flash memory can be erased in one or few seconds (faster than EPROM) Possible to erase just blocks Impossible to erase byte-level Use only one transistor per bit Achieves high density 5-19

20 Chip Logic A 16Mbit chip can be organized as 1M of 16 bit words A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on A 16Mbit chip can be organized as a 2048 x 2048 x 4bit array Reduces the number of address pins Multiplex row address and column address 11 pins to address (2 11 =2048) Adding one more pin doubles range of values So the memory size grows by a factor of

21 Refreshing Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance 5-21

22 Typical 16 Mb DRAM (4M x 4) 5-22

23 Chip Packaging Pins support following signal lines Address of words being accessed For 1M words, a total of 20(2 20 =1M) pins needed(a0-a19) Data to be read out, consisting of 8 lines(d0-d7) Power supply to the chip(vcc) Ground pin(vss) Chip enable (CE)pin Program voltage(vpp) that is supplied during programming(writing operation) 5-23

24 Typical Memory Package 5-24

25 Module Organization How a memory module consisting of 256K 8-bit words could be organized For 256K word, 18-bit address is needed and is supplied to the module from some external sources 5-25

26 Module Organization Possible organization of a memory consisting of 1M word by 8 bits per word Need four columns of chips, each column containing 256K words arranged 5-26

27 1-Mbyte Memory Organisation 5-27

28 Error Correction Error Correction Hard Failure Permanent physical defect Memory cell or cells affected cannot reliably store data and become stuck at 0 or 1or switch erratically between 0 and 1 Caused by harsh environmental abuse, manufacturing defects and wear Soft Error Random, non-destructive No permanent damage to memory Caused by power supply problems or alpha particles Detected using Hamming error correcting code 5-28

29 Error - Correcting Code When data are to be read into memory, a function f is performed to produce a code Both the data and the code are stored If M-bit data word and K-bit code, the stored word is M+K bits 5-29

30 Error Correction If M-bit word of data is stored, and code is K bit, then actual size of stored word is M+K bits New set of K code is generated from M data bits compared with fetched code bits Comparison one of three results No errors detected The fetched data bits sent out An error is detected and it is possible to correct error The data bit plus error-correction bits fed into corrector which produces a corrected set of M bits to be sent out An error is detected, but it is impossible to correct it This condition reported 5-30

31 Hamming Error-Correcting Code 5-31

32 Hamming Code Parity bits By checking the parity bits, discrepancies found in circle A and circle C, but not in circle B Only one of the seven compartments is in A and C but not B The error can be corrected by changing that bit Syndrome word : result of comparison of bit-by-bit Each bit of syndrome is 0 or 1 according to if there is or is not a match in position for two input The syndrome word is K bits wide and has a range between 0 and 2 K -1 2 K 1 M + k 5-32

33 Increase in Word Length Data Bits Single-Error- Correction Single-Error Correction/Double- Error Detection Check Bits %Increase Check Bits %Increase

34 Error Correction To generate 4-bit syndrome If the syndrome contains all 0s, no error is detected If the syndrome contains one and only one bit set to 1, an error occurs in one of 4 check bits No correction needed If the syndrome contains more than one bit set to 1, numerical value of syndrome indicates the position of data bit in error This data bit is inverted for correction 5-34

35 Layout of Data Bits & Check Bits 5-35

36 Layout of Data Bits & Check Bits To achieve these characteristics, data and check bits are arranged into a 12-bit word as depicted Those bit positions whose position numbers are powers of 2 are designated as check bits 5-36

37 Yonsei University 5-37 Error Correction Error Correction Each check bit operates on every data bit position whose position number contains 1 in corresponding column position M M M M C M M M M C M M M M M C M M M M M C = = = =

38 Check Bit Degeneration Data and check bits are positioned properly in the 12-bit word. By laying out position number of each data bit in columns, the 1s in each row indicates data bits checked by the check bit for that row 5-38

39 Check Bit Degeneration 5-39

40 Error Correction Single-error-correcting(SEC) Single-error-correcting, double-error -detecting(sec-ded) 5-40

41 Hamming SEC-DEC Code 5-41

42 Error Correction Error Correction IBM 30xx implementations use 8-bit SEC- DED code for each 64 bits of data in main memory Size of main memory is 12% larger than apparent to the user VAX computer use 7-bit SEC-DED for each 32 bits of memory, for 22% overhead A number of contemporary DRAMs use 9 check bits for each 128 bits of data, for 7% overhead 5-42

43 Advanced DRAM Organization Advanced DRAM organization Basic DRAM same since first RAM chips Enhanced DRAM Contains small SRAM as well SRAM holds last line read (c.f. Cache!) Cache DRAM Larger SRAM component Use as cache or serial buffer 5-43

44 Synchronous DRAM(SDRAM) Advanced DRAM organization SDRAM exchanges the data with the processor synchronized to an external clock signal and running at the full speed of the proc./mem. bus without imposing wait states With synchronous access, the DRAM moves data in & out under control of the system clock Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else 5-44

45 Synchronous DRAM(SDRAM) Advanced DRAM organization Burst mode allows SDRAM to set up stream of data and fire it out in block To eliminate the address setup time and row and column line precharge time after first access In burst mode, a series of data bits can be clocked out rapidly after the first bit has been accessed Useful when all bits are to be accessed in sequence and in the same row of the array as the initial access 5-45

46 SDRAM Advanced DRAM organization Dual-bank architecture that improves opportunities for on-chip parallelism The mode register and associated control logic is another key feature differentiating SDRAMs from conventional DRAMs It provides a mechanism to customize the SDRAM to suit specific system needs The mode register specifies the burst length SDRAM performs best when it is transferring large blocks of data serially DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) 5-46

47 IBM 64Mb SDRAM Advanced DRAM organization 5-47

48 SDRAM Operation Advanced DRAM organization 5-48

49 Rambus DRAM(RDRAM) 5-49 Advanced DRAM organization A more revolutionary approach to the memory-bandwidth problem Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package all pins on one side The chip exchanges data with processor over 28 wires no more than 12cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps The special RDRAM bus delivers address and control information using an asynchronous block-oriented protocol Asynchronous block protocol 480ns access time Then 1.6 Gbps An RDRAM gets a memory request over the high-speed bus

50 RAMBUS Diagram Advanced DRAM organization 5-50

51 Cache DRAM(CDRAM) Advanced DRAM organization Includes a larger SRAM cache than EDRAM SRAM on the CDRAM can be used in two ways Used as a true cache, consisting of a number of 64-bit lines The cache mode is effective for ordinary random access to memory Used as a buffer to support the serial access of a block of data 5-51