Current and Projected Digital Complexity of DMT VDSL

Transcription

1 June 1, Standards Project: T1E1.4: VDSL Title: Current and Projected Digital Complexity of DMT VDSL Source: Texas Instruments Author: C. S. Modlin J. S. Chow Texas Instruments 2043 Samaritan Drive San Jose, CA Phone: Fax: Date: June 7, 1999 Distribution: T1E1.4 Technical Subcommittee Working Group Abstract: We estimate the digital complexity of the current DMT VDSL line code proposal by looking at available solutions and by scaling them in current and future technologies. The purpose of this contribution is to show that DMT VDSL is a competitive and deployable solution today. Notice: This contribution has been prepared to assist the T1E1.4 Technical Subcommittee Working Group. It is submitted for discussion only and is not to be construed as binding on Texas Instruments. The contents are subject to change after further study. Texas Instruments specifically reserves the right to add to, amend, or withdraw the statements contained herein.

2 June 1, Measure of complexity To a first degree, complexity can be measured by power consumption and chip area. There is often a trade-off between power consumption and chip area. For example, a 16 tap filter could be implemented with one multiplier and a very fast clock or with 16 multipliers and a much slower clock. The faster design requires less chip area but consumes roughly the same amount of power. A faster design might consume slightly more power since pipeline stages and extra control logic are often needed. The power vs. gate count trade-offs depend on detailed design practices. Our designs have been optimized for power consumption. 2.0 Technology scaling Following the trend at Texas Instruments since 1995, logic density is doubling every year and with it, the core supply voltage is being cut by about 70% every year. CMOS technology is often specified by the transistor channel length and the core voltage. I/O voltages are usually higher to allow inter operability with other older parts. The active area of a CMOS chip is linearly related to the area of a transistor and varies roughly as the square of the transistor channel length. The core power consumption of a CMOS chip is linearly related to CV 2 f where C is the capacitance, V is the core voltage, and f is the frequency. As we mentioned, the trend for V 2 is to be cut in half every year. There does not appear to be any simple rule that governs the capacitance. Capacitance is proportional to the area divided by the oxide thickness. Although the area is also being halved every year, the oxide thickness is also decreasing. Typically, however, the capacitance does decrease as the process improves. For VDSL, the frequency is not varying over time. Table 1 lists four generations of ASIC technology along with estimates of area and power consumption. The number 100 is used as a reference for area and power. process area power.35µ, 3.3V 100 a 100 a.25µ, 2.5V µ, 1.8V µ, 1.5V Table 1 Process comparison a. 100 is a reference value, the units are arbitrary 3.0 Current solutions Texas Instruments has developed a DMT VDSL chipset and has investigated an FDD solution compliant with [MA-050]. The existing chipset is TDD DMT with a 256 tone FFT. The [MA-050] compliant solution is FDD with 2048 tones. By investigating the existing TDD solution in its first generation and in today s technology, we estimate the complexity of the FDD DMT line code proposal.

3 June 1, µ / 3.3V first generation The first generation of Texas Instruments VDSL chipsets, developed in 1997, is in.35µ CMOS with a 3.3V core and 3.3V I/Os. This is a two chip solution, each chip about 110mm 2 with a total combined power consumption of about 1.5W transmitting over an 11 MHz bandwidth (22 MHz sampling rate) including I/Os. The features of this chipset are very similar to those described by Alcatel in their ISSCC contribution [ISSCC:Alcatel] except that there is no ATM interface and the on chip interleaver memory is 16Kbytes. This solution was created primarily as a proof of concept. We continue to make improvements to this design to reduce the power and chip size. However, it is difficult to estimate the degree of improvement objectively. Therefore, we use this design as a baseline µ / 1.8V core, 3.3V I/O, today s technology Projecting the first generation solution onto today s technology, we estimate the size and power consumption of our TDD solution. This estimate is based on scaling arguments and on our experience. We include an ATM interface with this projection. This projection does not include any improvements or optimization to our design. Based on scaling the first generation design, the same design in today s.18µ technology would be about 58mm 2. Adding about 10% for an ATM interface gives about 65mm 2. This is very close to what we have projected using a more accurate appraisal. Also based on scaling arguments, we project that the power consumption will be about 228mW. This roughly includes I/O power since the two-chip solution has many more I/Os than a single chip would need. The I/O power consumption assuming an 11MHz bandwidth and 52Mbps data interface is roughly 13% of the 228mW. 4.0 Proposed FDD DMT Solution To arrive at an estimate for the complexity of the proposed FDD solution [MA-050], we can scale our current solution and account for the increased FFT size, the need to do a simultaneous FFT and IFFT, the increase in interleaver memory, and the removal of the time domain equalizer (TEQ). We will, as has been proposed in [BM-066], assume enough interleaver memory to correct up to 500µs of impulse noise at 26 Mb/s. The impact of the larger FFT is, as has been pointed out before [BM-066], primarily in the size of the RAMs but also includes the multipliers and control logic. The complexity increase in logic is approximately a log 2 (2048)/log 2 (256) = 11/8 increase. The memory increase is linear with the FFT size. We first adjust the chip size considering the factor of 11/8 increase in logic. In the.15µ process, it is sufficient to say that the increase in logic is certainly under 1 mm 2. Let us just say that it is equal to 1 mm 2. Using in place memory optimization techniques for the FFT (see for example [IEEE:CIRSYS]), we need enough RAM to store 2N values where N is the FFT size. These RAMs add to roughly 2.5mm 2 in.15µ. Although the design could be done with a single FFT/IFFT shared in time, for the benefit of discussion, we will assume we need two of them. In addition to these RAMs, we require other coefficient RAMs for each of the 2048 tones. The coefficient RAMs are considerably smaller than the FFT RAMs. These are the RAMs that are needed for DMT that are not needed for a single carrier system. Subtracting off what we would have needed for a single 256 tone FFT we arrive at the additional memory required for the FDD DMT VDSL solution. This is roughly 4mm 2. Although we have argued in the past [T1E1.4/96-337] that DMT has an inherent advantage in terms of interleaver size since most impulse noise is band limited, we will assume here that impulse noise is wide band. This way there is no difference in the memory requirements between single carrier and multi-carrier. There is a trade-off between interleaver memory required and coding gain. We will assume a (144,128) code when evaluating the interleaver memory required. This codeword size and degree of redundancy is a reasonable compromise between coding gain and interleaver requirements for any line code.

4 June 1, The amount of interleaver memory required can be approximated as N*depth bytes with the correction capability at t*depth bytes where N is the codeword size (144) and t is the correction capability (8). To correct 500µs at 26 Mbps means correcting a burst of 1625 bytes. This means the depth is 203 and the size of the memory is about 30 Kbytes. This is the combined interleaver and deinterleaver for an efficient implementation. A 2048 tone DMT design does not need a TEQ filter. The reason is that even a relatively long cyclic prefix adds only a small amount to the overhead. Even 256 samples, over six times longer than what we are using in our TDD design, represents under 6% of overhead. This can be compared with the 20% excess bandwidth typically used in single carrier systems. The 16 tap TEQ design in our TDD designs is done with 16 multipliers and occupies roughly 3mm 2 in.18µ technology. Scaling, this to.15µ comes to roughly 2mm 2 that we will subtract. The total area of the extra logic and RAMs for the FFT, coefficients, and interleaver add to about 6mm 2 in.15µ technology. Subtracting the TEQ, we should add 4mm 2 to our current design to estimate the extra size from implementing the FDD DMT VDSL solution. We can now estimate the size and power of the FDD DMT VDSL solution in the latest technology using our existing designs. Scaling the 65mm 2 in.18µ to.15µ (about 45mm 2 ) and adding about 4mm 2 for the additional complexity of the larger FFT and interleaver, the chip would be about 50mm 2. For power consumption again we can scale and add. Scaling the.18µ chip at 228mW by first subtracting the I/O power and then scaling to.15µ and adding back the I/O power gives 129mW. Adding about 10% to the core power for the larger RAMs and increased logic brings a conservative estimate to about 138mW. This is an estimate for the 2048 tone (4096 point), FDD DMT VDSL proposal. Some features include completely flexible band allocation symmetric and asymmetric data rates radio frequency interference cancellation narrow band egress notching ADSL compatibility sufficient interleaving to correct a 500µs impulse at 26Mbps with a (144,128) Reed Solomon code variable Reed Solomon codeword redundancy from 2 to 16 bytes (correction from 1 to 8 bytes) ATM-TC and STM-TC interface with 32 cells of transmit and 32 cells of receive buffering 5.0 FDD DMT VDSL solution over time Table 2 is a rough estimate of the active die size and power consumption of the FDD DMT VDSL solution over the next three years if semiconductor technology follows its current trend. The power consumption numbers assume a factor of 3 decrease in core power every year. We also assume that by 2002, the I/O power will be 2.5V instead of 3.3V. These numbers assume only process improvements and do not consider improvements to our design over time.

5 June 1, year size power consumption mm 2 138mW mm 2 66mW mm 2 32mW a Table 2 Estimate of size and power consumption of the FDD DMT VDSL [MA-050] solution over the next three years. a. 2.5V I/Os 6.0 Summary This contribution is for information only. This contribution has estimated the complexity and power consumption of a DMT-FDD VDSL solution based upon an operating DMT-TDD VDSL solution. This DMT-FDD solution would be deployable today and will see continued reduction in power and complexity over the next three years based on normal semiconductor projections. References [ISSCC:Alcatel]Viethen, D., et al., A 70 Mb/s Variable-Rate DMT-based Modem for VDSL, ISSCC Digest of Technical Papers, San Francisco, CA, pp , February [BM-066]Joshi, R et al., G.vdsl: Complexity Comparison of QAM VDSL and DMT VDSL Transceiver Integrated Circuits Based on Proceedings in ISSCC 99, ITU contribution BM-066, Boston, MA, May [T1E1.4/96-337]Modlin, C et al., A Comparison of Proposed FEC and interleaving Schemes for DMT and CAP, T1E1.4 contribution T1E1.4/96-337, November [IEEE:CIRSYS] Johnson, L, Conflict Free Memory Addressing for Dedicated FFT Hardware, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol 39, No 5, May [MA-050] Pollet, T. et al., DMT based Physical Medium Specific proposal for G.vdsl, ITU contribution MA-050, Melbourne, Australia, April, 1999.