ECE 747 Digital Signal Processing Architecture. DSP Implementation Architectures
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1 ECE 747 Digital Signal Processing Architecture DSP Implementation Architectures Spring 2006 W. Rhett Davis NC State University W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 1
2 My Goal Challenge you to use the techniques you have learned in this class to design the next generation of DSP hardware When you undertake a new design, the most important question for you to answer is whether or not it will work better than an existing design.» Faster» Longer Battery Life» Cheaper W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 2
3 Today s Lecture Types of DSP Implementations Comparison of Hardware Efficiency The Promise of Systems-on-Chip What s keeping us from getting there? W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 3
4 ECE 747-Style Design reg. file reg. file MAC Σ add shift Up to now, you have been designing signal-flow graphs and converting them into hardware, through a design process some call direct-mapping of algorithms But what are the other choices? W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 4
5 Efficiency-Flexibility Trade-Off Flexibility Embedded Processor Embedded DSP Embedded FPGA Direct Mapped Hardware 100x-1000x Difference in Power Efficiency W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 5
6 Computational Efficiency Metrics Definition: MOPS» Millions of algorithmically defined arithmetic operations (e.g. multiply, add, shift) in a GP processor several instructions per useful operation Figures of merit» MOPS/mW - Energy efficiency (battery life)» MOPS/mm 2 - Area efficiency (cost) Optimization of these efficiencies is the basic goal assuming functionality is met W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 6
7 Dedicated Designs 10X-100X More Efficient Low Energy Efficiency / Battery Life (MOPS/mW) due to overhead, lack of parallelism, high supply voltages PPC-95 PPC1-SOI-00 Sparc-95 Sparc2-97 PPC2-SOI-00 Sparc1-97 X86-97 Alpha-00 Alpha-97 PPC-00 SA-DSP-98 Hit-DSP-98 Fuj-DSP2-98 Fuj-DSP1-00 NEC-DSP-98 MPEG2-99 Encrypt Microprocessors General Purpose DSP Dedicated 2 orders of magnitude MOPS/mW MUD-98 MPEG a-01 (Brodersen, ISSCC 2002) W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 7
8 Potential of Direct Mapping In.25 micron a multiplier requires.05 mm 2 and 7pJ per operation at 1 V. Adders and registers are about 10 times smaller and 10 times lower energy Lets implement a 50mm 2,.25 micron chip using adders, registers and multipliers We can have 2000 adders/registers and 200 multipliers in less than 1/2 of the chip, also assume 1/3 of power goes into clocks 25 MHz clock (1 volt) gives ~50 Gops at 100mW 500 MOPS/mW and 1000 MOPS/mm 2 W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 8
9 Why is Direct Mapping Better? Low Area Efficiency / High Cost (MOPS/mm 2 ) due to large on-chip memories Low Energy Efficiency due to long wires and overhead of multiplexing the datapath 16x16 multiplier (.05 mm 2 ) DSP processor with 1 multiplier (25 mm 2 ) W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 9
10 Results in Fully Parallel Solutions Reducing supply voltage saves energy: E = CV 2 Energy Area 64-point FFT Energy per Transform (nj) 16-State Viterbi Decoder Energy per Decoded bit (nj) 64-point FFT Transforms per second per unit area (Trans/ms/mm 2 ) 16-State Viterbi Decoder Decode rate per unit area (kb/s/mm 2 ) Direct-Mapped Hardware , ,000 FPGA Low-Power DSP High-Performance DSP (numbers taken from vendor-published benchmarks) Orders of magnitude lower efficiency even for an optimized processor architecture (N. Zhang) W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 10
11 Reconfigurability can get the best of both worlds Energy per Transform (J) Lower limit Function-specific reconfigurable hardware Data-path reconfigurable processor FPGA Low-power DSP High-performance DSP FFT size Energy per Transform vs. FFT size (Transforms per Second)/(Silicon Area) (Trans/s/mm 2 ) Function-specific reconfigurable hardware Data-path reconfigurable processor FPGA Low-power DSP High-performance DSP FFT size Transforms per Second per mm 2 vs. FFT size * All results are scaled to 0.18µm W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 11
12 Enter the Era of Systems-on-Chip MCU Gates (RTL) ROM DSP RAM Cellular Phone Baseband SOC (Courtesy Mike McMahon, Texas Instruments) W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 12
13 What is a System-on-Chip? a complex IC that integrates the major functional elements of a complete endproduct into a single chip... incorporates at least one programmable processor, onchip memory, and accelerating functionunits...» Winning the SoC Revolution, Martin & Chang 2003 (paraphrasing from Dataquest) W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 13
14 Problem: Design Productivity Gap 1000's of Transistors 1,000, ,000 10,000 1, designers per chip designers per designer per year The main message in 2001 is this: Cost of design is the greatest threat to continuation of the semiconductor roadmap ITRS $20M Average cost for an SOC (includes only software licenses & slaries) ITRS W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 14
15 Next Lectures Survey of System-Level Design Techniques» What tools can I use to get performance estimates faster, with less work? Methods of Scaling» How do I convert my 180 nm performance estimates into the latest technology? W. Rhett Davis NC State University ECE 406 Spring 2006 Slide 15
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