A 20 GSa/s 8b ADC with a 1 MB Memory in 0.18 µm CMOS

Transcription

1 A 20 GSa/s 8b ADC with a 1 MB Memory in 0.18 µm CMOS Ken Poulton, Robert Neff, Brian Setterberg, Bernd Wuppermann, Tom Kopley, Robert Jewett, Jorge Pernillo, Charles Tan, Allen Montijo 1 Agilent Laboratories, Palo Alto, California 1 Agilent Technologies, Colorado Springs, Colorado

2 Background Design Goals: 20 GSa/s, 8-bit conversions -1 db bandwidth of 6-GHz Low power (less than 15 Watts) On-chip memory for storage of 20-Gbyte/s data Design Approach: Massively parallel interleaving Small transistors for low power Open-loop circuits for high speed Extensive calibration

3 Application: Digital Oscilloscopes Probe Preamp ADC Display & Analysis Calibrator Signals System CPU Simplified oscilloscope block diagram Inputs band-limited to ~ Fsample/3. External calibrator signals. Calibration coefficients computed by system CPU.

4 ADC Module Block Diagram 1 GHz Clock V in SiGe BiCMOS Buffer Chip Clock Gen T/Hs Pipeline ADCs Radix Converters -Slice Decimator 8 Memory Controllers 1 MByte SRAM 2 muxes CMOS ADC Chip Please, don t rotate this page. I like it in landscape mode, thank you very much. asdfasdfasfdsafds asdfasfdsadfsadfsadf asdfasdfasdfasdfasdfsadf

5 Input Buffer Chip Design Goals: Flat gain response from DC to 6 GHz. Drive the ADC chip s 4pF input capacitance through chip-to-chip wirebonds. Well-matched 50-ohm input termination. Low input capacitance. Adjustable input resistance.

6 Simplified SiGe buffer chip schematic Vin Vout 4pF Vin 4pF ADC Chip

7 DLL 1 GHz Input 10 Clocks 20 Clocks Clock Generator Johnson Counters 4 Delay Adjust PD Interpolator Sampling Clocks (250 MHz) 50 ps spacing 4

8 Track and Hold Front End SCK1 CCK1 V in SCK CCK RS1 V/I Iout1 interleaved outputs (250 MSa/s) Track & Hold Charge Comp. RS Reset V/I C hold I out Full 6-GHz signal bandwidth at C hold. Transconductor (V/I) output drives pipeline ADC. Reset prevents signal-dependent kickback onto V in.

9 Pipeline ADC Required performance: 250 MSa/s. 8 bits. Design approach: One bit per stage pipeline ADC for high speed. Open loop amplifiers for fast settling. Reduced radix for redundancy. Current-mode signals enable simple amplifiers that occupy minimal area.

10 Pipeline ADC Block Diagram Corrected 8-bit binary output Radix converter 12 bits, radix 1.6 De-skew latches Input Clock 1-bit 1-bit 1-bit quantizer quantizer quantizer Input Clock T/H FF DAC G Residue G=1.6

11 Current-Mode T/H and Gain I in I out Gain=M W M*W Good Linearity: Current mirrors with cascodes are 8 bit linear. Poor Accuracy: Gain and offset errors.

12 Simplified Pipeline Stage Schematic Comparator Clock Vbias T/H Clock DAC Residue Currents Input Currents W Track & Hold 1.6 W Gain = 1.6

13 Radix Converter - Principle of Operation Calculate and download bit weights during calibration. Bit 11 weight 11 Bit 10 weight 10 Bit 9 weight 9 Σ Binary Output (8 bits) Bit 1 weight 1 Bit 0 weight 0 Output = b 11.w 11 + b 10.w b 1.w 1 + b 0.w 0 Look-up table would be an alternative architecture. This ADC uses a hybrid look-up/adder.

14 Pipeline ADC Performance Outstanding speed/power ratio 250 MSa/s 57 mw total 9 mw V/I buffer 28 mw pipeline 20 mw radix converter Small area 0.12 mm 2

15 On-chip Memory System Goals Full-speed 160-Gbit/sec data storage. Store data at user-selectable sample rates. 1-Mbyte storage capacity. Low digital noise coupling to analog circuits. Low impact on fabrication yield. Memory controller synthesized from Verilog.

16 Memory System Block Diagram 20 GS/s data from radix converter 640 Decimator CK0 Memory Group 0 CK1 Memory Group 1 CK2 Memory Group 2 CK3 Memory Group 3 CK4 Memory Group 4 CK5 CK6 CK7 Memory Group 5 Memory Group 6 Memory Group GS/s Readout MUX 16 Data output

17 Memory Design Approach: Programmable decimator for adjustable samplerate storage. Static RAM with built-in self test (BIST) and redundancy. Staggered writes - Full-width data path is * 8 bits = 640 pairs. - 8 memory group clocks staggered at 0.5-ns intervals to spread out supply-current spikes. Dummy writes during non-acquisition intervals keep chip temperature constant and maintain calibration accuracy.

18 ck Input data from 10 ADCs data 4 ns Memory Group (1 of 8) Memory Controller BIST 410w x b SRAM 8 ns 410w x b SRAM 410w x b SRAM 410w x b SRAM 410w x b SRAM 410w x b SRAM 8 ns Spare 16 blocks per row + 1 spare blocks BIST runs at power-up. Defective blocks are auto-detected and replaced by spares. Precharged data lines minimize pattern-dependent noise.

19 Calibration Clock External Lookup Table Radix Converters Pipeline ADCs T/H + V/I Clock Gen. Vin Timing Adjust INL Correction Per-ADC gain & offset DACs Bit weights

20 Offline Calibration Voltage Calibration Apply a slow ramp input, observe ADC radix bits. Adjust analog gain and offset for each path. Use least squares fit on a large record to find optimal bit weights and 3rd harmonic fit. Least squares fit minimizes INL. Timing Calibration Apply a pulse train with fast edges. Use an FFT to measure phase delay on each T/H. Adjust time delays and iterate.

21 Buffer Chip ADC Chip Pipelines Radix Converters Memory Controllers SRAM Array 1.2 x 2.6mm buffer chip, 14 x 14mm ADC chip.

22 Acquisition Before Calibration 250 ADC Code (LSBs) Time (ns) ~ 3.5 effective bits

23 Acquisition With Calibration ADC Code Equivalent Time (ns) Fs = 20 GSa/s Fin = MHz 6.4 effective bits

24 Acquisition With Calibration Error (LSBs) ADC Code Equivalent Time (ns) Fs = 20 GSa/s Fin = MHz 6.4 effective bits

25 Calibrated, With 5 GHz Input Error (LSBs) ADC Code Equivalent Time (ps) Fs = 20 GSa/s Fin = MHz 5.0 effective bits

26 Static Linearity INL (LSBs) DNL (LSBs) Intrinsic INL INL with lookup table ADC code

27 ADC Effective Bits vs Input Frequency 8 7 Effective Bits Noise-limited Jitter-limited Input amplitude 95% of full scale. 0 10M 20M 50M 100M 200M 500M 1G 2G 5G 10G Input Frequency (Hz)

28 ADC Amplitude Response Amplitude Response (db) M 200M 400M 1G 2G 4G 10G Input Frequency (Hz) -1 db at 5.9 GHz -3 db at 6.6 GHz

29 Sample Rate Resolution INL Intrinsic With linearity correction DNL Bandwidth 500 MHz 6 GHz input Jitter Input Range ADC Key Specs 20 GSa/s 8 bits +1.7 LSBs +0.4 LSBs +0.3 LSBs 6.6 GHz 6.5 effective bits 4.6 effective bits 0.7 ps rms 0.25 Vpk differential Buffer Chip ADC Chip Input Capacitance 0.2 pf 4 pf Power 1 W 9 W Chip Size 1.2 x 2.6 mm 14 x 14 mm Technology 40-GHz SiGe BiCMOS 0.18-µm CMOS Transistors M Package 438-ball BGA

30 Published ADC Performance 8 7 Commercial Datasheet CMOS 8 bit Bipolar 8 bit ENOB at Fs/4 6 5 Commercial Datasheet ISSCC ps rms clock jitter 1 ps rms clock jitter ISSCC 2002 VLSI 1997 This work 4 3 1G 2G 4G 10G 20G 40G Sample Rate

31 Energy per Conversion Step Energy FOM (pj/conversion/level) Commercial Datasheet Commercial Datasheet CMOS 8 bit Bipolar 8 bit ISSCC 1991 ISSCC 2002 FOM 1 VLSI Power ( 2 ERBW )2 ENOB This work 1G 2G 4G 10G 20G 40G Sample Rate (Fs) (Hz) = Full System Excludes memory power 1 G. Geelen, A 6b 1.1GSample/s CMOS A/D Converter, 2001 ISSCC Digest of Technical Papers, pp

32 Energy per Sample (Watts/GSa/s) Energy per Sample Datasheet Datasheet CMOS 8 bit Bipolar 8 bit ISSCC 1991 VLSI 1997 ISSCC 2002 Nikkei Electronics 2002 This work (includes memory system power) 1G 2G 4G 10G 20G 40G Sample Rate (Fs) (Hz)

33 Summary Features: interleaved ADCs with an -phase precision clock generator. SiGe buffer chip to drive the 4-pF ADC chip input. 1-MB on-chip memory. Extensive calibration to achieve accuracy. Results: Sample rate 5x higher than any other CMOS ADC and 2x higher than any ADC of 6 or more bits. Highest reported ENOB at 5 GHz input frequency. Power consumption of only 500 mw per Gsample.