Computer Organization

Transcription

1 Computer Organization Dr. Lokesh Chouhan Assistant Professor Computer Science and Engineering (CSE) Department National Institute of Technology (NIT) Hamirpur (H.P.) INDIA Website:

2 Theory Lab Overview of the Course General System Architecture Processor Design Computer Arithmetic Control Design I/O Organization & Memory Hierarchy Introduction to Parallelism CO Simulator ( Java Run Time Environment) Assignments Case Studies Programming

3 Overview of the Course 1. J.P. Hayes, Computer architecture & Organization,McGraw Hill. 2. William Stallings, Computer Organization and Architecture, Designing for Performance, Pearson Education Asia. 3. M. Morris Mano, Computer system architecture. PHI 4. David A. Patterson & John. L. Hennessy, Computer Architecture. A quantitative Approach. Morgan Kaufmann.

4 Introduction

5 INTRODUCTION Definitions Stored Programme Von Neumann Machine

6 What s In It For Me? In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary. Insight into fast/slow operations that are easy/hard to implementation hardware Experience with the design process in the context of a large complex (hardware) design. Functional Spec --> Control & Datapath --> Physical implementation Modern CAD tools 6

7 Computer Architecture - Definition Computer Architecture = ISA + MO Instruction Set Architecture What the executable can see as underlying hardware Logical View Machine Organization How the hardware implements ISA? Physical View 7

8 Computer Architecture Changing Definition 1950s to 1960s: Computer Architecture Course: Computer Arithmetic 1970s to mid 1980s: Computer Architecture Course: Instruction Set Design, especially ISA appropriate for compilers 1990s: Computer Architecture Course: Design of CPU, memory system, I/O system, Multiprocessors, Networks 2000s: Computer Architecture Course: Non Von-Neumann architectures, Reconfiguration DNA Computing, Quantum Computing???? 8

9 The Big Picture Processor Input Control Memory Datapath Output Since 1946 all computers have had 5 components!!! 9

10 Storing of Program and Data in Memory A stored program concept is one in which first the program and data are stored in the main memory and then the processor fetches instructions and executes them, one after another. 10

11 The Von Neumann Architecture Named after John von Neumann, Princeton, he designed a computer architecture whereby data and instructions would be retrieved from memory, operated on by an ALU, and moved back to memory (or I/O) This architecture is the basis for most modern computers (only parallel processors and a few other unique architectures use a different model)

12 Principles Von Neumann Architecture Data and instructions are both stored in the main memory(stored program concept) The content of the memory is addressable by location (without regard to what is stored in that location) Instructions are executed sequentially unless the order is explicitly modified The basic architecture of the computer consists of: Computer Data CPU Bus Control Main Memory 12

13 Von Neumann Architecture A more complete view of the computer system architecture that integrates interaction (human or otherwise) consists of: Computer Computer System CPU Data Bus Control Main Memory Bus Input Device Output Device Five Main Components: 1. CPU 2. Main Memory (RAM) 3. I/O Devices 4. Mass Storage 5. Interconnection network (Bus) Bus Secondary Storage Device 13

14 Example Organization TI SuperSPARC tm TMS390Z50 in Sun SPARCstation20 MBus Module SuperSPARC Floating-point Unit Integer Unit L2 $ CC MBus DRAM Controller Inst Cache Ref MMU Bus Interface Data Cache Store Buffer L64852 SBus SBus DMA SBus Cards MBus control M-S Adapter SCSI Ethernet STDIO serial kbd mouse audio RTC Floppy 14

15 Another view of a digital computer 15

16 The MIPS R3000 ISA (Summary) Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management Special R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP OP OP rs rt rd sa funct rs rt immediate jump target 16

17 What is Computer Architecture? Application Operating System CSD-221 Compiler Firmware Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design Layout Instruction Set Architecture Coordination of many levels of abstraction Under a rapidly changing set of forces Design, Measurement, and Evaluation 17

18 Impact of changing ISA Early 1990 s Apple switched instruction set architecture of the Macintosh From Motorola based machines To PowerPC architecture Intel 80x86 Family: many implementations of same architecture program written in 1978 for 8086 can be run on latest Pentium chip 18

19 Factors affecting ISA??? Technology Programming Languages Applications Computer Architecture Cleverness Operating Systems History 19

20 ISA: Critical Interface software instruction set hardware Examples: 80x86 50,000,000 vs. MIPS 5500,000??? 20

21 CO vs CA Computer Organization Computer Architecture Often called microarchitecture (low level) Transparent from programmer (ex. a programmer does not worry much how addition is implemented in hardware) Computer architecture (a bit higher level) Programmer view (i.e. Programmer has to be aware of which instruction set used) Physical components (Circuit design, Adders, Signals, Peripherals) Logic (Instruction set, Addressing modes, Data types, Cache optimization) How to do? (implementation of the architecture) What to do? (Instruction set) 21

22 Moore s Law How small can we make transistors? How densely can we pack chips? No one can say for sure In 1965, Intel founder Gordon Moore stated, The density of transistors in an integrated circuit will double every year. The current version of this prediction is usually conveyed as the density of silicon chips doubles every 18 months Using current technology, Moore s Law cannot hold forever There are physical and financial limitations At the current rate of miniaturization, it would take about 500 years to put the entire solar system on a chip Cost may be the ultimate constraint 22

23 The Computer Level Hierarchy Through the principle of abstraction, we can imagine the machine to be built from a hierarchy of levels, in which each level has a specific function and exists as a distinct hypothetical Machine Abstraction is the ability to focus on important aspects of a situation at a higher level while ignoring the underlying complex details We call the hypothetical computer at each level a virtual machine. Each level s virtual machine executes its own particular set of instructions, calling upon machines at lower levels to carry out the tasks when necessary UNIT-1 Computer 23 Organization

24 The Computer Level Hierarchy Level 6: The User Level Composed of applications and is the level with which everyone is most familiar. At this level, we run programs such as word processors, graphics packages, or games. The lower levels are nearly invisible from the User Level. 24

25 Level 5: High-Level Language Level The level with which we interact when we write programs in languages such as C, Pascal, Lisp, and Java These languages must be translated to a language the machine can understand. (using compiler / interpreter) Compiled languages are translated into assembly language and then assembled into machine code. (They are translated to the next lower level.) The user at this level sees very little of the lower levels 25

26 Level 4: Assembly Language Level Acts upon assembly language produced from Level 5, as well as instructions programmed directly at this level As previously mentioned, compiled higher-level languages are first translated to assembly, which is then directly translated to machine language. This is a one-to-one translation, meaning that one assembly language instruction is translated to exactly one machine language instruction. By having separate levels, we reduce the semantic gap between a high-level language and the actual machine language UNIT-1 Computer 26 Organization

27 Level 3: System Software Level deals with operating system instructions. This level is responsible for multiprogramming, protecting memory, synchronizing processes, and various other important functions. Often, instructions translated from assembly language to machine language are passed through this level unmodified 27

28 Level 2: Machine Level Consists of instructions (ISA)that are particular to the architecture of the machine Programs written in machine language need no compilers, interpreters, or assemblers Level 1: Control Level A control unit decodes and executes instructions and moves data through the system. Control units can be microprogrammed or hardwired A microprogram is a program written in a low-level language that is implemented by the hardware. Hardwired control units consist of hardware that directly executes machine instruction 28

29 Level 0: Digital Logic Level This level is where we find digital circuits (the chips) Digital circuits consist of gates and wires. These components implement the mathematical logic of all other levels 29

30 High Level Language Program Levels of Representation Compiler temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; Assembly Language Program Assembler Machine Language Program lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) Machine Interpretation Control Signal Specification ALUOP[0:3] <= InstReg[9:11] & MASK 30

31 Computer Components: Top Level View 31

32 Instruction Cycle Two steps: Fetch Execute 32

33 Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC Unless told otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions 33

34 Processor-memory Execute Cycle data transfer between CPU and main memory Processor I/O Data transfer between CPU and I/O module Data processing Some arithmetic or logical operation on data Control Alteration of sequence of operations e.g. jump 34 Combination of UNIT-1 above Computer Organization

35 Instruction Cycle State Diagram 35

36 Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program e.g. overflow, division by zero Timer I/O Generated by internal processor timer Used in pre-emptive multi-tasking from I/O controller Hardware failure 36

37 Program Flow Control 37

38 Interrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program 38

39 Transfer of Control via Interrupts 39

40 Instruction Cycle with Interrupts 40

41 Instruction Cycle (with Interrupts) - State Diagram 41

42 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Result Store Deposit results in storage for later use Next Instruction Determine successor instruction 42

43 The Role of Performance 43

44 Example of Performance Measure 44

45 Performance Assessment Clock Speed Key parameters Performance, cost, size, security, reliability, power consumption System clock speed In Hz or multiples of Clock rate, clock cycle, clock tick, cycle time Signals in CPU take time to settle down to 1 or 0 Signals may change at different speeds Operations need to be synchronised Instruction execution in discrete steps Fetch, decode, load and store, arithmetic or logical Usually require multiple clock cycles per instruction Pipelining gives simultaneous execution of instructions So, clock speed is not the whole story 45

46 System Clock 46

47 Instruction Execution Rate Millions of instructions per second (MIPS) Millions of floating point instructions per second (MFLOPS) Heavily dependent on instruction set, compiler design, processor implementation, cache & memory hierarchy 47

48 Benchmarks Programs designed to test performance Written in high level language Portable Represents style of task Systems, numerical, commercial Easily measured Widely distributed E.g. System Performance Evaluation Corporation (SPEC) CPU2006 for computation bound 17 floating point programs in C, C++, Fortran 12 integer programs in C, C++ 3 million lines of code Speed and rate metrics Single task and throughput 48

49 Response Time Performance Metrics Delay between start end end time of a task Throughput Numbers of tasks per given time New: Power/Energy Energy per task, power 49

50 Computer Performance Measures Program Execution Time For a specific program compiled to run on a specific machine A, the following parameters are provided: The total instruction count of the program. The average number of cycles per instruction (average CPI). Clock cycle of machine A How can one measure the performance of this machine running this program? The machine is said to be faster or has better performance running this program if the total execution time is shorter. Thus the inverse of the total measured program execution time is a possible performance measure or metric: Performance A = 1 / Execution Time A How to compare performance of different machines? What factors affect 50 performance? Dr. Lokesh Chouhan How NIT Hamirpur to improve performance?

51 Comparing Computer Performance Using Execution Time To compare the performance of two machines A, B running a given specific program Performance A = 1 / Execution Time A Performance B = 1 / Execution Time B Machine A is n times faster than machine B means: Example: For a given program: Performance A Speedup = n = = Performance B Execution time on machine A: Execution A = 1 second Execution time on machine B: Execution B = 10 seconds Performance A / Performance B = Execution Time B / Execution Time A = 10 / 1 = 10 The performance of machine A is 10 times the performance of machine B when running this program, or: Machine A is said to be 10 times faster than machine B when running this program. 51 Execution Time B Execution Time A

52 CPU Execution Time The CPU Equation A program is comprised of a number of instructions executed, I Measured in: instructions/program The average instruction takes a number of cycles per instruction (CPI) to be completed. Measured in: cycles/instruction, CPI CPU has a fixed clock cycle time C = 1/clock rate Measured in: seconds/cycle CPU execution time is the product of the above three parameters as follows: CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle T = I x CPI x C 52

53 Example A Program is running on a specific machine with the following parameters: Total executed instruction count: 10,000,000 instructions Average CPI for the program: 2.5 cycles/instruction. CPU clock rate: 200 MHz. What is the execution time for this program? CPU time = Instruction count x CPI x Clock cycle = 10,000,000 x 2.5 x 1 / clock rate = 10,000,000 x 2.5 x 5x10-9 =.125 seconds 53

54 Example From the previous example: A Program is running on a specific machine with the following parameters: Total executed instruction count, I: 10,000,000 instructions Average CPI for the program: 2.5 cycles/instruction. CPU clock rate: 200 MHz. Using the same program with these changes: A new compiler used: New instruction count 9,500,000 New CPI: 3.0 Faster CPU implementation: New clock rate = 300 MHZ What is the speedup with the changes? Speedup = Old Execution Time = I old x CPI old x Clock cycle old Speedup = (10,000,000 x 2.5 x 5x10-9 ) / (9,500,000 x 3 x 3.33x10-9 ) =.125 /.095 = 1.32 or 32 % faster after changes. New Execution Time I new x CPI new x Clock Cycle new 54

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56 Examples (Throughput/Performance) Replace the processor with a faster version? 3.8 GHz instead of 3.2 GHz Add an additional processor to a system? Core Duo instead of P4 56

57 Measuring Performance Wall-clock time or- Total Execution Time CPU Time User Time System Time Try using time command on UNIX system 57

58 Relating the Metrics Performance = 1/Execution Time CPU Execution Time = CPU clock cycles for program x Clock cycle time CPU clock cycles = Instructions for a program x Average clock cycles per Instruction 58

59 Amdahl s Law Pitfall: Expecting the improvement of one aspect of a machine to increase performance by an amount proportional to the size of improvement 59

60 Amhdahl s Law [contd ] A program runs in 100 seconds on a machine, with multiply operations responsible for 80 seconds of this time. How much do I have to improve the speed of multiplication if I want my program to run five times faster? Execution Time After improvement = (exec time affected by improvement/amount of improvement) + exec time unaffected exec time after improvement = (80 seconds / n) + ( seconds) We want performance to be 5 times faster => 20 seconds = 80/n seconds / n + 20 seconds 0 = 80 / n!!!! 60

61 Amdahl s Law [contd ] Opportunity for improvement is affected by how much time the event consumes Make the common case fast Very high speedup requires making nearly every case fast Focus on overall performance, not one aspect 61

62 Instruction Sets: Addressing Modes and Formats

63 Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack 63

64 Immediate Addressing Operand is part of instruction Operand = address field e.g. ADD 5 Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Limited range 64

65 Immediate Addressing Diagram Instruction Opcode Operand 65

66 Direct Addressing Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Limited address space 66

67 Direct Addressing Diagram Opcode Instruction Address A Memory Operand 67

68 Indirect Addressing Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator 68

69 Indirect Addressing Large address space 2 n where n = word length May be nested, multilevel, cascaded e.g. EA = (((A))) Draw the diagram yourself Multiple memory accesses to find operand Hence slower 69

70 Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand 70

71 Register Addressing Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed Shorter instructions Faster instruction fetch 71

72 No memory access Very fast execution Register Addressing Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing N.B. C programming register int a; c.f. Direct addressing 72

73 Register Addressing Diagram Instruction Opcode Register Address R Registers Operand 73

74 Register Indirect Addressing C.f. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2 n ) One fewer memory access than indirect addressing 74

75 Register Indirect Addressing Diagram Opcode Instruction Register Address R Memory Registers Pointer to Operand Operand 75

76 Displacement Addressing EA = A + (R) Address field hold two values A = base value R = register that holds displacement or vice versa 76

77 Displacement Addressing Diagram Instruction Opcode Register R Address A Memory Registers Pointer to Operand + Operand 77

78 Relative Addressing A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage 78

79 Base-Register Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86 79

80 Indexed Addressing A = base R = displacement EA = A + R Good for accessing arrays EA = A + R R++ 80

81 Combinations Postindex EA = (A) + (R) Preindex EA = (A+(R)) (Draw the diagrams) 81

82 Stack Addressing Operand is (implicitly) on top of stack e.g. ADD Pop top two items from stack and add 82

83 Instruction Set Operations Arithmetic/Logical : Integer ALU ops. Load/Stores : Data transfer between memory and registers. Control : Instructions to change the program execution sequence. System : OS instructions, virtual memory management instructions. Floating Point : ADD, AND, SUB, OR. LOAD, STORE (Reg-reg), MOVE (Mem-mem) BEQZ, BNEQ, JMP, CALL, RETURN, TRAP INT FADD, FMULT Decimal : Support for BSD String : Special instruction optimized for handling ASCII character strings. Graphics : Pixel operations, compression and decompression. 83

84 Instruction Set Operations All machines generally provide a full set of operations for the first three categories. All machines MUST provide instruction support for basic system functions. Floating point instructions are optional but are commonly provided. Decimal and string instructions are optional but are disappearing in recent ISAs. They can be easily emulated by sequences of simpler instructions. Graphic instructions are optional. Remember MAKE THE COMMON CASE FAST? ALU and Load/Store instructions represent a significant portion of the instruction mix and therefore should execute quickly. 84

85 Instruction Set Operations: Control Flow instructions: Four types are identifiable: Conditional branches Jumps Procedure Calls Procedure Returns 85

86 Instruction Set Operations: Control Flow instructions: Program analysis shows that Conditional branches dominate (> 80% ). The destination address must always be specified. In most cases, it is given explicitly in the instruction. Exception: Procedure return addresses are not known at compile time. 86

87 RISC vs CISC 87

88 The debate between CISC & RISC has been going on for a long time and will likely continue. The difference between RISC and CISC can lays on many levels, lots of plausible arguments are put forward by both sides such as. Code density Transistor counts Memory bottlenecks Compiler Decode complexity etc. 88

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