Vacuum Reflow Process Characterization for Voidless Soldering Process in Semiconductor Package

Transcription

1 Vacuum Reflow Process Characterization for Voidless Soldering Process in Semiconductor Package Siang Miang Yeo, Azman Mahmood, Shahrul Haizal Ishak Amkor Technology Corporation Kuala Langat, Selangor Malaysia Abstract Semiconductor packaging s solder void criteria is getting tighter overtime due to involvement of high usage in automotive industry. Semiconductor packaging component maker starts to strengthen the solder joint quality and electrical power conductivity by tighten the solder void requirement through seeking a solution in controlling the maximum solder void size reduction from 10-15% original fraction to 5% or below over die size. Vacuum reflow is introduced to overcome this challenge. Critical process parameters in vacuum reflow process including temperature and pressure were characterized for void reduction and compared to that of conventional reflow process. Promising results show that high temperature, fast depressurize rate and long pressure dwell time in low pressurized environment as well as solder paste volume increment are critical factors in providing minimum solder void sizes that successfully meet the new industry criteria. Keywords Void-less Soldering, Vacuum Reflow, Solder void I. INTRODUCTION The global power discrete semiconductors market demand is rising exponentially because of the automotive industries growth in hybrid and electric vehicles. In response the automotive usage, industries start to strengthen the solder joint quality at interconnects for better mechanical reliability, heat dissipation and electrical power conductivity by tightening the solder void requirement on maximum solder void size, from the original 10-15% down to 5% or below. This helps to create a low and homogeneous thermal resistance of the solder joints for uniform heat dissipation through conduction of heat release from the power discrete s die towards base leadframe then printed circuit board (PCB). Large solder void always causes a displacement of electrical and thermal paths, with the result of heat generated surrounding the solder void and weaken the solder joint reliability performance, especially in power cycling test [1]. Therefore, industry is always seeking an effective solution such as flux-less soldering or reformulate solder paste material to achieve the criteria. Vacuum reflow technology has been a well-known solution for product with limited development time or as last resort when all other solutions fail to meet this new requirement. This reflow technology has evolved so as to not have considerable process differences in comparison to conventional reflow process with no changes of build of material (BOM) list. This is achieved by introducing an assisted vacuum process during a typical reflow process. By introducing a vacuum technology into the reflow process as shown in Figure 1. Conventional reflow Vacuum reflow Preheat Reflow Cooling Outgassing trapped after solder melted Vacuum assist trapped gas expands and escapes Solder void formed No solder void Fig. 1. Soldering Process Flow - comparison between conventional reflow and vacuum reflow. Figure1 shows the differences of void escape mechanism between conventional reflow and vacuum reflow. From conventional reflow process, flux vaporization happened and out gassing is generated during preheat process. Outgassing are trapped after solder melted during reflow process. Without additional energy, outgas shall have trapped forever and form as solder void after cooling process. For vacuum reflow process, the flux vaporization would be same due to same flux material characteristic. During reflow process, vacuum is assisted. Trapped gas expands due to delta pressure between pressure in solder void and low pressurize environment in side vacuum chamber. Solder voids successfully escapes from die and form void-less solder as result. To achieve the void-less soldering condition, a structural design of experiment (DOE) study is needed to identify the critical process parameter for this technology and study the interaction of the reflow temperature profile and vacuum depressurization profile. Besides, the vacuum reflow process toward different die size in same solder bond line thickness (BLT) was studied and discuss at here.

2 II. EXPERIMENTAL All the studies carried out used non-clean low residue solder paste with high melting temperature alloy which is 95% Lead and 5% Tin (Pb95Sn5). The test vehicle is small outline 8-leads (SO-8) packages with lead-frame and clip connector made of copper material and the die is attached in between by using the solder paste mentioned above, as shown in Figure 2. In the first part of study, the vacuum reflows critical to function (CTF) process parameters for achieving ultra-low solder void performance are identified. The second part of the study is validating the developed vacuum reflow process across different die sizes and explore other alternative solutions besides vacuum reflow parameter to improve solder void size reduction. Fig. 3. Process Characterization factors in vacuum reflow Fig. 2. Schematic drawing of SO-8 internal structure 2.1 Vaccum Reflow Process Characterization Study The evaluation was done using medium size of MOSFET die which is mm 2, to identify vacuum reflow CTF parameters and process target for ultra-low solder void achievement. The process characterization study focuses into 4 areas preheat/soaking temperature, reflow temperature (solder liquidous), vacuum pressure depressurizes rate and vacuumed dwell time at minimum pressure of 10torrs which is summarized in the figure 3, whereby a total of 30 sample sizes were collected for each DOE. For preheat temperature profile study, there are 5 types of preheat/soaking temperature profiles generated which are low soaking temperature, medium soaking temperature, high soaking temperature, normal linear ramp and fast linear ramp. To reveal the potential significant influence of preheat temperature towards solder void performance, a short-vacuumed dwell time was used. Figure 4 illustrates the preheat temperature behavior for each preheat profile. In addition, a control reference study with similar preheat profiles but no vacuum-assisted condition was conducted, in order to identify any significant variation of the solder void performance in vacuum-assisted reflow process from the original solder void performance without vacuum-assisted process. Fig. 4. Preheat temperature study with different temperature profiles. On the other hand, three different reflow temperature levels: high, medium and low was studied, with the profile as shown in Figure 5. This is the second part of the temperature profile study which is to understand the correlation of liquid solder temperature during vacuum reflow process, which preheat temperature does not have. Fig. 5. Three level reflow temperature profile study

3 TABLE I. PRESSURE PROFILE STUDY. III. RESULTS AND DISCUSSION Leg Pressure Profile Shape (Pressure vs time) Pump down rate Dwell time at lowest depressurized condition 3.1 Vaccum Reflow Process Characterization Study Temperature Preheat Profile study Control Slow Short 2 Slow Medium 3 Slow Long 4 Medium Short 5 Fast Short Subsequently for the pressure profile study, vacuum pump down rate and vacuumed dwell time at the lowest de-pressurized condition were studied. For vacuum pump down rate study, slow, medium and fast were used with short dwell time at minimum pressure condition which table I leg 1, 4 and 5 illustrated. Then, for vacuum dwell time study at 10torrs pressure condition, short, medium and long dwell time were chosen with slow pump down rate which table I leg 1, 2 and 3 illustrated. Table I summarizes the overall pressure profile study which include pump down rate study and dwell time study as well as without vacuum for comparison purposes. 2.2 Process Validation and other process solution study This evaluation used 3 different die sizes of mm 2, mm 2 and mm 2 in SO-8 products. The first part of the study aims to validate the solder void performance across 3 different die sizes by using defined process recipe. A total of 560 sample were collected. The second part of the study evaluate the other process factors besides vacuum reflow for further solder void improvement, in order to enable same vacuum reflow profile be used across all die sizes. Subsequently, solder paste deposition volume was assessed for further solder void improvement. Fig. 6. Single and total solder voids distribution box plot graph in different preheat temperature profile condition. Figure 6 shows the solders void result in single and total voids level for all the five preheat profiles. All the preheat profiles successfully achieved the strict solder void criteria which are single void size of less than 2.5% over die size and total void of less than 5% over die size, with the low soak profile shows the weakest performance. The result also demonstrates that temperature profile at preheat or soaking process has minimum influence on solder void reduction performance at vacuum reflow technology. Even though preheat temperature has minimal effect in vacuum reflow technology, it is still very important for normal reflow condition. Figure 7 illustrates the overall solder void performance in conventional process without vacuum assisted condition. All types of preheat profile had failed to meet the less than 2.5% single solder voids over die size criteria, and only normal soaking temperature profile achieve less than 5% over die size at total solder voids criteria in low sample size condition.

4 Fig. 7. Single and total solder voids distribution box plot graph in different preheat temperature profile without vacuumed condition. Fig. 8. Single and total solder voids distribution box plot graph in different reflow temperature profile condition Temperature Reflow Profile study In the temperature reflow profile study, a total of 3 levels of temperature reflow profiles were studied. Figure 8 shows all the DOE result of 3 different level temperature profile legs had passed the criteria of single solder void of less than 2.5% over die size and total solder void of less than 5.0% over die size. Comparing among the DOE legs in single solder void study, there is no significant differences obvious dependence on reflow temperature but the total solder void percentage over die size had improved with the average value for low, medium and high temperatures of 1.94%, 1.16% and 0.71% respectively. Thus, higher reflow temperature provides the most promising performance in total solder void percentage over die size. Figure 9 illustrates the proposed solder void escape mechanism under different reflow temperatures. With the increase of reflow profile temperature, the solder void expands into larger size because larger kinetic energy of gas molecule inside the solder void at higher temperature. This provides a shorter distance for solder void to reach out of the die edge and escape. With the help of vacuum-assisted process subsequently, solder void is found to have escaped easily with the shorter distance to the die edge. Fig. 9. Proposed solder void escape mechanism at different reflow temperatures.

5 3.1.3 Pressure Profile Study pump down rate has 33% longer total vacuum time than medium and fast pump down rate. Overall, high vacuum-assisted reflow temperature, fast depressurization rate and low pressurized environment with more than medium dwell depressurized time are critical to function (CTF) required to provide ultra-low solder void sample for vacuum reflow process. Preheat temperature has the effect for normal conventional reflow process only, but not for vacuum reflow process. Fig. 10. Single and total solder voids distribution box plot graph in different pressure dwell time. Figure 10 shows the result of dwell time study. Only conventional reflow method without vacuum-assisted reflow has failed to meet the strict criteria. The use of medium dwell time DOE leg2-t successfully reduced the overall solder void over die size distribution to below 0.5% with the maximum outliners 1.08% solder void size over die size. The long dwell time DOE leg3-t has succeeded to reduce the solder void outliners into 0.5% solder void size over die size. Consequently, the results show that dwell time at the lowest pressure condition is the most influencing factor for the overall solder void improvement at vacuum reflow technology. Figure 11 shows the solder void result in conventional reflow method without vacuum-assisted reflow process, as control with comparison to vacuum-assisted reflow process at slow, medium and fast vacuum pump down rate, followed by short dwell time in each case. From the single void performance observed, there is no significant differences among the vacuum-assisted processes (Figure11 leg1-s, leg4-s and leg5-s), but there is significant solder void variation when compared to the figure 11 control leg which is without vacuum assisted process. From total solder void performance result, higher pump down rates such as medium (leg4-t) and fast (leg5-t) provide better solder void performance as compared to slow (leg1-t), even-though slow Fig. 11. Solder void comparison between different pressure profile in two factors: dwell time and pump down rate. 3.2 Process Validation and other process solution study Three types of die sizes - large, medium and small are built with the center level of bond line thickness and tested with same vacuum reflow recipe that had been established in vacuum reflow process characterization studied in previous sections. Figure 12 shows the solder void performance in these three die sizes. Small and medium die sizes have passed the requirement of solder void size over die size based on 560 units data sample size. However, small die size has wider solder void distribution as compared to that of medium die size. Due to that the solder void size is calculated based on percentage of the die size, same solder void size may carry larger solder void percentage in smaller die as compared to that medium or large

6 die size. This has caused a high sensitivity of solder void count or measurement even in a tiny void size range for small die size. Therefore, larger solder void size is observed at small die size. On the other hand, the results also show that the largest die has failed to meet both the new solder void size percentage over die size criteria and requires further research work to explore alternative process conditions to achieve these criteria. (A) Die tilt when Solder void escape to the right side (B) Die back to flat after solder void escaped Fig. 13. Die tilting during and after solder void escape Fig. 12. Solder void comparison between different die size. Other possible approach to reduce the solder void is by increasing the solder paste volume during solder paste deposition process. Solder paste amount increment is correlated with the bond line thickness (BLT) increment. Solder voids may find it easier to escape from the molten solder in higher BLT during reflow process because of stronger buoyancy force of gas inside solder void and weaker adhesion force between die and leadframe when higher solder BLT introduced. Solder void tent to lift or tilt the die during the escape process of the void. This shall probably give a higher opportunity for solder void to escape easily. This concept may prove through a reflow simulator which a video shooting across the reflow soldering process. Figure 13(A) has clearly shows die tilting during void escaping and figure 14(B) shows solder void back to flat condition after solder void escaped from underneath die. Fig. 14. Single and total solder void comparison in between of different solder BLT.

7 Figure 14 shows the solder void size over die size is improved through the increase of solder BLT from center to thicker BLT. Hence, thick BLT on large die is proven to be able to meet the new strict criteria with maximum single solder void size 1.5% over die size and 3.5% size over die size in total solder void size over die size. Figure 15 shows the X-ray solder void image for 3 different die sizes. It shows minimum solder void size over die size from this 3 die sizes. Besides, it also shows that every single void size is similar size in each die size. Again, its carry primary factor of small die size has larger solder void percentage over die size that figure 12 explained before. IV. SUMMARY The study has shown the feasibility of vacuum reflow technology in meeting ultra-low solder void size over die size across the range of die size from (smallest) to (biggest) mm 2 at SO-8 product level. Vacuum reflow provides significant solder void size reduction in achieving less than 5% total solder void and less than 2.5% single solder void over die size. Process key parameters identified to minimize the solder void are high vacuumed reflow temperature, fast depressurize rate, long dwell time in lowest pressurized environment and thick bond line thickness (BLT), while preheat temperature has less significant effect. REFERENCES [1] D. C. Katsis and J. D. van Wyk, Void Induced Thermal Impedance in Power Semiconductor Modules: Some Transient Temperature Effects, 2003 [2] Raiyo F. Aspandiar, Void in solder joint, SMTA journal, vol.19 issue 4, 2006 [3] Richard Lathrop, Avoiding solder void, 2003 [4] Helmut Ottl, The Benefits of Soldering with Vacuum Profiles, [5] Rolf Diehm, Mathias Nowottnick, and Uwe Pape, A new approach to void-free reflow soldering, 2012 [6] Weicheng Lin, The Void-free Reflow Soldering of BGA with Vacuum, 2007 [7] Gunter Hagen, Klaus Wolter, and Armin Wagner, Vacuum Soldering in Electronic Packaging [8] Ning-Cheng Lee and Wanda B. Hance. Voiding mechanism in SMT, 1 Fig. 15. X-ray solder void image for 3 different die sizes (Large, Medium and Small)