ECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath

Transcription

1 ECE468 Computer Organization and Architecture Designing a Single Cycle Datapath ECE468 datapath1 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath Output Today s Topic: Datapath Design ECE468 datapath2

2 The Big Picture: The Performance Perspective Performance of a machine was determined by: Instruction count Clock cycle time Clock cycles per instruction Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction In the next two lectures: Single cycle processor: - Advantage: One clock cycle per instruction - Disadvantage: long cycle time ECE468 datapath3 The MIPS Instruction Formats All MIPS instructions are bits long The three instruction formats: 11 6 R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I-type 6 bits 5 bits 5 bits bits J-type op target address 6 bits bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction ECE468 datapath4

3 The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm LOAD and STORE lw rt, rs, imm sw rt, rs, imm BRANCH: beq rs, rt, imm op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 bits 5 bits 5 bits bits 11 6 JUMP: j target op target address 6 bits bits ECE468 datapath5 An Abstract View of the Implementation PC Operational element vs State element Instruction Address Ideal Instruction Rd 5 Instruction Rs 5 Rt 5 Imm Rw Ra Rb -bit Data Address Data In Ideal Data DataOut ECE468 datapath6

4 Clocking Methodology Setup Hold Don t Care Setup Hold All storage elements are clocked by the same clock edge Edge-trigged: all stored values are updated on a clock edge Cycle Time = Latch Prop + Longest Delay Path + Setup + Clock Skew (Latch Prop + Shortest Delay Path - Clock Skew) > Hold Time ECE468 datapath7 An Abstract View of the Critical Path Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: - Address valid => Output valid after access time PC Ideal Instruction Instruction Address Rd 5 Instruction Rs 5 Rt 5 Imm Critical Path (Load Operation) = PC s prop time + Instruction s Access Time + Register File s Access Time + to Perform a -bit Add + Data Access Time + Setup Time for Register File Write + Clock Skew Rw Ra Rb -bit Data Address Data In Ideal Data DataOut ECE468 datapath8

5 The Steps of Designing a Processor Instruction Set Architecture => Register Transfer Language Register Transfer Language => Datapath components Datapath interconnect Datapath components => Control signals Control signals => Control logic ECE468 datapath9 RTL: The ADD Instruction add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The ADD operation PC <- PC + 4 Calculate the next instruction s address ECE468 datapath1

6 RTL: The Load Instruction lw rt, rs, imm mem[pc] Fetch the instruction from memory Addr <- R[rs] + SignExt(imm) Calculate the memory address R[rt] <- Mem[Addr] Load the data into the register PC <- PC + 4 Calculate the next instruction s address ECE468 datapath11 Combinational Logic Elements Adder MUX A B A Select MUX CarryIn Adder Y B Sum Carry OP ECE468 datapath12 A B Result Zero

7 Storage Element: Register Register Similar to the D Flip Flop except - N-bit input and output - Write Enable input Write Enable: Write Enable Data In - : Data Out will not change - 1: Data Out will become Data In N Data Out N ECE468 datapath13 Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: RA selects the register to put on busa RB selects the register to put on busb RW selects the register to be written via busw when Write Enable is 1 RW RA RB Write Enable busw -bit busa busb Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - RA or RB valid => busa or busb valid after access time ECE468 datapath14

8 Storage Element: Idealized (idealized) One input bus: Data In One output bus: Data Out word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory memory word to be written via the Data In bus Clock input (CLK) Data In Write Enable The CLK input is a factor ONLY during write operation Address During read operation, behaves as a combinational logic block: - Address valid => Data Out valid after access time DataOut ECE468 datapath15 Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[pc] Update the program counter: - Sequential Code: PC <- PC Branch and Jump PC <- something else PC Next Address Logic Address Instruction Instruction Word ECE468 datapath

9 RTL: The ADD Instruction 11 6 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the next instruction s address ECE468 datapath17 RTL: The Subtract Instruction 11 6 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits sub rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] - R[rt] The actual operation PC <- PC + 4 Calculate the next instruction s address ECE468 datapath18

10 Datapath for Register-Register Operations R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt Ra, Rb, and Rw comes from instruction s rs, rt, and rd fields ctr and RegWr: control logic after decoding the instruction 11 6 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RegWr busw Rd Rs Rw Ra Rb -bit Rt busa busb ctr Result ECE468 datapath19 Register-Register Timing PC Rs, Rt, Rd, Op, Func ctr Old Value -to-q New Value Old Value Old Value Instruction Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value Delay busw Old Value New Value RegWr busw Rd Rs Rt Rw Ra Rb -bit busa busb ctr Result Register Write Occurs Here ECE468 datapath2

11 RTL: The OR Immediate Instruction 6 bits 5 bits 5 bits bits ori rt, rs, imm mem[pc] Fetch the instruction from memory R[rt] <- R[rs] or ZeroExt(imm) The OR operation PC <- PC + 4 Calculate the next instruction s address bits 15 immediate bits ECE468 datapath Datapath for Logical Operations with Immediate R[rt] <- R[rs] op ZeroExt[imm]] Example: ori rt, rs, imm 6 bits 5 bits 5 bits rd bits 11 ECE468 datapath22 Rd Rt RegDst Don t Care Rs RegWr (Rt) busw imm Rw Ra Rb -bit busb ZeroExt busa Src ctr Result

12 RTL: The Load Instruction lw rt, rs, imm 6 bits 5 bits 5 bits bits mem[pc] Fetch the instruction from memory Addr <- R[rs] + SignExt(imm) Calculate the memory address R[rt] <- Mem[Addr] Load the data into the register PC <- PC + 4 Calculate the next instruction s address 15 bits bits immediate bits immediate bits ECE468 datapath23 Datapath for Load Operations R[rt] <- Mem[R[rs] + SignExt[imm]] Example: lw rt, rs, imm 11 6 bits 5 bits 5 bits rd bits Rd Rt RegDst Don t Care Rs RegWr (Rt) busw imm Rw Ra Rb -bit busb Extender busa Src ctr Data In MemWr WrEn Adr Data MemtoReg ECE468 datapath24 ExtOp

13 RTL: The Store Instruction 6 bits 5 bits 5 bits bits sw rt, rs, imm mem[pc] Fetch the instruction from memory Addr <- R[rs] + SignExt(imm) Calculate the memory address Mem[Addr] <- R[rt] Store the register into memory PC <- PC + 4 Calculate the next instruction s address ECE468 datapath25 Datapath for Store Operations Mem[R[rs] + SignExt[imm] <- R[rt]] Example: sw rt, rs, imm 6 bits 5 bits 5 bits bits RegDst busw Rd Rt RegWr 5 5 imm Rs Rt 5 Rw Ra Rb -bit busb Extender busa Src ctr Data In MemWr WrEn Adr Data MemtoReg ECE468 datapath ExtOp

14 RTL: The Branch Instruction 6 bits 5 bits 5 bits bits beq rs, rt, imm mem[pc] Fetch the instruction from memory Cond <- R[rs] - R[rt] Calculate the branch condition if (COND eq ) Calculate the next instruction s address - PC <- PC ( SignExt(imm) x 4 ) else - PC <- PC + 4 ECE468 datapath27 Datapath for Branch Operations beq rs, rt, imm We need to compare Rs and Rt! 6 bits 5 bits 5 bits bits Rd Rt RegDst Rs Rt RegWr busw imm Rw Ra Rb -bit busb Extender busa Src ctr imm Branch Zero PC Next Address Logic To Instruction ECE468 datapath28 ExtOp

15 Binary Arithmetics for the Next Address In theory, the PC is a -bit byte address into the instruction memory: Sequential operation: PC<:> = PC<:> + 4 Branch operation: PC<:> = PC<:> SignExt[Imm] * 4 The magic number 4 always comes up because: The -bit PC is a byte address And all our instructions are 4 bytes ( bits) long In other words: The 2 LSBs of the -bit PC are always zeros There is no reason to have hardware to keep the 2 LSBs In practice, we can simplify the hardware by using a 3-bit PC<:2>: Sequential operation: PC<:2> = PC<:2> + 1 Branch operation: PC<:2> = PC<:2> SignExt[Imm] In either case: Instruction Address = PC<:2> concat ECE468 datapath29 Next Address Logic: Expensive and Fast Solution Using a 3-bit PC: Sequential operation: PC<:2> = PC<:2> + 1 Branch operation: PC<:2> = PC<:2> SignExt[Imm] In either case: Instruction Address = PC<:2> concat PC 3 1 imm Instruction<15:> SignExt Adder Adder 3 1 Addr<:2> Addr<1:> Instruction Instruction<:> Branch Zero ECE468 datapath3

16 Next Address Logic: Cheap and Slow Solution Why is this slow? Cannot start the address add until Zero (output of ) is valid Does it matter that this is slow in the overall scheme of things? Probably not here Critical path is the load operation 3 PC imm Instruction<15:> 3 SignExt Carry In Adder 3 Addr<:2> Addr<1:> Instruction Instruction<:> Branch Zero ECE468 datapath RTL: The Jump Instruction op target address 6 bits bits j target mem[pc] Fetch the instruction from memory PC<:2> <- PC<:28> concat target<25:> Calculate the next instruction s address ECE468 datapath

17 Instruction Fetch Unit j target PC<:2> <- PC<:28> concat target<25:> PC<:28> Target Instruction<25:> Addr<:2> Addr<1:> Instruction PC 3 1 imm Instruction<15:> Adder SignExt 3 Adder Jump Instruction<:> Branch Zero ECE468 datapath33 Putting it All Together: A Single Cycle Datapath We have everything except control signals (underline) RegDst busw 1 Rs Rt RegWr Rd imm Rt Rw Ra Rb -bit busb Extender Branch Jump busa 1 Src Instruction Fetch Unit ctr Data In Zero Instruction<:> Rt <:25> WrEn Rs <:2> MemWr Adr Data Rd <11:15> <:15> Imm 1 MemtoReg ECE468 datapath34 ExtOp

18 Where to get more information? To be continued ECE468 datapath35