Lecture 6 Datapath and Controller

Transcription

1 Lecture 6 Datapath and Controller Peng Liu liupeng@zju.edu.cn

2 Windows Editor and Word Processing UltraEdit, EditPlus Gvim Linux or Mac IOS Emacs vi or vim Word Processing(Windows, Linux, and Mac IOS) LaTex (English) Office (Chinese) 2

3 Review: Critical Timing Issues Flops work great as long as input is stable when clock rises Called setup and hold windows Clock skew can cause some nasty problems Hold time violations Cycle Time = longest Prop Delay + Setup + Clock Skew 3

4 Review: How to Execute Instructions First we need to: Fetch the instruction Then we need to: Decode instruction/fetch register Then we need to: Do the operation Then we need to: Write the result into register file Finally we need to: Calculate the next instruction address 4

5 Review: Memories In Our Design They will be combinational Otherwise we can t complete an instruction in one cycle! Interface is simple: Inputs: Address DataIn WriteEn (WriteEn must be a pulse) Outputs: Dataout Register file: It has three address, two for reads, and one for write It is called a 3-port, since it can perform 3 accesses per cycle Data Memory Addr Din Dout WE 5

6 The First Task: Fetching The Instruction (IF) Not that complex Instr = Mem[PC] Fetch the instruction from memory Update program counter for next cycle What is the address of the next instruction? 6

7 Instruction Fetch 7

8 What Did We Fetch? 8

9 Nice Characteristics of MIPS Machine Code Instructions are fixed length Don t need to decode first instruction to find next one Always add 4 bytes to instruction pointer (PC) Register specifiers are always in the same place Destination moves around some, but Source register are always in the same place Or you don t need that register Can fetch the registers BEFORE you decode instruction Feed bits directly from the instruction memory 9

10 Register to Register Operations In our subset this is only addu and subu I do not want to worry about overflow addu rd, rs, rt subu rd, rs, rt Operation R[rd] <- R[rs] + R[rt]; Add operation R[rd] <- R[rs] - R[rt]; Sub operation

11 Datapath: R-Format Instructions Read two register operands Perform arithmetic/logical operation Write register result

12 OR Immediate RTL OR Immediate instruction ori rt, rs, imm R[rt] <- R[rs] OR ZeroExt(imm); Means I need to get instr[5:] into the datapath, on RT path 2

13 Datapath: Immediate Ops Extend datapath to support immediate operations Write register is rt or rd based on instruction Read data 2 is ignored for immediates Immediates can be sign or zero extended src and operation set based on instruction 3

14 Load Load instruction lw rt, rs, imm Addr <- R[rs] + SignExt(imm); Compute memory address R[rt] <- Mem[Addr]; Load data into register Notice this will use the immediate path as well 4

15 Datapath: Load Extend datapath to support other immediate operations Extender handlers either sign or zero extension MUX selects between result and Memory output 5

16 Store Store instruction sw rt, rs, imm Addr <-R[rs] + SignExt(imm); Compute memory addr Mem[Addr] <- R[rt]; Load data into register Bits OP rs rt imm First Source Register Second Source Register Immediate 6

17 Datapath: Store Read Register 2 is passed on to Memory Memory address calculated just as in lw case 7

18 Branch Branch instruction beq rs, rt, imm Cond <- R[rs] R[rt]; Calculate branch condition If (cond eq ) Test if equal PC <- PC SignExt(imm)*4 else PC <-PC + 4; Calculate next address Bits OP rs rt imm First Source Second Source Immediate 8

19 The Next Address PC is byte-addressed into instruction memory Sequential PC [3:] = PC[3:] + 4 Branch operation PC[3:] = PC[3:] SignExt(imm)x4 Instruction Addresses PC is byte addressed, but instructions are 4 bytes long Simplify hardware by using 3-bit PC Sequential PC [3:2] = PC[3:2] + Branch operation PC[3:2] = PC[3:2] + + SignExt(imm) 9

20 Datapath: IF + Branch 2

21 Jump RTL Jump instruction j target PC[3:2]<- PC[3:29] target[25:]; Bits 6 26 OP target Jump Target Address 2

22 Datapath: IFU + Jump MUX selects pseudodirect jump target 22

23 Putting it All Together 23

24 The MIPS ISA Processor State -bit GPRs, R always contains a single precision FPRs, may also be viewed as 6 double precision FPRs FP status register, used for FP compares & exceptions PC, the program counter some other special registers Data types 8-bit byte, 6-bit half word -bit word for integers -bit word for single precision floating point 64-bit word for double precision floating point Load/Store style instruction set data addressing modes- immediate & indexed branch addressing modes- PC relative & register indirect Byte addressable memory- big endian mode All instructions are bits 24

25 Instruction Execution Execution of an instruction involves. instruction fetch 2. decode and register fetch 3. operation 4. memory operation (optional) 5. write back and the computation of the address of the next instruction 25

26 Datapath: Reg-Reg Instructions x4 Add RegWrite clk PC clk addr inst Inst. Memory inst<25:2> inst<2:6> inst<5:> we rs rs2 rd ws wd rd2 GPRs z inst<5:> Control OpCode RegWrite Timing? rs rt rd func rd (rs) func (rt)

27 Datapath: Reg-Imm Instructions x4 Add RegWrite clk PC clk addr inst Inst. Memory inst<25:2> inst<2:6> inst<5:> inst<3:26> we rs rs2 rd ws wd rd2 GPRs Imm Ext Control z OpCode ExtSel opcode rs rt immediate rt (rs) op immediate

28 Conflicts in Merging Datapath PC clk x4 Add addr inst Inst. Memory inst<25:2> inst<2:6> inst<5:> inst<5:> inst<3:26> inst<5:> RegWrite clk we rs rs2 rd ws wd rd2 GPRs Imm Ext Control z Introduce muxes OpCode ExtSel rs rt rd func rd (rs) func (rt) opcode rs rt immediate rt (rs) op immediate 28

29 Datapath for Instructions x4 Add RegWrite clk PC clk addr inst Inst. Memory <25:2> <2:6> <5:> <5:> we rs rs2 rd ws wd rd2 GPRs Imm Ext z <3:26>, <5:> Control OpCode RegDst rt / rd ExtSel OpSel BSrc Reg / Imm rs rt rd func rd (rs) func (rt) opcode rs rt immediate rt (rs) op immediate 29

30 Datapath for Memory Instructions Should program and data memory be separate? Harvard style: separate (Aiken and Mark influence) - read-only program memory - read/write data memory - Note: Somehow there must be a way to load the program memory Princeton style: the same (von Neumann s influence) - single read/write memory for program and data - Note: A Load or Store instruction requires accessing the memory more than once during its execution 3

31 Load/Store Instructions:Harvard Datapath PC clk x4 Add addr inst Inst. Memory base disp RegWrite clk we rs rs2 rd ws wd rd2 GPRs Imm Ext Control z MemWrite clk we addr rdata Data Memory wdata WBSrc / Mem OpCode RegDst ExtSel OpSel addressing mode opcode rs rt displacement (rs) + displacement BSrc rs is the base register rt is the destination of a Load or the source for a Store 3

32 MIPS Control Instructions Conditional (on GPR) PC-relative branch opcode rs offset BEQZ, BNEZ Unconditional register-indirect jumps opcode rs JR, JALR Unconditional absolute jumps 6 26 opcode target J, JAL PC-relative branches add offset 4 to PC+4 to calculate the target address (offset is in words): ±28 KB range Absolute jumps append target 4 to PC<3:28> to calculate the target address: 256 MB range jump-&-link stores PC+4 into the link register (R3) All Control Transfers are delayed by instruction we will worry about the branch delay slot later

33 Conditional Branches (BEQZ, BNEZ) PCSrc br RegWrite MemWrite WBSrc pc+4 x4 Add Add clk PC clk addr inst Inst. Memory we rs rs2 rd ws wd rd2 GPRs Imm Ext Control z clk we addr rdata Data Memory wdata OpCode RegDst ExtSel OpSel BSrc zero? 33

34 Register-Indirect Jumps (JR) PCSrc br rind RegWrite MemWrite WBSrc pc+4 x4 Add Add clk PC clk addr inst Inst. Memory we rs rs2 rd ws wd rd2 GPRs Imm Ext Control z clk we addr rdata Data Memory wdata OpCode RegDst ExtSel OpSel BSrc zero? 34

35 Register-Indirect Jump-&-Link (JALR) PCSrc br rind RegWrite MemWrite WBSrc pc+4 x4 Add Add clk PC clk addr inst Inst. Memory 3 we rs rs2 rd ws wd rd2 GPRs Imm Ext Control z clk we addr rdata Data Memory wdata OpCode RegDst ExtSel OpSel BSrc zero? 35

36 36 Absolute Jumps (J, JAL) x4 RegWrite Add Add clk WBSrc MemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSel OpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd GPRs rs rs2 ws wd rd2 we Imm Ext Control 3 PCSrc br pc+4 rind jabs

37 37 Harvard-Style Datapath for MIPS x4 RegWrite Add Add clk WBSrc MemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSel OpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd GPRs rs rs2 ws wd rd2 we Imm Ext Control 3 PCSrc br rind jabs pc+4

38 Putting it All Together: Cycle Datapath Inst Memory Adr Rs <2:25> <:5> <:5> <6:2> Rt Rd Imm6 Instruction<3:> PCSrc RegDst Rd Rt Zero ctr MemWr MemtoReg imm6 4 PC Ext Adder Adder Mux PC Clk RegWr busw Clk imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Mux WrEn Adr Data In Data Memory Clk Mux ExtOp Src 38

39 Controller Since every instruction takes one cycle, control is state free! It is just decoded instruction bits There are also few control points Control the multiplexers Operation type for the Write control on the Instruction & data memories First part of cycle does not have any control Which is good, since we don t have instruction yet Look at setting of the control points for different instructions 39

40 At Beginning of Clock Cycle 4

41 Control for Arithmetic 4

42 Instruction Fetch at End 42

43 Arithmetic Immediate (ori) 43

44 Control for Load 44

45 Control for Store 45

46 Control for Branch (beq) 46

47 Control for Jump (j) 47

48 Given Datapath: RTL -> Control Instruction<3:> Inst Memory Adr Op <2:25> Fun Rt <2:25> <:5> <:5> <6:2> Rs Rd Imm6 Control PCSrc RegWr RegDst ExtOp Src ctr MemWr MemtoReg Zero DATA PATH 49

49 The Single Cycle Datapath during Or Immediate R[rt] <= R[rs] or ZeroExt[Imm6] RegDst <= RegWr <= 5 5 busw Clk 3 Rd Mux imm6 Rt Rs 5 Rw Ra Rb -bit Registers 6 26 Rt busb Extender 2 op rs rt immediate PCSrc <= +4 Clk busa ctr <= Or Mux 6 Data In Src <= Instruction Fetch Unit Clk Zero Instruction<3:> Rt <2:25> WrEn Rs <6:2> MemWr <= Adr Data Memory Rd <:5> <:5> Imm6 MemtoReg <= Mux ExtOp <= 5

50 The Concept of Local Decoding op 6 Main Control func 6 op N Control (Local) ctr 3 55

51 The Encoding of op op 6 Main Control func 6 op N Control (Local) ctr 3 In this exercise, op has to be 2 bits wide to represent: () R-type instructions I-type instructions that require the to perform: (2) Or, (3) Add, and (4) Subtract To implement the more of MIPS ISA, op has to be 3 bits to represent (4 bits in book to include NOR): () R-type instructions I-type instructions that require the to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) R-type ori lw sw beq jump op (Symbolic) R-type Or Add Add Subtract xxx op<2:> xxx 56

52 The Decoding of the func Field op 6 Main Control func 6 op N Control (Local) ctr 3 R-type ori lw sw beq jump op (Symbolic) R-type Or Add Add Subtract xxx op<2:> xxx R-type op rs rt rd shamt funct funct<5:> Instruction Operation add subtract and or set-on-less-than ctr ctr<2:> Operation And Or Add Subtract Set-on-less-than 57

53 Drawback of This Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Instruction Memory Access Time + Register File Access Time + Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions 58

54 Addr Instr Mem Data What is Single Cycle Control? Equal Combinational Logic (Only Gates, No Flip Flops) Just specify logic functions! rs,rt,rd,imm RegDest RegWr ExtOp src MemWr MemToReg PCSrc RegDest RegFile 5 rs 5 rs2 rd 5 ws rd2 wd WE Ext ctr Equal RegWr ExtOp src MemWr MemToReg 59

55 Two Goals When Specifying Control Logic Bug-free: One that should be a in the control logic function breaks contract with the programmer. Should be easy for humans to read and understand: sensible signal names, symbolic constants... Efficient: Logic function specification should map to hardware with good performance properties: fast, small, low power, etc. 6

56 Advantages Single Cycle Processor Single cycle per instruction makes logic and clock simple Disadvantages Inefficient utilization of memory and functional units since different instructions take different lengths of time only computes values a small amount of the time Cycle time is the worst case path -> long cycle times Load instruction Best possible CPI is 6

57 Single Cycle Processor Performance Functional unit delay Memory: 2ps and adders: 2ps Register file: ps CPU clock cycle = 8 ps =.8ns(.25GHz) 62

58 Variable Clock Single Cycle Processor Performance Instruction Mix 45% 25%loads %stores 5%branches 5%jumps CPU clock cycle =.6x45%+.8x25% +.7x% +.5x5% +.2x5%=.625 ns(.6ghz) 63

59 Increasing Parallelism Problem: Each functional unit used once per cycle Most of the time it is sitting waiting for its turn Well it is calculating all the time, but it is waiting for valid data There is no parallelism in this arrangement Making instructions take more cycles makes machine faster! Each instruction takes roughly the same time While the CPI is much worse, the clock freq is much higher Overlap execution of multiple instructions at the same time Different instructions will be active at the same time This is called Pipelining Increases the parallelism going on in the machine We will look at a 5 stage pipeline Modern machines have order 5 cycles/instruction 64

60 The Five Stages of Load Instruction Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 lw IFetch Dec Exec Mem WB IFetch: Instruction Fetch and Update PC Dec: Registers Fetch and Instruction Decode Exec: Execute R-type; calculate memory address Mem: Read/write the data from/to the Data Memory WB: Write the result data into the register file 65

61 Pipelined MIPS Processor Start the next instruction while still working on the current one improves throughput or bandwidth - total amount of work done in a given time (average instructions per second or per clock) instruction latency is not reduced (time from the start of an instruction to its completion) Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB pipeline clock cycle (pipeline stage time) is limited by the slowest stage for some instructions, some stages are wasted cycles 66

62 Single Cycle, Multiple Cycle, vs. Pipeline Single Cycle Implementation: Clk Cycle Cycle 2 Load Store Waste Multiple Cycle Implementation: Clk Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch Pipeline Implementation: lw IFetch Dec Exec Mem WB wasted cycles sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB 67

63 Multiple Cycle v. Pipeline, Bandwidth v. Latency Multiple Cycle Implementation: Clk Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch Pipeline Implementation: lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB Latency per lw = 5 clock cycles for both Bandwidth of lw is per clock clock (IPC) for pipeline vs. /5 IPC for multicycle Pipelining improves instruction bandwidth, not instruction latency 68

64 Pipelining the MIPS ISA What makes it easy all instructions are the same length ( bits) easier to fetch in st stage and decode in 2 nd stage few instruction formats (three) with symmetry across formats can begin reading register file in 2 nd stage memory operations can occur only in loads and stores can use the execute stage to calculate memory addresses each MIPS instruction writes at most one result and does so near the end of the pipeline What makes it hard structural hazards: what if we had only one memory? control hazards: what about branches? data hazards: what if an instruction s input operands depend on the output of a previous instruction? 69

65 MIPS Pipeline Datapath Modifications What do we need to add/modify in our MIPS datapath? registers between pipeline stages to isolate them IF:IFetch ID:Dec EX:Execute MEM: MemAccess WB: WriteBack Add PC 4 Instruction Memory Read Address IFetch/Dec Read Addr Register Read Read Addr 2 Data File Write Addr Write Data Read Data 2 Dec/Exec Shift left 2 Add Exec/Mem Address Write Data Data Memory Read Data Mem/WB Sign 6 Extend System Clock 7

66 Graphically Representing MIPS Pipeline IM Reg DM Reg Can help with answering questions like: how many cycles does it take to execute this code? what is the doing during cycle 4? is there a hazard, why does it occur, and how can it be fixed? 7

67 Why Pipeline? For Throughput! Time (clock cycles) I n s t r. Inst Inst IM Reg DM Reg IM Reg DM Reg Once the pipeline is full, one instruction is completed every cycle O r d e r Inst 2 Inst 3 IM Reg DM Reg IM Reg DM Reg Inst 4 Time to fill the pipeline IM Reg DM Reg 72

68 Acknowledgements These slides contain material from courses: UCB CS52 Stanford EE8B 73

69 ExtOp: src: ctr: Meaning of the Control Signals zero, sign regb; immed add, sub, or RegDst RegWr busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Zero MemWr: write memory MemtoReg: ; Mem RegDst: RegWr: Mux ctr WrEn Adr Data In Data Memory Clk rt ; rd write register MemWr MemtoReg Mux ExtOp Src 74

70 Two Equivalent Ways to Specify Control Control line Control line Control line n AddU A B SubU ORI LW SW BEQ X Y (Rotate about 45degree axis) Control line Control line Control line n AddU SubU ORI LW SW BEQ A B X Y 75

71 Setting PC Source Control Signal PCSrc: PC <= PC + 4 PC <= PC {SignExt(Im6), 2b} Later in lecture: higher-level connection between mux and branch cond imm6 4 PC Ext Adder Adder PCSrc PC Mux Clk Adr Inst Memory Answer? AddU SubU ORI LW SW BEQ X 8 X X X X X 9 None of the above 76

72 ExtOp: src: ctr: Meaning of the Control Signals zero ; sign regb; immed add, sub, or RegDst RegWr busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Zero MemWr: write memory MemtoReg: ; Mem RegDst: RegWr: Mux ctr WrEn Adr Data In Data Memory Clk rt ; rd write register MemWr MemtoReg Mux ExtOp Src 78

73 Specify Source mux Control src: reg as B input; immediate as B input busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Mux Data In An sw e r? Ad d U S ubu OR I L W S W B E Q X 6 7 X 8 X X X X X 9 No n e of t h e ab o v e ExtOp Src 79

74 Specify Source mux Control src: reg as B input; immediate as B input busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Mux Data In An sw e r? Ad d U S ubu OR I L W S W B E Q X 6 7 X 8 X X X X X 9 No n e of t h e ab o v e ExtOp Src 8

75 Specify Immediate Extender Op Control ExtOp: zero extend immediate ; sign extend imm. busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Mux Data In Answer? AddU SubU ORI LW SW BEQ X 7 X X 8 X X 9 None of the above ExtOp Src 8

76 Specify Register Write Control RegWr: write register RegDst RegWr busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Mux Answer? AddU SubU ORI LW SW BEQ X X 9 None of the above ExtOp Src 83

77 Specify Register Write Control RegWr: write register RegDst RegWr busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Extender Mux Answer? AddU SubU ORI LW SW BEQ X X 9 None of the above ExtOp Src 84

78 RegDst RegWr busw Clk Specify Register Destination Control RegDst: imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt rt ; rd busa busb Extender ExtOp 3 3 op rs rt rd shamt funct op rs rt immediate Mux Src Answer? AddU SubU ORI LW SW BEQ X X 8 X 9 None of the above 6 85

79 MemWr: Specify the Memory Write Control Signal write memory RegDst Rd RegWr 5 5 Clk imm6 Rt Rw Ra Rb -bit Registers 6 Rs Rt 5 busa busw busb Extender Zero Mux ExtOp Src ctr MemWr Data In WrEn Adr Data Clk Memory MemtoReg Mux Answer? AddU SubU ORI LW SW BEQ X 8 X X X X 9 None of the above 87

80 Specify Memory To Register File Mux Control MemtoReg: ; Mem RegDst Rd RegWr 5 5 Clk imm6 Rt Rw Ra Rb -bit Registers 6 Rs Rt 5 busa busw busb Extender Zero Mux ExtOp Src ct r MemWr MemtoReg WrEn Adr Data In Data Memory Clk Mux Answer? AddU SubU ORI LW SW BEQ 2 3 X 4 X X X 8 X 9 None of the above 89

81 Specify Memory To Register File Mux Control MemtoReg: ; Mem RegDst Rd RegWr 5 5 Clk imm6 Rt Rw Ra Rb -bit Registers 6 Rs Rt 5 busa busw busb Extender ExtOp Zero Mux Src ctr MemWr Data In WrEn Adr Data Clk Memory MemtoReg Mux Answer? AddU SubU ORI LW SW BEQ 2 3 X 4 X X X 8 X 9 None of the above 9

82 Specify the Control Signals ctr: add, sub, 2 or RegDst Rd RegWr 5 5 Clk imm6 Rt Rw Ra Rb -bit Registers 6 Rs Rt 5 busa busw busb Extender ExtOp Zero Mux Src ctr MemWr Data In WrEn Adr Data Memory Clk MemtoReg Mux Answer? AddU SubU ORI LW SW BEQ X 5 2 X X 6 2 X X X 7 X 2 X X X 8 X X 2 9 None of the above 9

83 ctr: Specify the Control Signals add, sub, 2 or RegDst Rt Zero Rd RegWr Rs Rt busa Rw Ra Rb -bit Registers busb Clk busw imm6 6 Extender Mux ExtOp Src ctr MemWr Data In WrEn Adr Data Memory Clk MemtoReg Mux Answer? AddU SubU ORI LW SW BEQ X 5 2 X X 6 2 X X X 7 X 2 X X X 8 X X 2 9 None of the above 92

84 The Add Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <= R[rs] + R[rt] The actual operation PC <= PC + 4 Calculate the next instruction s address 93

85 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction <= mem[pc] This is the same for all instructions Inst Memory Adr Instruction<3:> PCSrc 4 imm6 PC Ext Adder Adder PC Mux Clk 94

86 Instruction Fetch Unit at the End of Branch op rs rt immediate if (Zero == ) PC = PC {SignExt[imm6], 2b} ; else PC = PC PCSrc Zero PCSrc Inst Memory Adr Instruction<3:> What is encoding of PCSrc? Direct MUX select? Branch / not branch Let s choose second option 4 imm6 Adder Adder Mux Clk PC PCSrc zero? MUX X 95

87 RegDst = The Single Cycle Datapath during Load RegWr <= 5 5 busw Clk 3 Rd Mux imm6 Rt Rs 5 Rw Ra Rb -bit Registers 6 26 R[rt] <= Data Memory [R[rs] + SignExt[imm6]] Rt busb Extender ExtOp <= 2 op rs rt immediate PCSrc<= +4 Clk busa Mux 6 ctr <= Add Src = Instruction Fetch Unit Data In Clk Zero Instruction<3:> Rt <2:25> WrEn Rs <6:2> MemWr = Adr Data Memory Rd <:5> Imm6 MemtoReg <= <:5> Mux 96

88 The Single Cycle Datapath during Store op rs rt immediate Data Memory [R[rs] + SignExt[imm6]] <= R[rt] RegDst <= busw Clk RegWr <= 3 Rd Mux imm6 Rt Rs 5 Rw Ra Rb -bit Registers 6 Rt 2 PCSrc <= busb Extender Clk busa ExtOp <= 6 ctr <= Mux Data In Src <= Instruction Fetch Unit Clk Zero Instruction<3:> Rt <2:25> WrEn Rs <6:2> MemWr <= Adr Data Memory Rd <:5> <:5> Imm6 MemtoReg <= Mux 97

89 The Single Cycle Datapath during Store RegDst <= x RegWr <= busw Clk 3 Rd Mux imm6 Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 26 Data Memory [R[rs] + SignExt[imm6]] <= R[rt] Rt busb Extender ExtOp <= 2 op rs rt immediate PCSrc<= +4 Clk busa Mux 6 Instruction Fetch Unit ctr <= Add Data In Src <= Clk Zero Instruction<3:> Rt <2:25> WrEn Rs <6:2> MemtoReg <= x MemWr <= Adr Data Memory Rd <:5> <:5> Imm6 Mux 98

90 RegDst <= x The Single Cycle Datapath during Branch RegWr <= busw Clk 3 Rd Mux imm6 Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 26 if (R[rs] - R[rt] == ) Zero <= ; else Zero <= Rt busb Extender 2 op rs rt immediate PCSrc<= Br Clk busa ctr <=Sub Mux 6 Data In Src <= Instruction Fetch Unit Clk Zero Instruction<3:> Rt <2:25> WrEn Rs <6:2> MemWr <= Adr Data Memory Rd <:5> <:5> Imm6 MemtoReg <= x Mux ExtOp <= x 99

91 Step 4: Given Datapath: RTL -> Control Instruction<3:> Inst Memory Adr Op <2:25> Fun Rt <2:25> <:5> <:5> <6:2> Rs Rd Imm6 Control PCSrc RegWr RegDst ExtOp Src ctr MemWr MemtoReg Zero DATA PATH

92 A Summary of Control Signals inst Register Transfer ADD R[rd] <= R[rs] + R[rt]; PC <= PC + 4 src = RegB, ctr = add, RegDst = rd, RegWr, PCSrc = +4 SUB R[rd] <= R[rs] R[rt]; PC <= PC + 4 src = RegB, ctr = sub, RegDst = rd, RegWr, PCSrc = +4 ORi R[rt] <= R[rs] + zero_ext(imm6); PC <= PC + 4 src = Im, Extop = Z, ctr = or, RegDst = rt, RegWr, PCSrc = +4 LOAD R[rt] <= MEM[ R[rs] + sign_ext(imm6)]; PC <= PC + 4 src = Im, Extop = Sn, ctr = add, MemtoReg, RegDst = rt, RegWr, PCSrc = +4 STORE MEM[ R[rs] + sign_ext(imm6)] <= R[rs]; PC <= PC + 4 src = Im, Extop = Sn, ctr = add, MemWr, PCSrc = +4 BEQ if ( R[rs] == R[rt] ) then PC <= PC +4 + {sign_ext(imm6)], b2} else PC <= PC + 4 PCSrc = Br, ctr = sub

93 A Summary of the Control Signals See func We Don t Care :-) Appendix A op RegDst Src MemtoReg RegWrite MemWrite PCSrc ExtOp ctr<2:> add sub ori lw sw beq jump x x x x x x x x Add x Subtract Or Add Add x Subtract x xxx R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump 2