ECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations
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1 ECE7 Computer Architecture Single Cycle Control Review: 3a: Overview of the Fetch Unit The common operations Fetch the : mem[] Update the program counter: Sequential Code: < + Branch and Jump: < something else Net Logic Word Review: 3b: Add & Subtract R[rd] < R[rs] op R[rt] Eample: addu rd, rs, rt Ra, Rb, and Rw come from instruction s rs, rt, and rd fields ctr and RegWr: control logic after decoding the instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RegWr -bit ctr Result Review: 3c: Logical Operations with Immediate Additions to prior path R[rt] < R[rs] op Et[imm6] ] bits 5 bits 5 bits rd? 6 bits immediate 6 bits 6 bits R-type and I-type different? field for destination RegWr ctr -bit Result Reg file or imm6 6 Immediate Src Et -etend immed. Review: 3d: Load Operations R[rt] < Mem[R[rs] + SignEt[imm6]] Eample: lw rt, rs, imm bits 5 bits 5 bits 6 bits? RegWr ctr -bit MemWr imm6 6 or sign etend EtOp In?? Src Chose output or output W_Src Separate memory for data Review: 3e: Store Operations Mem[ R[rs] + SignEt[imm6] ] < R[rt] Eample: sw rt, rs, imm bits 5 bits 5 bits 6 bits ctr MemWr W_Src RegWr -bit imm6 6 EtOp Src In Reg file bus B as input
2 beq mem[] 3f: The Branch bits 5 bits 5 bits 6 bits rs, rt, imm6 Equal < (R[rs] R[rt]) Fetch the instruction from memory Calculate the branch condition if (Equal) Calculate the net instruction s address < + + { SignEt(imm6), 2b } else < + path for Branch Operations beq rs, rt, imm6 path generates condition (equal) imm6 Et bits 5 bits 5 bits 6 bits Cond Src RegWr -bit Test if Reg file equals Reg file Chose + or ++{SignEtImm, } Equal? imm6 Putting it All Together: A Single Cycle path Et Src RegWr -bit imm6 <2:25> 6 <6:2> <:5> <:5> Imm6 Equal <3:> ctr MemWr MemtoReg In Src Step : Given path: What are Control Signals? <3:> <2:25> Op Fun <2:25> <6:2> <:5> Control <:5> Imm6 RegWr EtOp Src ctr MemWr MemtoReg DATA PATH EtOp Src Meaning of the Control Signals The Single Cycle path during Load EtOp: src: ctr: zero, sign MemWr: write memory regb; immed MemtoReg: ; Mem add, sub, or : rt ; rd RegWr: write register ctr MemWr MemtoReg RegWr -bit imm6 6 In R[rt] < [R[rs] + SignEt[imm6]] RegWr < imm6 -bit 6 Src< + ctr < Add Src Fetch Unit In <3:> <2:25> <6:2> MemWr <:5> <:5> Imm6 MemtoReg < EtOp Src EtOp <
3 The Single Cycle path during Store [R[rs] + SignEt[imm6]] < R[rt] < RegWr < imm6 -bit 6 EtOp < Src< + Fetch Unit ctr < Add In Src < <3:> <2:25> <6:2> <:5> MemtoReg < MemWr < <:5> Imm6 The Single Cycle path during Branch if (R[rs] - R[rt] ) < ; else < < RegWr < imm6 -bit 6 Src< Br EtOp < ctr <Sub Src < Fetch Unit In <3:> <2:25> <6:2> <:5> MemWr < <:5> Imm6 MemtoReg < Specify source mu Control Specify Immediate Op Control src: reg as B input; immediate as B input EtOp: zero etend immediate ; sign etend imm. -bit imm6 6 In X 6 7 X 8 X X X X X -bit imm6 6 In X 7 X X 8 X X EtOp Src EtOp Src Specify Register Write Control RegWr: write register RegWr -bit imm6 6 EtOp Src X X Specify Register Destination Control : rt ; rd op rs rt rd shamt funct RegWr Rw Ra Rb -bit 3 5 imm6 6 7 X X 6 8 X EtOp Src
4 Specify the Write Control Signal MemWr: write memory 5 a Rb it rs EtOp Src ctr MemWr MemtoReg In X 8 X X X X Specify To Register File Control MemtoReg: 5 a Rb it rs EtOp Src ctr ; Mem MemWr MemtoReg In 2 3 X X X X 8 X ctr: 5 a Rb it rs EtOp Specify the Control Signals Src add, sub, 2 or ctr MemWr MemtoReg In X 5 2 X X 6 2 X X X 7 X 2 X X X 8 X X 2 imm6 Setting Source Control Signal Src: < + < + + {SignEt(Im6), 2b} Et Src X 8 X X X X X Depends on the encoding of Src? Direct MUX select? Branch / not branch? Fetch Unit During Branch if ( ) + + {SignEt[imm6], 2b} ; else + Src imm6 MUX <3:> What is encoding of Src? Direct MUX select? Branch / not branch Let s choose second option Src zero? MUX X inst A Summary of Control Signals Register Transfer ADD R[rd] < R[rs] + R[rt]; < + src RegB, ctr add, rd, RegWr, Src + SUB R[rd] < R[rs] R[rt]; < + src RegB, ctr sub, rd, RegWr, Src + ORi R[rt] < R[rs] + zero_et(imm6); < + src Im, Etop Z, ctr or, rt, RegWr, Src + LOAD R[rt] < MEM[ R[rs] + sign_et(imm6)]; < + src Im, Etop Sn, ctr add, MemtoReg, rt, RegWr, Src + STORE MEM[ R[rs] + sign_et(imm6)] < R[rs]; < + src Im, Etop Sn, ctr add, MemWr, Src + BEQ if ( R[rs] R[rt] ) then < + + {sign_et(imm6)], b2} else < + Src Br, ctr sub
5 A Summary of the Control Signals Step : Given path: RTL -> Control See func We Don t Care :-) Green Card op Src MemtoReg RegWrite MemWrite Src EtOp ctr<2:> add sub ori lw sw beq jump Add Subtract Or Add Add Subtract Src <3:> <2:25> Op Fun <2:25> <6:2> <:5> Control <:5> Imm6 RegWr EtOp Src ctr MemWr MemtoReg R-type I-type op rs rt rd shamt funct add, sub ori, lw, sw, beq DATA PATH J-type op target address jump In Class Question Assumptions For the net few slides in this lecture assume that. Delay to Access Register File Delay to do -bit add Delay to do -bit operation 2. Multipleor delays (ignore for now) imm6 Et 2 What is critical path for BEQ?. A, B, C, D, I, K 2. A, B, C, D, G, I, K 3. A, B, C, D, E, F, G, I, J, K. A, B, C, D, E, F, G, H, I, J, K Wr -bit imm6 6 A. s -to-q B. s Access Time C. Register File s Access Time D. to Perform a -bit Operation E. adds to F. Et sign etends immediate G. 2 adds imm to sum H. Access Time I. Setup Time for J. Setup Time for Register File Write K. Clock Skew Equal In What is critical path for LW? Which has longest critical path? imm6. A, B, C, D, H, J, K 2. A, B, C, D, H, I, J, K 3. A, B, C, D, E, H, I, J, K. A, B, C, D, E, F, G, H, I, J, K Et 2 Wr -bit imm6 6 A. s -to-q B. s Access Time C. Register File s Access Time D. to Perform a -bit Operation E. adds to F. Et sign etends immediate G. 2 adds imm to sum H. Access Time I. Setup Time for J. Setup Time for Register File Write K. Clock Skew Equal In imm6. ADDU 2. BEQ 3. LW. ORI 5. SUBU 6. SW Et 2 A. s -to-q B. s Access Time C. Register File s Access Time D. to Perform a -bit Operation E. adds to F. Et sign etends immediate G. 2 adds imm to sum H. Access Time I. Setup Time for J. Setup Time for Register File Write K. Clock Skew Equal Wr imm6 -bit 6 In
6 An Abstract View of the Critical Path memory AND register file: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: valid > Output valid after access time. Net -bit Imm 6 A B Critical Path (Load Operation) s -to-q + s Access Time + Register File s Access Time + to Perform a -bit Add + Access Time + Setup Time for Register File Write + Clock Skew In Drawback of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: s Clock -to-q + Access Time + Register File Access Time + Delay (address calculation) + Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions An Abstract View of the Implementation Summary Net -bit A B Control Control Signals path Conditions In Out 5 steps to design a processor. Analyze instruction set > datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic MIPS makes it easier s same size; Source registers, immediates always in same place Operations always on registers/immediates Single cycle datapath > CPI, CCT > long
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