ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University
Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design: Practice 2
Fixed Shifters & Rotators ECE 448 FPGA and ASIC Design with VHDL 3
Fixed Logical Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 L A(3) A(2) A() A() A(3) A(2) A() A C 4
Fixed Logical Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 L A(3) A(2) A() A() A(3) A(2) A() A C C = '' & A(3 downto ); 5
Fixed Arithmetic Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() 6
Fixed Arithmetic Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() C = A(3) & A(3 downto ); 7
Fixed Logical Shift Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A << C 4 L A(3) A(2) A() A() A(2) A() A() A C 8
Fixed Logical Shift Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A << C 4 L A(3) A(2) A() A() A(2) A() A() C = A(2 downto ) & ''; A C 9
Fixed Rotation Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A <<< C 4 A(3) A(2) A() A() A(2) A() A() A(3) A C
Fixed Rotation Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A <<< C 4 A(3) A(2) A() A() A(2) A() A() A(3) C = A(2 downto ) & A(3); A C
Variable Rotators ECE 448 FPGA and ASIC Design with VHDL 2
8-bit Variable Rotator Left A 8 3 B A <<< B C 8 To be covered during one of the future classes 3
Multiplexers ECE 448 FPGA and ASIC Design with VHDL 4
2-to- Multiplexer s s f w f w w w (a) Graphical symbol (b) Truth table VHDL: 5
2-to- Multiplexer s s f w f w w w (a) Graphical symbol (b) Truth table VHDL: f <= w WHEN s = '' ELSE w ; or f <= w WHEN s = ' ELSE w ; 6
Cascade of two multiplexers w 3 w 2 y w VHDL: s2 s 7
Cascade of two multiplexers w 3 w 2 y w VHDL: s2 s f <= w WHEN s = ' ELSE w2 WHEN s2 = ELSE w3 ; 8
4-to- Multiplexer (a) Graphic symbol (b) Truth table s s s s s f w w w 2 w 3 f w w w 2 w 3 9
4-to- Multiplexer (a) Graphic symbol (b) Truth table s s s s s f w w w 2 w 3 f w w w 2 w 3 WITH s SELECT f <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; 2
Decoders ECE 448 FPGA and ASIC Design with VHDL 2
2-to-4 Decoder (b) Graphical symbol (a) Truth table w w y 3 En w w y y y y 3 2 w y 2 y En y y x x 22
2-to-4 Decoder (b) Graphical symbol (a) Truth table w w y 3 En w w y 3 y 2 y y w y 2 y En y y x x 23
2-to-4 Decoder (b) Graphical symbol (a) Truth table w w y 3 En w w y 3 y 2 y y w y 2 y En y y x x Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; 24
VHDL code for a 2-to-4 Decoder entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO ) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO ) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; END dataflow ; 25
Encoders ECE 448 FPGA and ASIC Design with VHDL 26
Priority Encoder w w w w 2 w 3 y y z y w 3 w 2 w w y y z - - - - - - 27
Priority Encoder w w w w 2 w 3 y y z y w 3 w 2 w w y y z - - - - - - d d 28
Priority Encoder w w w w 2 w 3 y y z y y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; w 3 w 2 w w y y z z <= '' WHEN w = "" ELSE '' ; - - - - - - d d 29
VHDL code for a Priority Encoder entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY priority IS PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; z : OUT STD_LOGIC ) ; END priority ; ARCHITECTURE dataflow OF priority IS BEGIN y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; z <= '' WHEN w = "" ELSE '' ; END dataflow ; 3
Adders ECE 448 FPGA and ASIC Design with VHDL 3
Adder mod 2 6 6 6 X Y S 6 32
VHDL code for an Adder mod 2 6 LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder6 IS PORT ( X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ) ; END adder6 ; ARCHITECTURE dataflow OF adder6 IS BEGIN S <= X + Y ; END dataflow ; 33
6-bit Unsigned Adder 6 6 Cout X + S Y Cin 6 34
Operations on Unsigned Numbers For operations on unsigned numbers USE ieee.std_logic_unsigned.all and signals of the type STD_LOGIC_VECTOR OR USE ieee.numeric_std.all and signals of the type UNSIGNED and conversion functions: std_logic_vector(), unsigned() 35
Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all; 36
VHDL code for a 6-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder6 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ; Cout : OUT STD_LOGIC ) ; END adder6 ; ARCHITECTURE dataflow OF adder6 IS SIGNAL Sum : STD_LOGIC_VECTOR(6 DOWNTO ) ; BEGIN Sum <= ('' & X) + Y + Cin ; S <= Sum(5 DOWNTO ) ; Cout <= Sum(6) ; END dataflow ; 37
Addition of Unsigned Numbers () LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.numeric_std.all ; ENTITY adder6 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ; Cout : OUT STD_LOGIC ) ; END adder6 ; 38
Addition of Unsigned Numbers (2) ARCHITECTURE dataflow OF adder6 IS SIGNAL Xu : UNSIGNED(5 DOWNTO ); SIGNAL Yu: UNSIGNED(5 DOWNTO ); SIGNAL Su : UNSIGNED(6 DOWNTO ) ; BEGIN Xu <= unsigned(x); Yu <= unsigned(y); Su <= ('' & Xu) + Yu + unsigned('' & Cin) ; S <= std_logic_vector(su(5 DOWNTO )) ; Cout <= Su(6) ; END dataflow ; ECE 448 FPGA and ASIC Design with VHDL 39
Addition of Unsigned Numbers (3) ARCHITECTURE dataflow OF adder6 IS signal Sum: STD_LOGIC_VECTOR(6 DOWNTO ) ; BEGIN Sum <= std_logic_vector( unsigned('' & X) + unsigned(y) + unsigned('' & Cin) ) ; S <= Sum(5 downto ); Cout <= Sum(6) ; END dataflow ; 4
Operations on Signed Numbers For operations on signed numbers USE ieee.numeric_std.all, signals of the type SIGNED, and conversion functions: std_logic_vector(), signed() OR USE ieee.std_logic_signed.all and signals of the type STD_LOGIC_VECTOR 4
Multipliers ECE 448 FPGA and ASIC Design with VHDL 42
Unsigned vs. Signed Multiplication Unsigned Signed 5 - x x 5 x x - 225 43
8x8-bit Unsigned Multiplier 8 8 a b * c U 6 44
Multiplication of unsigned numbers LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_unsigned.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); c : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow; 45
8x8-bit Signed Multiplier 8 8 a b * c S 6 46
Multiplication of signed numbers LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_signed.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); c : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow; 47
8x8-bit Unsigned and Signed Multiplier 8 8 a b cu cs 6 6 48
Multiplication of signed and unsigned LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all ; numbers entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); cu : out STD_LOGIC_VECTOR(5 downto ); cs : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b)); -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b)); end dataflow; 49
Multiplication of signed and unsigned LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all ; numbers entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); cu : out STD_LOGIC_VECTOR(5 downto ); cs : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b)); -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b)); end dataflow; 5
Comparators ECE 448 FPGA and ASIC Design with VHDL 5
4-bit Number Comparator 4 4 A B A > B AgtB 52
4-bit Unsigned Number Comparator 4 4 A B A > B AgtB U AgtB <= '' WHEN A > B ELSE '' ; 53
VHDL code for a 4-bit Unsigned Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '' WHEN A > B ELSE '' ; END dataflow ; 54
VHDL code for a 4-bit Signed Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '' WHEN A > B ELSE '' ; END dataflow ; 55
4-bit Unsigned Number Comparator 4 4 A B AeqB AgtB AltB U 56
VHDL code for a 4-bit Unsigned Number Comparator LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AeqB <= '' WHEN A = B ELSE '' ; AgtB <= '' WHEN A > B ELSE '' ; AltB <= '' WHEN A < B ELSE '' ; END dataflow ; 57
VHDL code for a 4-bit Signed Number Comparator LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AeqB <= '' WHEN A = B ELSE '' ; AgtB <= '' WHEN A > B ELSE '' ; AltB <= '' WHEN A < B ELSE '' ; END dataflow ; 58
Arithmetic operations Synthesizable arithmetic operations: Addition, + Subtraction, - Comparisons, >, >=, <, <= Multiplication, * Division by a power of 2, /2**6 (equivalent to right shift) 59
Arithmetic operations The result of synthesis of an arithmetic operation is a - combinational circuit - without pipelining. The exact internal architecture used (and thus delay and area of the circuit) may depend on the timing constraints specified during synthesis (e.g., the requested maximum clock frequency). 6
Integer Types Operations on signals of the integer types: INTEGER, NATURAL, and their sybtypes, such as TYPE day_of_month IS RANGE TO 3; are synthesizable in the range -(2 3 -).. 2 3 - for INTEGERs and their subtypes.. 2 3 - for NATURALs and their subtypes 6
Integer Types Operations on signals (variables) of the integer types: INTEGER, NATURAL, are less flexible and more difficult to control than operations on signals (variables) of the type STD_LOGIC_VECTOR UNSIGNED SIGNED, and thus are recommened to be avoided by beginners. 62
ROM ECE 448 FPGA and ASIC Design with VHDL 63
ROM 8x6 example () Addr 3 8x6 ROM Dout 6 C 64
ROM 8x6 example (2) LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all; ENTITY rom IS PORT ( ); Addr : IN STD_LOGIC_VECTOR(2 DOWNTO ); Dout : OUT STD_LOGIC_VECTOR(5 DOWNTO ) END rom; 65
ROM 8x6 example (3) ARCHITECTURE dataflow OF rom IS SIGNAL temp: INTEGER RANGE TO 7; TYPE vector_array IS ARRAY ( to 7) OF STD_LOGIC_VECTOR(5 DOWNTO ); CONSTANT memory : vector_array := ( X"8A", X"D459", X"A87", X"7853", X"65D", X"642F", X"F742", X"F548"); BEGIN temp <= to_integer(unsigned(addr)); Dout <= memory(temp); END dataflow; 66
ROM 8x6 example (4) ARCHITECTURE dataflow OF rom IS TYPE vector_array IS ARRAY ( to 7) OF STD_LOGIC_VECTOR(5 DOWNTO ); CONSTANT memory : vector_array := ( X"8A", X"D459", X"A87", X"7853", X"65D", X"642F", X"F742", X"F548"); BEGIN Dout <= memory(to_integer(unsigned(addr))); END dataflow; 67
Buffers ECE 448 FPGA and ASIC Design with VHDL 68
Tri-state Buffer e x f e = (a) A tri-state buffer x f e x f x e = (b) Equivalent circuit f (c) Truth table 69
Tri-state Buffer e x f e = (a) A tri-state buffer x f e x f Z Z x e = (b) Equivalent circuit f (c) Truth table 7
Four types of Tri-state Buffers e e x f x f f <= x WHEN (e(a) = '') ELSE 'Z'; f <= not x WHEN (b) (e = '') ELSE 'Z'; e e x f x f f <= x WHEN (e(c) = '') ELSE 'Z'; f <= not x WHEN (d) (e = '') ELSE 'Z'; 7
Tri-state Buffer entity () LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY tri_state IS PORT ( e: IN STD_LOGIC; x: IN STD_LOGIC; f: OUT STD_LOGIC ); END tri_state; 72
Tri-state Buffer entity (2) ARCHITECTURE dataflow OF tri_state IS BEGIN f <= x WHEN (e = ) ELSE Z ; END dataflow; 73
MLU Example 74
MLU Block Diagram A A MUX_ MUX_4_ NEG_A MUX_ MUX_2 IN IN IN2 OUTPUT IN3 SEL SEL Y Y NEG_Y B B L L NEG_B MUX_3 75
MLU: Entity Declaration LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L : IN STD_LOGIC; L : IN STD_LOGIC; ); END mlu; Y : OUT STD_LOGIC 76
MLU: Architecture Declarative Section ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A : STD_LOGIC; SIGNAL B : STD_LOGIC; SIGNAL Y : STD_LOGIC; SIGNAL MUX_ : STD_LOGIC; SIGNAL MUX_ : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR( DOWNTO ); 77
MLU - Architecture Body BEGIN A<= NOT A WHEN (NEG_A='') ELSE A; B<= NOT B WHEN (NEG_B='') ELSE B; Y <= NOT Y WHEN (NEG_Y='') ELSE Y; MUX_ <= A AND B; MUX_ <= A OR B; MUX_2 <= A XOR B; MUX_3 <= A XNOR B; L <= L & L; with (L) select Y <= MUX_ WHEN "", MUX_ WHEN "", MUX_2 WHEN "", MUX_3 WHEN OTHERS; END mlu_dataflow; 78
Combinational Logic Synthesis for Beginners ECE 448 FPGA and ASIC Design with VHDL 79
Simple rules for beginners For combinational logic, use only concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) 8
Simple rules for beginners For circuits composed of - simple logic operations (logic gates) - simple arithmetic operations (addition, subtraction, multiplication) - shifts/rotations by a constant use concurrent signal assignment ( ) 8
Simple rules for beginners For circuits composed of - multiplexers - decoders, encoders - tri-state buffers use conditional concurrent signal assignment (when-else) (ending with ELSE) selected concurrent signal assignment (with-select-when) (ending with WHEN OTHERS;) 82
Example: VHDL code for a 4-to- MUX LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY mux4to IS PORT ( w, w, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR( DOWNTO ) ; f : OUT STD_LOGIC ) ; END mux4to ; ARCHITECTURE dataflow OF mux4to IS BEGIN WITH s SELECT f <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; END dataflow ; 83
when-else vs. with-select-when () "when-else" should be used when: ) there is only one condition (and thus, only one else), as in the 2-to- MUX 2) conditions are independent of each other (e.g., they test values of different signals) 3) conditions reflect priority (as in priority encoder); one with the highest priority need to be tested first. 84
when-else vs. with-select-when (2) "with-select-when" should be used when there is ) more than one condition 2) conditions are closely related to each other (e.g., represent different ranges of values of the same signal) 3) all conditions have the same priority (as in the 4-to- MUX). 85
Left vs. right side of the assignment Left side <= <= when-else with-select <= Right side Internal signals (defined in a given architecture) Ports of the mode - out - inout Expressions including: Internal signals (defined in a given architecture) Ports of the mode - in - inout 86