上海泛腾电子科技有限公司徐鹤军上海张江高科技园区碧波路 500 号 306 室. Tel :

上海泛腾电子科技有限公司徐鹤军 15901848767 上海张江高科技园区碧波路 500 号 306 室 Tel : 5027-0385

Mission Statement FIVAL focus on design ready-for-production platform, help customer speed up time to market is our mission. Foresight Interact Vigor Adaptability Leadership consider more than Customer needs build partnership with Customer make commitment to Customer take fast Customer response supply the best product to Customer Help our customers solve their design challenges and get to market more quickly and with a competitive advantage. We take advantage of advanced technological abilities and considerable experience in the development and manufacturing of high-quality, highperformance platforms, share customer the value: reduce R&D cost, speed up time to market, alleviate Hardware Design Risk, providing professional sourcing, manufactory and quality management Copyright 2010 Fival Corporation. All Rights Reserved 2

FIVAL TP MULIT-CORE PLATFORM Networking Multimedia Wireless Cloud High Performance Low Power Standard Programming Performance utca inic 1U Rack server ATCA 2U Web server Copyright 2010 Fival Corporation. All Rights Reserved 3

Product roadmap 100 cores - Performance & Scalability - Power, Price, Footprint - Same architecture up and down 16 cores 36 cores 64 cores Double Processor s Every Two Years Scalability Dual core Quad core Up to 8 cores Up to 32 starved cores The Other Solutions: Discontinuity in architectures Limited scalability Power inefficiency # of s 8 Copyright 2010Fival Corporation. All Rights Reserved 8

COMPARE MULTI-CORE PROCESSORS Clock (MHz) CPU Power (W) Chipset Power (W) Packet I/O (Gb/s) Mem I/O(Gb/s) Processor s Issue Width Peak BIPS Peak BIPS/W Tilera TILEPro64 700 22 0 20 200 64 3 134.0 6.10 Cisco SPP 250 35 0 192 175 188 1 47.0 1.34 Intel IXP2855 1500 27 0 25 122 16 1 24.0 0.89 Cavium Octeon CN5860 1000 40 0 25 102 16 2 32.0 0.80 Intel Atom Z530, SCH/US15W chipset 1600 2.2 2.3 0 34 1 2 3.2 0.71 Cavium Octeon CN3860 600 30 0 25 102 16 2 19.2 0.64 Intel Xeon 5508, 5520 chipset 2000 38 27.1 410 205 4 4 32.0 0.49 Intel Xeon 5540, 5520 chipset 2530 80 27.1 410 205 4 4 40.5 0.38 Intel Quad- Xeon 5300, 5000P chipset AMD Turion 64X2 Dual- Mobile TL-56 Intel Mobile 2Duo, 965e chipset Intel Dual- Xeon 5138, Intel 5000P chipset 2330 80 30 0 86 4 4 37.3 0.34 1800 33 0 51 86 2 3 10.8 0.33 2400 35 28 0 68 2 4 19.2 0.30 2130 35 30 0 86 2 4 17.0 0.26 NetLogic XLR 732 1000 32 0 25 8 1 8.0 0.25 AMD Dual- Opteron1218 HE 2600 65 0 192 86 2 3 15.6 0.24 Intel Dual- Xeon7120, E8501 chipset 3000 96 32 0 51 2 4 24.0 0.19 9 Copyright 2010 Fival Corporation. All Rights Reserved 9

PROVEN BEST PERFORMANCE/WATT 2X Quad XEON x86 Server 300W under load 1X FIVAL TP Server 40W under load 30W target (optimized server) Measured by Tier 1 Server OEM running MemcacheD on its own Tilera and x86-based servers One TILEPro64 performance = Dual Quad XEON Much Lower Power 7X Compute/Watt advantage Copyright 2010 Fival Corporation. All Rights Reserved 11

ABOUT MULTICORE A rich heritage in developing the world s leading multicore processors 1994 2002 2004 2007 2009 2010 32-node cache coherent multi-processor based on a mesh First 16 core mesh-based multicore processor (MIT RAW) Tilera founded and funded by Bessemer, Walden First commercial 64-core processor shipping Second generation 36/64-core processors Third generation 16-100-core processors Copyright 2010 Fival Corporation. All Rights Reserved 12

SYSTEM-ON-A-CHIP IN ALL TILE PROCESSORS DDR2 Controller 0 DDR2 Controller 1 SerDes PCIe 0 XAUI 0 SerDes Flexible I/O UART JTAG SPI, I2C GbE 0 GbE 1 SerDes PCIe 1 XAUI 1 SerDes DDR2 Controller 3 DDR2 Controller 2 TILEPro64 Block Diagram *Dynamic Distributed Cache Copyright 2010 Fival Corporation. All Rights Reserved 13

Full-Featured General s Enable Throughput Oriented Computing and Standard Languages Processor Each core is a complete computer 3-way VLIW CPU Designed for low power 200mW per core SIMD instructions: 32, 16, and 8-bit ops Instructions for video (e.g., SAD) and networking Protection and interrupts Single core performance roughly the same as a modern MIPS or ARM core Memory L1 cache: 8KB I, 8KB D, 1 cycle latency L2 cache: 64KB unified, 7 cycle latency 32-bit virtual address space per process 64-bit physical address space Instruction and data TLBs Cache integrated 2D DMA engine in each tile Register File Three Execution Pipelines Cache 16K L1-I 8K L1-D 64K L2 I-TLB D-TLB 2D DMA Runs SMP Linux Runs off-the-shelf open-source C/C++ programs Copyright 2010 Fival Corporation. All Rights Reserved 14

imesh On-Chip Network Distributed resources 2D Mesh peer-to-peer tile networks 5 independent networks Each with 32-bit channels, full duplex Tile-to-memory, tile-to-tile, and tile-to-io data transfer Packet switched, wormhole routed, point-to-point Near-neighbour flow control, dimension-ordered routing Performance and energy efficiency ASIC-like one cycle hop latency 2 Tbps bisection bandwidth 32 Tbps interconnect bandwidth Low power 6 independent networks One static, four dynamic IDN System and I/O MDN Cache misses, DMA, other memory TDN, VDN Tile to tile memory access and coherence UDN, STN User-level streaming and scalar transfer SWITCH MDN TDN UDN IDN VDN STN Achieves scalability and power efficiency Copyright 2010 Fival Corporation. All Rights Reserved 15

CONSOLIDATION OF FUNCTIONS ON A SINGLE PROCESSOR Memory Controller Memory Controller MiCA Misc I/O Video/Audio SSL Clusters of Tiles can be tasked with distinct and virtualized applications PCIe Interfaces Flexible Services Flexible Services Network Stack Network I/O Tile cores excel at mixed workloads: General-purpose compute Network processing Signal processing Apache IPS MiCA mpipe Memory Controller Memory Controller Copyright 2010 Fival Corporation. All Rights Reserved 16

NETWORK APPLIANCE (TOP LAYER) 4G IPS (135W, 2RU) 4G & 10G IPS (80W, 1RU) DDR2 TILE64 I/O, Power, and Control DDR2 L2 Performance 2.5X Power 41% TILE64 replaces 12 chips Simpler design, lower cost Flexible product platform Copyright 2010 Fival Corporation. All Rights Reserved 17

NAPATECH PROVIDES 20 GBPS PATTERN MATCHING SOLUTION BASED ON THE MULTICORE 20Gbps Pattern Matching Adaptor Line rate with min packet Sustained capacity up to 1M flows 100K new flows per second 1 million patterns to match Reasons for choosing multicore Highest performance and low power 20Gbps pattern matching on one chip Standard programming 1 programmer using C and Linux 2 months to demo 9 months to production Copyright 2010 Fival Corporation. All Rights Reserved 18

2010 年网络安全设备领域绿盟科技今日宣布已经在其下一代抗拒绝服务系统 ( Anti-DDoS ) 和网络防护 / 检测系统 ( NIPS/NIDS ) 中采用 Tilera TILEPro64TM 多核处理器新一代的抗拒绝服务系统将于 2010 年 7 月上市, 新一代 IPS/IDS 系统也将在 2010 年晚些时候上市除了采用目前的 Tilera TILEPro64 处理器, 绿盟科技还与 Tilera 公司形成战略合作伙伴关系, 还将在未来的产品研发中采用 Tilera 公司即将上市的 Gx 系列产品, 用以建立其下一代更强大更稳定的安全系统 Tilera 公司是市场领先的多核处理器厂商, 通过网状芯片架构将上百个核心高度集成在一个芯片上, 解决了多核处理器的性能扩展问题及低功耗问题对于 Tilera 的处理器, 可以采用基于标准 Linux 的 gcc 编译器进行编程 TILEPro64 处理器从 2009 年开始就已经量产, 该处理器集成了 64 个高性能处理器核心 4 个内存控制器 PCIe 控制器, 以及高达 22Gbps 的以太网端口 Copyright 2010 Fival Corporation. All Rights Reserved

STANDARD TOOLS AND SOFTWARE STACK Multicore Development Environment Standards-based tools Standard application stack Standard programming SMP Linux 2.6.26 ANSI C/C++ pthreads Integrated tools SGI compiler Standard gdb gprof Eclipse IDE Innovative tools Multicore debug Multicore profile Application layer Open source apps Standard C/C++ libs Operating System layer 64-way SMP Linux Zero Overhead Linux Bare metal environment Hypervisor layer Virtualizes hardware I/O devices drivers Load balancer Applications Linux libraries Operating System Linux kernel and kernel drivers Hypervisor Applications libraries Virtualization and high speed I/O drivers TILE hardware Tile Tile Tile Tile Copyright 2010 Fival Corporation. All Rights Reserved 19

上海泛腾电子科技有限公司徐鹤军 上海张江高科技园区碧波路 500 号 306 室. Tel :

上海泛腾电子科技有限公司徐鹤军上海张江高科技园区碧波路 500 号 306 室. Tel :