Modeling And Simulation Of Microcode Based Asynchronous Memory Built In Self Test For Fault Detection Using Verilog

Modeling And Simulation Of Microcode Based Asynchronous Memory Built In Self Test For Fault Detection Using Verilog Amruta P. Auradkar # and Dr. R. B. Shettar * # M.Tech.,2 nd year, Digital Electronics, B. V. Bhoomaraddi College of Engg. and Technology, Hubli, India * Department Of Electronics and Communication Engg.,B. V. Bhoomaraddi College Of Engg. and Technology, Hubli, India. Abstract Most of SoC today are synchronous and operates at single clock or its derivative. In fact, many effective fault detection methods for such system are developed. But in synchronous processors more than 40% of power is consumed by clock, which is used to synchronize the entire system. The complexity of clock routing to various part of system is increasing due to clock skew. Hence major challenges in synchronous design are clock scaling, clock distribution and timing closure. As trend for smaller feature, higher speed and accuracy continues, clock may affect the performance. Idea of this project is to introduce asynchronous method of testing in which communication between blocks will be through handshaking signal. Due to removal of clock, power consumption is reduced to large extend. The fault detection is done with microcode based MBIST using March SS algorithm. New BIST can be designed by just changing instruction in microcode storage without need of redesign of circuitry. Detailed power, time and area overhead analysis is performed for both synchronous and asynchronous system. Index Terms Memory Built In Self Test, March SS Algorithm, Synchronous MBIST, Asynchronous MBIST. I. INTRODUCTION Embedded memories are becoming very vital part of any SoC. According to International Technology Roadmap for Semiconductors (ITRS) recent report, memory cores will occupy around 90% area on chip. As memories become denser, they are more prone to defects and faults are more complex. BIST is technique used to test memories. MBIST is one of the most widely used and cost effective solution as it does not require external test equipment such as ATE, test can run at circuit speed to yield more realistic test time. The fault models in memories include the address decoder fault (AF), stuck-at fault (SAF), Transition fault (TF), stuck open fault (SOF), coupling fault (CF), neighborhood pattern sensitive fault (NPSF), and data retention fault (DRF) [5]. Several BIST schemes have been proposed to test the faults in embedded RAMS [2,3,4].Many March algorithms were developed to detect faults. Out of this, March SS algorithm is used for detecting both static and dynamic faults as it has good fault coverage compared to other algorithms. Recently many synchronous methods are used for memory testing, but study shows that in such systems most of the power consumption is because of efforts required to synchronize the entire system. This paper initiates the idea of testing a memory asynchronously. II. SYNCHRONOUS MBIST The block diagram of the simple BIST controller architecture together with fault diagnosis interface through input MUX shown in Figure 1. The BIST Control Circuitry consists of Clock Generator, Microcode Instruction storage unit, Test Collar circuitry, Multiplexer, Memory under test and comparator for fault diagnosis. A. Clock Generator This is a simple circuit built for analysis purpose hence single master clock is sufficient to derive all the block In case if we want to go for real time system, the same circuit have to be modified with four clocks (a single master clack and three clocks with different frequencies derived from it). And additionally it will contain instruction register and instruction pointer B. Microcode Instruction Storage The microcode is a binary code that consists of a fixed number of bits, each bit specifying a particular data or operation value. As there is no standard in developing a microcode MBIST instruction [7], the microcode instruction fields can be structured by the designer depending on the test pattern algorithm to be used. The microcode instruction developed in this work is coded to denote one operation in a single microword. Thus a five operation March element is made up by five micro-code words. The format of 7-bit microcode MBIST instruction word is as shown in Table 1. Table1. Format of Microcode Instruction Word #1 #2 #3 #4 #5 #6 #7 Valid F0 I0 L0 I/D R/W Data F0 I0 L0 Description 0 0 0 Single operation Element 1 0 0 I operation of multiple operation 0 1 0 Middle operation of multiple 0 0 1 Last operation of multiple 351

#1Valid #2 F0 #3 I0 #4 L0 #5 I/D #6 R/W #7 Data International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) Clock Generato r Microcode Instruction Storage Address Generator Data Control Input Multiplexer Memory under test R/W Control Test Collar Comparator Mode Norm Data al/te Add R/W st Figure1. Microcode Based Synchronous MBIST Architecture Fault Pulse A. Test Collar It consists of address generator, data control, r/w control. Address Generator points to the next memory address in MUT, according to the test pattern sequence. It can address the memory in forwards as well as backwards direction. RW Control generates read or write control signal for MUT, depending on relevant microword bits. Data Control generates data to be written to or expected to be read out from the memory location being pointed at by the Address Generator. B. Input Multiplexer It directs the input to memory by switching between test algorithm input and input given externally during the normal mode. The control signal for this multiplexer is also given externally by the user. If it indicates test mode then internally generated test data by BIST controller is given to the memory as input from the Test Collar. In case of Normal mode the memory responds to the external address, data and read/write signals. C. Comparator It is used to compare the output from mux and memory. If both the values are matching it will remain low but if both value differ it will generate a pulse indicating a fault. III. MARCH ALGORITHM The format of 7-bit microcode MBIST instruction word is as shown in Table 1. Its various fields are,bit #1 (=1) indicates a valid microcode instruction, otherwise, it indicates the end of test for BIST Controller. Bits #2, #3 and #4 are used to specify first operation, in-between operation and last operation of a multi-operation March element, interpreted as shown in Figure 6.Bit #5 (=1) notifies that the memory under test (MUT) is to be addressed in decreasing order; else it is accessed in increasing order. Bit #6 (=1) indicates that the test pattern data is to be written into the MUT; else, it is retrieved from the memory under test. Bit #7 (=1) signifies that a byte of 1s is to be generated else byte containing all 0s are generated. The instruction word is so designed so that it can accommodate any existing or future March algorithm. The contents of Instruction storage unit for March SS algorithm are shown in Table 2. Table2. MARCH SS Algorithm M0: ᵡ W0 1 0 0 0 0 1 0 M1: { R0 1 1 0 0 0 0 0 R0 1 0 1 0 0 0 0 W0 1 0 1 0 0 1 0 R1 1 0 1 0 0 0 0 W1 } 1 0 0 1 0 1 1 M2: {R1 1 1 0 0 0 0 1 R1 1 0 1 0 0 0 1 W1 1 0 1 0 0 1 1 R1 1 0 1 0 0 0 1 W0 1 0 0 1 0 1 0 M3: {R0 1 1 0 0 1 0 0 R0 1 0 1 0 1 0 0 W0 1 0 1 0 1 1 0 R0 1 0 1 0 1 0 0 W1} 1 0 0 1 1 1 1 M4: {R1 1 1 0 0 1 0 1 R1 1 0 1 0 1 0 1 W1 1 0 1 0 1 1 1 R1 1 0 1 0 1 0 1 W0} 1 0 0 1 1 1 0 M5: ᵡ R0 1 0 0 0 1 0 0 0 X X X X X X 352

Figure2. Microcode Based Asynchronous MBIST Architecture I. ASYNCRONOUS MBIST In Asynchronous MBIST instead of clock, two phase handshaking signals i.e. Request and Acknowledge are used. When a block needs work request data from previous block. The prior block sends the requested input and the success of receive is acknowledged by requesting block. Additional blocks in Asynchronous MBIST are, A. Pulse Generator It generates a Start Pulse at positive edge of the Start signal marking the start of test cycle. relevant bits of microword are sent to other blocks from IR. Comparator makes the comparison of input data from test collar and output data from memory, it the match doesn t exist it will generate the fault pulse along with the faulty address location and correct data that is required to remove fault. II. RESULTS All the blocks are implemented in Xilinx14.2 using Verilog and the simulation results are presented in this section. A. Microcode Instruction Storage B. Instruction Pointer Instruction Pointer points to the next microword, that is the next march operation to be applied to the memory under test (MUT). Depending on the test algorithm, it is able to i) point at the same address, ii) point to the next address, or iii) jump back to a previous address. C. Instruction Register It holds the microword (containing the test operation to be applied) pointed at by the Instruction Pointer. The various 353

B. Test Collar F. Synchronous MBIST RTL Schematics: Comparator Memor y C. Input Multiplexer MIS MUX TC D. Memory under Test Output Waveforms Fault pulse occurred at mismatch between mem and TC E. Comparator 354

III. CONCLUSION The simulation results have shown that the micro-coded MBIST architecture for synchronous memory testing is successfully implemented. Implementation of a single test operation in one microword ensures that any future test algorithms with any number of test operations per test element are successfully implemented using the current BIST architecture. Block diagram of asynchronous MBIST using two way handshaking is presented in the paper and the implementation work is in progress. A detailed power, time and area overhead analysis of this architecture is underway and efforts are being made to develop a power-optimized BIST architecture for embedded memories. As a final step, a comparative study of synchronous and asynchronous systems will be presented. REFERENCES [1] International SEMATECH, International Technology Roadmap for Semiconductors (ITRS): Edition 2001 [2] P. Camurati, P. Prinetta, M. S. Rcorda, P. di Torino, S. Barbagallo, A. Burri, and D. Medina, "An Industrial Experience in the Built-In Self Tcst of Embedded RAMS,'' Proc. 0fI2'~ VLSl Test Symp.. 1994, pp. 306-31 I. [3] G. M. Park and H. Chang, "An Extended March Test Algorithm for Ernbedded Memories," Proc. of 61h Asian Test Symp., 1997, pp. 404-409. [4] C. T. Huang, J. R. Huang, C. F. Wu, C. W. Wu, T. Y. Chang, '"A Programmable BlST Core far Embedded DRAM," IEEE Design and Test of Compulers, January - March 1999, pp. 59-69. [5] A. J. van de Goor and Z. Al-Ars, Functional Fault Models: A Formal Notation and Taxonomy, In Proc. of IEEE VLSI Test Symposium, pp. 281-289, 2000. [6] S. Hamdioui, G.N. Gaydadjiev, A.J.van de Goor, State-of-art and Future Trends in Testing Embedded Memories, International Workshop on Memory Technology, Design and Testing (MTDT 04), 2004. [7] R. Dean Adams, High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test, Springer US, 2003. 355