A Parametric Design of a Built-in Self-Test FIFO Embedded Memory

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1 A Parametric Design of a Built-in Self-Test FIFO Embedded Memory S. Barbagallo, M. Lobetti Bodoni, D. Medina G. De Blasio, M. Ferloni, F.Fummi, D. Sciuto DSRC Dipartimento di Elettronica e Informazione Italtel Politecnico di Milano Settimo Milanese, Italy P.zza L. Da Vinci 32, Milano - Italy Abstract Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into larger devices. A dual port RAM-type FIFO has been designed. A new test procedure for the macrocell has been defined aiming at detecting all possible faults in the control logic and the RAM cell. Given such a test procedure the appropriate Built-In Self Test architecture has been defined, independently of the memory size. Fault coverage and area overhead for the proposed solution are presented. I. Introduction FIFO (First In First Out) memories have acquired a larger interest in VLSI design in telecom applications. Such macrocells provide an efficient way to interface two asynchronous systems, buffering data between subsystems operating at different data rates, thus increasing the flexibility in data transmission. In fact, data in FIFO memories are read following the same order in which they have been written, without the need of providing the address of the data. Different approaches have been considered in literature to design FIFO memory cells. In this paper we define an architecture based on a static RAM cell, available in the Italtel library of components. We aim at defining a parametric architecture whose size can be modified with slight modifications to the basic structure. In order to obtain such a result, the control logic has been designed in a modular way, thus defining a flexible structure, whose basic components are described in VHDL. In particular, the control logic is constituted by two subsystems with two independent clock signals, managing the read and write operations, respectively. Performance and area constraints have driven the design optimizations. The off-line Built-In Self Test (BIST) design technique has been chosen to allow for testing of such a macrocell. Two operation modes are provided: in the normal mode the macrocell performs the nominal operations; in the test mode the macrocell is isolated from the main device into which it is embedded in order to execute the test procedure. The choice for the Built-In Self Test technique is motivated by the requirement of testing such cells when they are deeply embedded into more complex devices, without the necessity of driving long test sequences into the device to the macrocell. Furthermore, such design for testability technique allows testing at the nominal operation frequency also in the application field with accurate test procedures. The BIST architecture has been defined in order to be easily interfaced to the TAP controller for Boundary Scan, thus providing the external inputs dedicated to the test activation following the specific test protocol, in addition to the nominal inputs. A complete fault model for the RAM cell has been taken into account, together with a set of functional faults representing the possible stuck-at faults in the control logic. An extended Single Order Addressed (SOA) march test [5] algorithm has been defined to ensure the fault coverage for all classes of faults identified. The test algorithm has then been efficiently implemented into the test logic, which has been realized as self-testing, to avoid erroneous fault attributions. The test logic structure has been defined in a parametric way in order to be adapted to different memory sizes.

2 The paper is structured as follows. The next section introduces the specifications and the basic architecture of the FIFO memory cell defined. Section III presents the fault model adopted and the test algorithm. Section IV introduces the BIST architecture. Finally section V shows the experimental results in terms of area and fault coverage of the macrocell. II. The architecture of the FIFO memory. Different classes of FIFO memories have been presented and realized in literature. The shifting-type FIFO is based on a shift register of n cells in which data move from the input writing port towards the read output port. When a write operation is performed, from the input write port the datum is inserted into the first cell of the register and shifted of one position, at every clock cycle, until the last free cell is reached. A read operation moves the content of the last cell of the register to the output port, while moving simultaneously the remaining data of one position towards the output port. The structure of such a memory is quite simple, but the main drawback is that each datum written must traverse all n cells of the memory before being available for a read operation, with a minimum delay of n clock cycles. The arbitration RAM-type FIFO is based on a static RAM to store data and on the presence of a write address register and a read address register. Each one of such registers is constituted by an m bit counter (m=log 2 n). A controller manages the read and write operations with the FIFO mode and decides which address register must be provided to the RAM port. This realization, although simple and inexpensive, does not allow simultaneous read and write operations. It is therefore not suitable for applications for which an high frequency of operation is required. The dual-port RAM-type FIFO is based on a dual port RAM cell to allow simultaneous read and write operations. Two different independent address busses are provided, to manage the read and write operation, respectively. The main difference with the arbitration RAM-type FIFO is the duplication of the address bus, thus allowing better performance in terms of maximum operation frequency. Two implementations can be identified based on the data access mode: ring-address RAM-type FIFO and counter-address RAM-type FIFO. The first solution is characterized by the use of two n bit shift-registers in which each cell is uniquely associated in an ordered way with a memory cell. Such an implementation requires a RAM macrocell without address decoder, since the two registers perform both the function of address generation and decoding. Such addressing mode allows the definition of very fast FIFO memories, but the area occupied increases linearly with the size of the memory, due to the increase of the size of the registers. The FIFO memory architecture proposed in this paper is based on the following specifications. The FIFO architecture should exploit a RAM cell available in the Italtel library of components. The read and write speed of the data should be independent. The design should be parametric with the size of the memory, starting from a same basic structure and modifying the minimum number of components. Therefore the architecture should be modular. The final implementation should allow an easy test by means of the introduction of the BIST design for testability technique. The main interface signals of the FIFO memory with the environment are defined in figure 1. FULL EMPTY R FIFO REN ER DATAOUT Figure 1 Interfaces of the FIFO memory with two different subsystems: a writer and a reader. A reset signal is also present which brings the FIFO into its initial state in which the RAM is considered

3 empty, both the read and write addresses are set to 0 and the output EMPTY assumes a 0 value. The EMPTY signal, when 0, indicates that all data in the memory have been read, and therefore any subsequent read request will not be satisfied. The write cycle starts when, on the falling edge of the write clock, the signal is active and the FULL output is not active. The FULL output indicates if a write request can be satisfied, i.e. there are memory cells available to store the new data. If this situation occurs the value present on the lines is stored and the write address will increment its value at the next rising edge of the write clock. The value on the lines must be stable for the entire write request. Whenever a read request is active on the falling edge of the read clock, i.e. the signal is active and the EMPTY output allows a read request to be satisfied, the read controller activates the read enable signal REN on the same clock edge and the read address will be incremented at the next rising edge of the clock. The data value is made available on the DATAOUT lines and remains stable for the entire period of the read clock cycle. Given the specifications, the architecture of the FIFO memory chosen is based on a counter-addressing mode. The dual port RAM is considered as a finite set of cells whose read and write addresses cyclically follow a fixed predefined order, by scanning one after the other all memory cells. The read or write operation consists of three phases: request acquisition, memory enable and counter update. The counter can be updated before the operation or after the memory has been enabled and the operation accomplished. In the first case the counter will be updated when required, while in the latter case the counter will address, at the end of the current operation, the cell that will be accessed by the next operation. This solution has been chosen in the implementation mainly because it will be exploited also for the Built-In Self-Test realization. data input register RAM n x b DATAOUT write counter dual port WEN read counter CK CONTROLLER EMPTY FULL REN Figure 2 The basic structure of the FIFO RAM with counter based addressing mode. To ensure that data read follow the same writing order, the read address can never precede the write address. When the two addresses match there are two possibilities: either all data in the memory have been read (emptyfifo) or no data have been read yet (full-fifo). This behavior can be realized by the structure shown in figure 2, where the address registers are implemented through counters counting up to the number of words in the RAM. The controller is synchronized by its own clock and manages the read and write operations by discriminating the memory conditions of empty-fifo and full-fifo, based on the knowledge of the state of the address counters. The RAM FIFO has been designed with two controllers independently synchronized, which separately manage the read and write operations. The evaluation of the two conditions empty-fifo and full-fifo considering the memory as a circular buffer and observing that the two conditions can be recognized by checking the read and write addresses as well as the number of times the buffer has been traversed. In fact, the empty-fifo condition is verified when the read and write addresses coincide and the buffer has been covered the same number of times. Conversely, The full-fifo condition is verified when the write address is equal to the read address, but it has performed one more cycle with respect to the read address. Obviously, the read address can never be greater than the write address and the addresses can differ for at most one cycle. Therefore the actual number of cycles performed by the read and write addresses is not relevant, the information necessary to evaluate the two conditions concerns the difference between the two cycling of addresses.

4 The implementation of the conditions verification consists of two addressing counters with log 2 n+1 bits, whose most significant bit represents the two conditions. In fact, when the m=log 2 n less significant bits coincide, the analysis of the most significant bit can identify which one of the two conditions has occurred; if the most significant bit is the same, then the same number of words has been read and written, otherwise the number of written words surmounts by n the number of read words. The comparison between the two counter values is performed by the evaluation block, a combinational module which directly outputs the EMPTY and FULL signals. Two separate controllers are used for the acquisition of the read and write requests, respectively. Each controller is synchronized by its own clock ( and ) to provide the correct signals necessary to increment the counters and enable the memory operations. Since a write operation cannot be performed when the FIFO is full and, analogously, a read operation cannot be performed when the FIFO is empty, the Write Controller uses the FULL signal to enable a write request while the EMPTY signal is an input to the Read Controller to enable or disable the read operations. CONTROLLER COUNTER m+1 m+1 EVALUATION BLOCK EMPTY FULL REN CONTROLLER COUNTER WEN INPUT REGISTER b m m RAM n x b dual port DATAOUT Figure 3 Structure of the RAM FIFO with two controllers. The different components of the FIFO architecture presented in figure 3 have been described in VHDL and synthesized with Mentor Graphics Autologic 2. The FIFO behavior is the following. The signal drives the FIFO into the initial condition corresponding to an empty RAM, with the read and write addresses reset to 0 and the output signal EMPTY set to 0 also. The write cycle is activated when the signal is active on the falling edge of the clock while the signal FULL is not. Immediately the Write Controller enables the RAM cell to the write operation of the datum contained in the input register and the write counter to the next clock rising edge. Similarly, the read operation starts when, on the falling edge of the clock signal, the signal is active while the EMPTY signal is disabled. On the same edge of the clock the read controller activates the read enable signal REN and the read counter to update at the next clock rising edge. III. The test algorithm for the RAM FIFO Fault models and tests for single-port RAM-type FIFOs have been described in [1], for ring-address RAMtype FIFOs in [2, 3], and for shifting-type FIFOs in [4]. Dual RAM-type FIFOs with counter addressing as the one described in the previous section cannot be analyzed following the same strategies. The FIFO function defined can be logically partitioned into two blocks: the memory array (the RAM cell), and the control logic which manages the memory addressing and all control signals. Therefore two specific fault models are identified, one for the control logic and one specific for the RAM cell, and as a consequence two test algorithms have been defined, keeping in mind that the final aim is to implement them into a Built-In Self-Test structure. The fault model adopted for the FIFO cell control logic is based on eight classes of functional faults, independent of the memory size and on the implementation, derived considering the requirement of single stuck-at fault detection. 1. After a reset operation, one of the counters or the controller is not reset in the initial state. 2. Assuming the FULL signal is not set, a request is non accepted or a operation is performed when not requested.

5 3. Assuming the EMPTY signal is not set, a request is non accepted or a operation is performed when not requested. 4. Assuming the FULL signal to be set, a request is accepted. 5. Assuming the EMPTY signal to be set, a request is accepted. 6. The FULL signal is set when the memory is not full or is not set when the memory is actually full. 7. The EMPTY signal is set when the memory is not empty or is not set when the memory is actually empty. 8. The output REN is stuck-at 0 or at 1. A test algorithm has been defined for all functional faults: the two counters are modified to generate two additional output signals, WTC and RTC which are set when the counter reaches the value n. The algorithm is shown in table 1. The time required for its execution is T = (4n+3)T ck. The functional fault model of the dual-port static RAM memory adopted for test generation is very comprehensive and includes address faults in the address decoder, stuck-at faults stuck-open faults, transition faults, data retention faults for the memory array cells, coupling faults between cells pairs and multiport faults considering coupling between read and write ports. Such a fault model does not require a detailed knowledge of the memory structure, thus allowing the selection of a different RAM implementation depending on the design constraints. The march tests family has been analyzed to evaluate their suitability for the proposed design. However, nor the traditional march tests [6], nor the algorithms proposed for Single-Address Order Memories [5] can be directly applied to our design since only a single address order can be used and the march elements are constituted by a single write and a single read operation. Therefore a new algorithm has been defined, based on the existing SOA MATS++ algorithm [5]. However such algorithm, while detecting all address faults, stuck-at faults and transition faults in the memory cells does not cover coupling faults between cells. To allow fault coverage of such class of faults the test algorithm has been modified by adding new march elements which detect most of the coupling faults idempotent and the entire class of coupling fault state. Stuck-on faults have been dealt with by introducing pseudo-march elements which alternatively read or write a 0 or 1. Figure 4 shows the extended march test applied. Its time complexity is given by (15n +2nlog 2 b)t ck. The first row corresponds to the original SOA MATS++ algorithm, while the second row represents the added elements to guarantee the detection of coupling fault state caused by the state of the cell, the third row shows the pseudo march elements necessary to detect stuck-open faults, and the fourth row presents the test elements to detect multi-port faults, peculiar of the dual-port RAM considered. # Inputs Expected outputs evaluated # Step applied FULL EMPTY WTC RTC REN Cycles n n NONE , n-2 7, , n Table 1 Test algorithm for the FIFO control logic. The complete test procedure is obtained by composing the test algorithm for the control logic and the march test for the RAM cell, shown in the two tables 1 and 2, respectively.

6 (w0); (r0,w1); (r1,w0); (r0); ); (w1,r1); (w0, r0); (w0 w1); (r0 r1,w1 w0); (r1 r0); (w0 w1 r1 r0) Figure 4 The extended march algorithm for the RAM memory. March # Inputs Inputs Expected # element Step applied RAM outputs Cycles (wa) 13 write n (ra,wā) n (rā,wa) n (ra) n (wā,rā) n (wa,ra) n (wa wā) n (ra rā, n wā wa) (rā ra) n (wa wā , n-2 rā ra) 33, , (wb rb) , n (wc rc) , n (wd rd) , n (wb rb ) , n (wc rc ) , n (wd rd ) , n Table 2 The extended march test algorithm for the RAM cell.

7 IV. The Built-In Self Test architecture The Built-In Self-Test implementation of the test procedure presented in the previous section has been realized by the architecture shown in figure 5. END_TEST RDATA b b COMPARATOR FLAGS EQUAL GENERATOR GO_NGOB GOB_NGO SEQUENCE WDATA M U X FIFO DATAOUT REN FULL EMPTY WTC RTC b CK MR GENERATOR CK CK MR NEXT_SEQ BIST CONTROLLER N_TB CK MR Figure 5 The Built-In Self-Test architecture of the FIFO cell. The BIST controller is enabled by the input signal N_TB such that, when it is set it drives the architecture in test mode and it enables the controller to manage the test procedure. The sequence generator is driven by the controller through the signal NEXT_SEQ and provides the input data to the FIFO and the data to be compared with the output of the FIFO. Furthermore, it provides the signal END_TEST to the flags generator block. Such a block together with the comparator constitute the data outputs evaluator. The flags generator block observes the output of the comparator and verifies that the datum output by the FIFO coincides with expected datum every time the read enable signal REN is set, and when the signal END_TEST is set provides the test result through the dual outputs GO_NGOB and GOB_NGO. To allow the modularity of the BIST structure with respect to the number of words of the FIFO memory, the comparator and the sequence generator blocks depend only on the data width b. Note that in test mode, the structure will be synchronized by a single clock signal and therefore also the FIFO will operate with this single clock signal. Such a clock will correspond either to the read or write clock. The BIST controller is constituted by a finite state machine with 32 states which implement the test algorithm. The controller is synchronized on the rising edge of the clock, thus reading the FIFO outputs on the edge following their switching. It is necessary to provide the detection of single stuck-at faults in the BIST controller. The faults to be detected are those which modify the correct execution of the test procedure implemented. The finite state machine specifies a don t care value to those outputs which do not affect the correct implementation of the test procedure. The assignment to such outputs has been performed then by considering the possibility of detection of those faults of the controller which affect the correct execution of the test procedure of the FIFO. These faults are considered as critical. Such critical faults can cause an undesired transition between two states and they can be detected by a difference between the output and the expected values. Figure 6 shows two significant situations caused by a critical fault: if G(i-1), G(i), G(i+1) constitute the correct sequence of states of the controller, there exists a class of faults which substitutes the correct sequence with G(i-1), F(j), G(i+1), where F(j) represents an unused state of the correct machine. Furthermore, there could be a different class of faults which induces a transition between two non adjacent states, e.g. G(i-1), G(i+1). The result of both situations is that the part of the algorithm implemented by G(i) (being one state or a group of states) is not applied. To avoid the first situation the FSM is specified such that, every time the machine reaches a state unused by the algorithm, the following transition drives the machine into a FAULTY state which stops the sequence generator and sets the END_TEST signal. The second class of critical faults has been overcome by a suitable state assignment and coding and by assigning the don t care values on the outputs so that it is guaranteed that there is a difference in the output values, thus allowing detection of

8 *L *L *L )L ([SHFWHG7UDQVLWLRQ (UURQHRXV7UDQVLWLRQ Figure 6 Possible effects of a critical fault in the controller. Total number of faults % Untestable faults % Possibly detected % Detected % Undetected % Critical % Actual critical faults % Table 3 Fault coverage of the BIST controller. such faults. Table 3 shows a taxonomy of the faults in the BIST controller. Critical faults have been identified through two fault simulations. The first simulation identifies the set of undetected faults of the controller by observing only the two outputs GO_NGOB and GOB_NGO of the flags generator. The second fault simulation considers the set of undetected faults and by observing the outputs of the controller at every clock cycle: those faults that can be detected at this level but not at the outputs are the critical faults. In fact, these actual critical faults are those faults that could affect the correct execution of the test algorithm of the RAM cell. The analysis of the lines stuck-at that cause such faults in the BIST controller has verified that none of them affects the RAM cell but only the test of the FIFO controller, thus implying that an additional fault in such a block could be masked. Thus the single stuck-at fault coverage is guaranteed. The sequence generator is a finite state machine which provides, during the test application, the words WDATA to the FIFO and the expected outputs RDATA to be compared with those read from the FIFO to the comparator. The input NEXT_SEQ, coming from the BIST controller, activates a state transition which implies a switch in one or both the outputs RDATA and WDATA. The output END_TEST is set when the last state of the sequence is reached, and therefore the test sequence has been completed. This signal is sent to the flags generator block which will output the result of the test. The number of states of the machine depends on the data width of the RAM cell, since the part of the test algorithm which allows detection of coupling faults between bits in the same word (steps 36 to 52 in table 2) requires the generation of a number of different words, which depend on the data width b. The number of states of the sequence generator is therefore (17+2log 2 b). The finite state machine can be decomposed in two parts, performing two distinct functions: the first partition concerns the test of the logic and of the memory cells belonging to different words and is independent of the data width of the memory; the second partition deals with coupling faults between bits of the same word. Furthermore, the first partition generates words constituted by all zeros or all ones, while the second partition generates more generic words. This decomposition allows the design of a BIST structure which is more flexible with respect to the data width. Moreover, in case of single-bit RAM cells, only the first partition is necessary. The sequence generator block has been analyzed similarly to the BIST controller, with two fault simulations. Ten critical faults have been identified, of which only two can actually affect the correct execution of the test algorithm of the RAM cell. Finally, the test output evaluation is performed by two blocks: the comparator which verifies if the data at its inputs coincide or not, and the flag generator block which evaluates the output of the comparators and at the end of the test phase provides the test results on the dual outputs GO_NGOB and GOB_NGO. To guarantee the correct operation of the two blocks even in presence of an internal fault and a fault in the RAM cell, a fault simulation has been performed. A single comparator does not provide the required fault coverage, and the specific tests necessary to guarantee its operation require a costly implementation, therefore the comparator has been duplicated thus guaranteeing its correctness. The same problem affects the flags generator block: to guarantee a full fault coverage of the block, it is necessary to observe its outputs at given time instants, instead of only at the beginning and at the end of the test phase. However, this is not easily feasible, therefore the flags generator is composed of

9 two complementary blocks operating in parallel, each generating one of the two flags. V. Experimental results and concluding remarks Let us now analyze the results in terms of fault coverage and area overhead. The BIST structure allows test of the FIFO at its maximum operational frequency. The BIST structure is characterized by 2438 faults, while the FIFO memory is characterized by 894 faults, a total of 3332 faults. The number of untestable faults is 22, while the number of undetected faults is 3. The undetected faults are all associated with the inputs of the flipflops of the read and write controllers. Therefore the fault coverage obtained for the FIFO memory is %. BIST overhead (%) component cell-units area (mm 2 ) BIST logic FIFO logic RAM (10248) Table 4 Area occupied by the FIFO BIST cell for a 1K8 memory bit 16 bit Figure 7 Area overhead for different RAM sizes # FIFO words The test algorithm execution for the FIFO can be affected only by the two faults in the sequence generator, the 0.082% of the total number of faults in the BIST logic. The area overhead of the BIST structure can be evaluated, given the data reported in table 4, as 4.85%. The impact of the BIST structure on the overall memory has been computed for different number of words of the FIFO. Note that, the area of the BIST structure does not depend on the number of words, while it depends on the data width for the sequence generation. Figure 7 shows the reduction of the area overhead with the increase of the data length, and the relative impact of the data width. The performance of the memory is not affected by the introduction of the BIST structure thus allowing its operation at the maximum operational frequency evaluated (76 Mhz). Future work will aim defining a completely parametric architecture of the FIFO cell and the BIST architecture connected. References [1] van de Goor, A.J, Zorian Y., Functional Tests for Arbitration SRAM-type FIFOs; Proc. IEEE First Asian Test Symposium, pp , November [2] van de Goor, A.J, Schanstra I., Zorian Y., Fault Models and Tests for Ring Address Type FIFOs, Proc. 12th IEEE VLSI Test Symposium, pp , April [3] Zorian Y., van de Goor, A.J, Schanstra I., An Effective BIST Scheme for Ring-Address Type FIFOs, Proc. IEEE Int. Test Conference, pp , October [4] van de Goor, A.J, Schanstra I., Zorian Y., Functional Test for Shifting-type FIFOs, Proc. IEEE EDAC, pp , March [5] van de Goor, A.J., Zorian Y., Effective March Algorithms for Testing Single-Order Addressed Memories, Journal of Electronic Testing, Theory and Application (JETTA), vol.5, n.4, November [6] van de Goor, A.J., Testing Semiconductor Memories, Theory and Practice, John Wiley, 1991.