Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany

Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany 2013 The MathWorks, Inc. 1

Agenda Model-Based Design of embedded Systems Software Implementation and Verification Automatic C/C++ code generation Hardware Implementation and Verification Floating- to fixed-point conversion Automatic HDL code generation Code optimization (speed, area, power) Verifiation on different levels of abstraction (HDL co-simulation, FIL) HW/SW Integration on heterogeneous System-on-Chips (SoCs) Execution profiling (SIL, PIL) Generation of target-specific C code Generation of hardware IP interfacing internal system bus Workflow for HW/SW system integration Questions & Answers 2

Things to remember. Best Practice #1: Enable collaboration by integrating workflows with Model-Based Design Best Practice #2: Reduce development time with Automatic Code (C, HDL) generation Best Practice #3: Reduce verification time with Test Bench Reuse 3

Model-Based Design of embedded Systems 2013 The MathWorks, Inc. 4

Demo: PMSM Control Gigabit Ethernet 5

Embedded Coder C Code Generation ARM Cortex-A9 Processor Gigabit Ethernet Plant Model System stimuli Voltage rectification 3-phase inverter Signal measurement PMSM motor model HDL Coder HDL Code Generation Controller AXI Bus Programmable Logic Field Oriented Control Coordinate transforms Torque control loop Speed control loop Vector modulation 6

RESEARCH REQUIREMENTS Traditional Flow SPECIFICATIONS Requirement Documents Difficult to analyze Difficult to manage as they change DESIGN Paper Specifications Easy to misinterpret Difficult to integrate with design EDA Electrical Components Algorithm Design Embeddable Algorithms MCAD/ MCAE Mechanical Components Physical Prototypes Incomplete and expensive Prevents rapid iteration No system-level testing IMPLEMENTATION Manual Coding Time consuming Introduces defects and variance Difficult to reuse C/C++ Embedded Software HDL FPGA/ ASIC Traditional Testing Design and integration issues found late Difficult to feed insights back into design process Traceability INTEGRATION AND TEST 7

Seamless Development RESEARCH DESIGN REQUIREMENTS Idea Environment Models Physical Components Algorithms IMPLEMENTATION TEST & VERIFICATION Algorithm FPGA, C, C++ VHDL, Verilog SPICE DSP MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION Model-Based Design 8

Heterogeneous Systems-on-Chip (SoCs) CPU DSP Memory Single-chip solution containing SW processors HW co-processors and interfaces Bus Chip-internal system bus Optional: analog IPs I/F Co-Proc Analog Challenges HW/SW partitioning System integration 9

Software Implementation and Verification 2013 The MathWorks, Inc. 10

Model-Based Design RESEARCH REQUIREMENTS DESIGN Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 11

C-Code Generation Tools Embedded Coder Simulink Coder MATLAB Coder 12

MATLAB Coder Automatic ANSI C code generation from MATLAB Simulink is not required A GUI for project generation from MATLAB Use configurations to control the generated code Embedded Coder Simulink Coder MATLAB Coder 13

Simulink Coder C code generation from Simulink, Stateflow and Simscape Hardware-in-the-loop testing (external mode) Targeting desktop applications Supports Eclipse IDE Includes Windows OS and Linux OS Target support package Embedded Coder Simulink Coder MATLAB Coder 14

Embedded Coder Major consolidation of MathWorks products to provide a high value solution Targeting real-time embedded systems Code optimization / customization SIL / PIL Profiling Embedded Coder Simulink Coder MATLAB Coder 15

Hardware Implementation and Verification 2013 The MathWorks, Inc. 16

Model-Based Design RESEARCH REQUIREMENTS DESIGN Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 17

Separate Views of DSP Implementation System Designer FPGA Designer Algorithm Design System Test Bench RTL Design Verification Fixed-Point Environment Models IP Interfaces Behavioral Simulation Timing / Control Logic Analog Models HW Architecture Functional Simulation Architecture Exploration Digital Models Static Timing Analysis Algorithms / IP Algorithms / IP Timing Simulation Implement Design Back Annotation FPGA Requirements Hardware Specification Test Stimulus Synthesis Map Place & Route FPGA Hardware 18

Where do you spend most of your time? Algorithm Design Fixed-Point Timing / Control Logic Architecture Exploration Algorithms / IP System Designer FPGA Requirements Hardware Specification Test Stimulus System Test Bench Environment Models Analog Models Digital Models Algorithms / IP Simulating designs? Creating designs and test benches? Analyzing and combining results from multiple tools? Exploring implementation ideas and architectures? Floating point to fixed-point? Writing HW specifications? Iterating over designs with the FPGA designer? Blaming the FPGA designer? 19

Where do you spend most of your time? Simulating designs and validating against HW specs? Creating designs and writing test benches? Hardware architecture design? Writing interfaces to existing IP? Synthesis, Map, PAR cycles? FPGA Designer RTL Design Verification IP Interfaces Behavioral Simulation Hardware Architecture Functional Simulation Static Timing Analysis Timing Simulation Implement Design Back Annotation Iterating over designs with the system designer? Blaming the system designer? Synthesis Map Place & Route FPGA Hardware 20

A Few Ways to Reduce Development Time 1. Increase simulation speed 2. Simplify design entry, system test harness creation, and exploration 3. Automate RTL design & verification to have shorter iteration cycles 4. Integrate the separate workflows to facilitate collaboration, re-use, and prototyping 21

Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Algorithm Design System Test Bench RTL Design Verification Fixed-Point Environment Models IP Interfaces Behavioral Simulation Timing / Control Logic Analog Models Hardware Architecture Functional Simulation Architecture Exploration Digital Models Static Timing Analysis Algorithms / IP Algorithms / IP Timing Simulation Implement Design Back Annotation FPGA Requirements Hardware Specification Test Stimulus Synthesis Map Place & Route FPGA Hardware 22

Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware RTL Design Verification Automatic HDL Code Generation IP Interfaces Hardware Architecture Implement Design Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation Back Annotation Synthesis Map Place & Route FPGA Hardware 23

Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Verification Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Functional Simulation Static Timing Analysis Behavioral Simulation Timing Simulation Implement Design Back Annotation Synthesis Map Place & Route FPGA Hardware 24

Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Verification Automatic HDL Code Generation HDL Co-Simulation Functional Simulation Static Timing Analysis Behavioral Simulation Timing Simulation Back Annotation Implement Design Back Annotation Synthesis Map Implement Design Verification Place & Route FPGA Hardware Synthesis Functional Simulation Map Static Timing Analysis Place & Route Timing Simulation 25

Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA Hardware FPGA-in-the-Loop 26

Automatic HDL Code Generation 27

From Algorithm to Synthesizable RTL MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA-in-the-Loop 28

Fixed-Point Analysis Corner Detection Convert floating point to optimized fixed-point models Automatic tracking of signal range (also intermediate quantities) Word / Fraction lengths recommendation Bit-true models in the same environment Automatically identify and solve fixed-point issues 29

Algorithm to HDL Workflows Simulink to HDL (with MATLAB and Stateflow) MATLAB to HDL 2 1 Hybrid workflow 3 VHDL & Verilog VHDL & Verilog 30

Automatic HDL Code Generation Automatically generate bit true, cycle accurate HDL code from Simulink, MATLAB and Stateflow Full bi-directional traceability!! Requirements 31

Simulink Library Support for HDL HDL Supported Blocks 170 blocks supported Core Simulink Blocks Basic and Array Arithmetic, Look-Up Tables, Signal Routing (Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs, Busses Signal Processing Blocks NCOs, FFTs, Digital Filters (FIR, IIR, Multirate, Adaptive), Rate Changes (Up &Down Sample), Statistics (Min/Max) Communications Blocks Psuedo-random Sequence Generators, Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders 32

MATLAB & Stateflow for HDL HDL Supported Blocks MATLAB Relevant subset of the MATLAB language for modeling and generating HDL implementations eml_hdl_design_patterns: Useful MATLAB Function Block Design Patterns for HDL Stateflow Graphical tool for modeling Mealy and Moore Finite State Machines 33

Integrating Legacy HDL Code HDL Supported Blocks Integrate legacy HDL code in Simulink using black boxes Configure the interface to legacy HDL code HDL Verifier is a special black box 34

Automated Mapping to Floating Point HDL FPGA Vendor Floating Point Libraries Support for: Floating Point Altera Megafunctions Xilinx LogiCORE IP Floating Point Operator Singles and Doubles support 35

HDL Code Optimization 36

From Algorithm to Optimized RTL MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA-in-the-Loop 37

Speed (ns) Design Space Exploration Area Constraint i2 i1 How can you easily explore different implementation solutions? i5 i3 Speed Constraint i4 Acceptable Solution Area(# LUTS, RAMS) 38

Hardware Design Challenges: Timing Analysis Finding the critical path in your model can be challenging 39

Strategies for Speed Improvement Pipelining Input / Output pipeling (Hierarchical) Distributed pipelining Delay Balancing Architectural choices, e.g. Linear, tree, cascade Factored-Canonical-Signed-Digit (FCSD) Newton-Raphson Approximation CORDIC 40

Identifying the critical path Integrating with P&R Timing Analysis Critical Path highlighting: Visual representation of critical path in your model Easier to identify bottlenecks of your model 41

Hardware Design Challenges: Balance Pipeline Registers parallel paths critical path Multiple parallel paths through your model High risk to have unmatched latencies 42

Hardware Design Solution: Distributed Pipelining 43

Strategies for Area Optimization Goal Area reduction Means Time-multiplexed re-use of resources Algorithms Resource Sharing Re-use of identical operators or atomic subsystems within algorithm Resource Streaming Re-use of vectorized operators or subsystems 44

Strategies for Power Optimization Power Dissipation = Static Power + Dynamic Power Static Power = Due to transistor leakage current Significant in smaller silicon geometries Dynamic Power = ½CV 2 fa Function of load capacitance, operating frequency, activity level and voltage swing Steps To Reduce Power: Smaller/Efficient Designs fixed-point optimization Reduce Clock Frequency gated clocks, multiple clocks Control Subsystem Execution gated clocks Low Power Design Libraries/FPGA Devices 45

Multi-rate Models to Reduce Clock Frequency Power Optimization Cycle accurate simulation and implementation Multiple or single clock implementation clk_enable clk clk_enable Timing Controller enb_1_2_1 enb_1_2_0 46

Control Subsystem Execution Power Optimization Enabled Subsystems Modules can be enabled and disabled 47

Control Subsystem Execution Power Optimization Triggered Subsystems Modules can be triggered: rising / falling / either edge 48

HDL Verification 49

Integrated HDL Verification MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA-in-the-Loop 50

Stand-Alone HDL Verification Simulink Test bench Stimulus Simulink Design Targeted to Hardware Reference Results Automatically Generated HDL Test Bench Stimulus HDL Design Actual Results 51

In Out HDL Co-Simulation Re-use system level test bench Combine analysis in HDL Simulator and MATLAB/Simulink Simulink Testbench Stimulus Response Input stimuli HDL Entity Output response HDL Simulator HDL Verifier Connects HDL simulation with the Simulink environment! 52

FPGA-In-the-Loop Verification Re-use the MATLAB/Simulink test bench Accelerate Verification with FPGA Hardware MATLAB/ Simulink Testbench Stimulus Response Input stimuli Output response HDL Verifier Connects FPGA HW with the MATLAB environment! 53

HW/SW Integration on heterogeneous Systems-on-Chip (SoCs) 2013 The MathWorks, Inc. 54

Targeting Heterogeneous Systems Partitioning Through Execution Weights Requirements Capture Hand Code C, C++, HDL System Model Functional Design Float to Fixed Point Plant Model IDDE Simulation and Analysis Execution Weights Partitioning and Implementation through Code Generation C, C++, ASM for MCUs & DSPs IDDE VHDL, Verilog for ASICs & FPGAs Integration Final Design 55

Software Execution Profiling (SIL, PIL) Measures the execution time of the code on the specific target platform during PIL simulations 56 56

Target-specific C Code Generation Exp.: Embedded Coder Support for ARM Cortex-A9 57

Target-specific C Code Generation Exp.: Embedded Coder Support for ARM Cortex-A9 Access on NEON instructions for vector / matrix arithmetic operations Leverage processor peripherals efficiently 58

Targeting Heterogeneous Systems Partitioning Through Execution Weights Requirements Capture Hand Code C, C++, HDL System Model Functional Design Float to Fixed Point Plant Model IDDE Simulation and Analysis Execution Weights Partitioning and Implementation through Code Generation C, C++, ASM for MCUs & DSPs IDDE VHDL, Verilog for ASICs & FPGAs Integration Final Design 59

High-Level Design Flow Simulink Simscape SimPowerSystems Fixed-Point Designer (opt.) MATLAB Coder Simulink Coder Embedded Coder Fixed-Point Designer MATLAB Coder HDL Coder HDL Verifier 60

Summary 2013 The MathWorks, Inc. 61

Things to remember. Best Practice #1: Enable collaboration by integrating workflows with Model-Based Design Best Practice #2: Reduce development time with Automatic Code (C, HDL) generation Best Practice #3: Reduce verification time with Test Bench Reuse 62

Model-Based Design - Basis RESEARCH REQUIREMENTS MATLAB DESIGN Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 63

Model-Based Design - Basis RESEARCH REQUIREMENTS MATLAB DESIGN Simulink Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 64

Model-Based Design - Basis RESEARCH REQUIREMENTS MATLAB DESIGN Simulink Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION Stateflow C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 65

Model-Based Design - Basis RESEARCH REQUIREMENTS MATLAB DESIGN Simulink Timing and Control Logic Digital Models Environment Models Algorithms Analog Models IMPLEMENTATION TEST & VERIFICATION Stateflow Fixed-Point Designer C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 66

Model-Based Design HDL Code Generation RESEARCH REQUIREMENTS MATLAB DESIGN Simulink Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION Stateflow Fixed-Point Designer MATLAB Coder & HDL Coder C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 67

Model-Based Design HDL & FIL Verification RESEARCH REQUIREMENTS MATLAB DESIGN Simulink Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION Stateflow Fixed-Point Designer MATLAB Coder & HDL Coder C, C++ VHDL, Verilog MCU DSP FPGA ASIC SPICE Analog Hardware TEST SYSTEM HDL Verifier INTEGRATION 68

Model-Based Design C Code Generation RESEARCH REQUIREMENTS MATLAB DESIGN Simulink Environment Models Timing and Control Logic Digital Models Analog Models Algorithms IMPLEMENTATION TEST & VERIFICATION Stateflow Fixed-Point Designer MATLAB Coder, Simulink Coder & Embedded Coder C, C++ VHDL, Verilog SPICE MCU DSP FPGA ASIC Analog Hardware TEST SYSTEM INTEGRATION 69

Questions? 2013 The MathWorks, Inc. 70

Thank you! 2013 The MathWorks, Inc. 71