Hardware Modeling. Hardware Description. ECS Group, TU Wien

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Transcription:

Hardware Modeling Hardware Description ECS Group, TU Wien

Content of this course Hardware Specification Functional specification High Level Requirements Detailed Design Description Realisation Hardware Description Hardware Implementation Verification Review Formal verification Simulation

Hardware Description: Outline Design entry Levels of abstraction Schematic entry vs. text-based entry VHDL One possible method to describe hardware History Motivation Range of application

Y-Diagram (1) Behaviour of the circuit Components inside the chip Geometry of the chip

Y-Diagram (2) Behavior system specification System Level Structure CPU,memory B: Functionality and constraints S: Partitioning into subsystems/processes G: (Motherboard-) Layout Geometry chips/board

Y-Diagram (3) Behavior Algorithmic Level Structure algorithms Subsystems (ALU), bus systems B: Operations and calculations S: Scheduling and allocation G: Chip-Layout ICs/blocks Geometry

Y-Diagram (4) Behavior register transfer Register Transfer Level Structure Adder, Reg, MUX B: Finite State Machines S: Data and control paths G: Refined chip layout macrocells Geometry

Y-Diagram (5) Behavior Structure Logic Level boolean equations and, or, flipflop standard-cells B: Boolean functions S: Gate-level Netlist G: Position of standard cells Geometry

Y-Diagram (6) Behavior Structure Circuit Level Differential equations Transistors Mask B: Differential Equations S: Transistor network G: ASIC Mask Geometry

Y-Diagram (7) Behavior Structure Chip The three views describes the same system/chip The same system/chip can be defined on all levels of abstraction Level of detail, information content Geometry

Hardware Description Behavior Algoritmic Level RTL Logic Level Structure Geometry State of the Art

Y-Table Behavior Structure Geometry System Level Inputs : Keyboard Output: Display Funktion:... Speicher CPU IO Control IN OUT Translator Algorithmic Level while input Read Schilling Calulate Euro Display Euro Speicher RS232 16 Interface 8 PS/2 µp IO-Ctrl Interface µp IO-Ctrl PS/2 RS232 Register Transfer Level (RTL) if A=`1` then B:= B+1 else B:= B end if RAM Counter Register ALU R E G A L U Counter Logic Level D = NOT E C = (D OR B) AND A E B >1 & A C INV OR AND Circuit Level du dt di I d 2 I = R + + L dt C dt 2

Hardware Description Languages SystemC UML SysML Verilog VHDL UDL/I Very High Speed Integrated Circuit HDL ABEL Graphical Tools/Lang.

History of VHDL VHSIC... Very High Speed IC VHDL... VHSIC HDL IEEE... Institute of Electrical and Electronics Engineers

Motivation: Documentation Documentation for : Complex systems Maintenance Reusability Different levels of abstraction Readable man-machine interface

Motivation: Data exchange Data exchange between: Orderer and contractor Developers Tools Computing systems

Motivation: Complexity (1) 21%/Yr. Productivity growth rate Design Productivity Gap vs. 58%/Yr. Complexity growth rate

Motivation: Complexity (2) Intel 4004 (1971) Intel P4 (2001) 2300 Transistors 12 mm2 / 10µm 108 khz 42 Millionen Transistors 217 mm2 / 0,18µm 2 Ghz

Motivation: Complexity (3) Trans. count ratio: 1: 18261

Range application of VHDL Behavior Structure Geometry System Level Inputs : Keyboard Output: Display Funktion:... Speicher CPU IO Control IN OUT Translator Algorithmic Level while input Testbench Read Schilling Calulate Euro (VHDL) Display Euro Speicher RS232 16 Interface 8 PS/2 µp IO-Ctrl Interface µp IO-Ctrl PS/2 RS232 Register Transfer Level (RTL) Logic Level if A=`1` then B:= B+1 RAM else B:= B Counter end if V H D L D = NOT E E B C = (D OR B) AND A Register >1 & A ALU C R E G INV OR A L U Counter AND Circuit Level du dt di I d 2 I = R + + L dt C dt 2

Range application of VHDL Behavior Structure Geometry System Level Inputs : Keyboard Output: Display Funktion:... Speicher CPU IO Control IN OUT Translator Algorithmic Level while input Testbench Read Schilling Calulate Euro (VHDL) Display Euro Speicher RS232 16 Interface 8 PS/2 µp IO-Ctrl Interface µp IO-Ctrl PS/2 RS232 Register Transfer Level (RTL) Logic Level if A=`1` then B:= B+1 RAM else B:= B Counter end if V H D L D = NOT E E B C = (D OR B) AND A Register >1 & A ALU C R A Generated E L G U by Tools Counter (Synplify, INV AND OR Synopsys) Circuit Level du dt di I d 2 I = R + + L dt C dt 2 Generated by tools (Quartus, e.g.)

Summary Hardware can be described from different view: Behavioral, Structural and Geometrical Hardware can be described on different Levels of Abstraction VHDL is one approach to describe hardware on RTL and Boolean Level

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