Common Power Format. CPF 1.1 Pocket Guide

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Common Power Format CPF 1.1 Pocket Guide

What is CPF? CPF (Common Power Format) is a design specification language that addresses the limitation in traditional design automation tool flows by capturing the designer's intent for power management and enabling the automation of advanced power-lowering design techniques. The Common Power Format enables all design, verification, implementation - and technology-related power objectives to be captured in a single file and allows the application of that data across the design flow, providing a consistent reference point for design development and production. CPF is available at Si2 s OpenEDA.si2.org web site at no cost for everyone to download and use.download instructions, along with an FAQ with important details on this process, as well as more information on the LPC is located at this link: http://www.si2.org/?page=811. Available supporting tools include a parser, the CPF Pocket Guide - an easy-to-use ready reference book, and the CPF Relational Analyzer - a powerful training and analysis tool (available to LPC members). In addition, training presentations in English, Mandarin, and Japanese are also available for the CPF user. What is the Low Power Coalition? The Low-Power Coalition (LPC) was formed in late 2006 to deliver enhanced capabilities in low-power Integrated Circuit (IC) design flows relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. The intent of the LPC is to develop a unified system approach to low power chip design covering the entire design flow, incorporating all applicable standards as necessary. The LPC is also planning a roadmap of additional enhancements and optimizations for reusable IP blocks and upstream migration of low-power intent. Low Power Coalition Members Advanced Micro Devices ARM Atrenta Azuro, Inc Cadence Design Systems Calypto Design Systems ChipVision Design Systems Entasys Design Envis Corp. Freescale Global UniChip Corp. IBM Corporation Intel Corporation LSI NXP Semiconductors Sequence Design, Inc. Virage Logic The Low Power Coalition guides the evolution of the CPF Standard as well as other design flow-related standards and supporting material. All companies are welcome to join in this unique innovation in the EDA industry. Copyright 2007, 2008 by Si2, Inc. All rights reserved. No part of the material contained herein may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Si2, Inc.

LPC Structure Full LPC Membership Technical Technical Steering Steering Group Group 3 Chief Architects 3 Chief Architects Data Data Model & Model API API WG WG Modeling Modeling WG WG Format Format WG WG LPC: business/policy & standards approvals (AMD, Chair) Technical Steering Group (TSG): charters working groups, owns the low-power technology roadmap Includes 3 Chief Architects (Cadence, IBM, LSI) Active and completed working groups: Data Model and API WG map clear semantics and data relationships in CPF, add API interface support to CPF ModelingWG define requirements and attributes of power models needed at all levels of a power-aware design flow Format WG define priorities and detailed requirements for all revisions of CPF Format Comparison WG report on technical comparison of CPF and UPF (Done, results widely shared)

Who Supports CPF? Industry Leaders AMD Freescale Fujitsu IBM Intel ARC ARM Chipidea Denali LSI NEC NXP STARC Wipro IP Vendors MIPS Tensilica Virage Logic Foundry Reference Flows Common Platform SMIC TSMC UMC EDA Vendors ARC Apache Atrenta Azuro Cadence Calypto Chipvision Entasys Envis Sequence Design Services Alchip DNP Faraday Fujitsu Global Unichip MindTree NEC NSW SOCLE Toppan VeriSilicon CPF Momentum Over 100 CPF design flow engagements now active Completed tape-outs include: NEC (several), Fujitsu (several), Freescale (several), NXP (several), TSMC (several), Global UniChip (several), Faraday (several), AMD 10 EDA tool suppliers committed to CPF (with more coming) ARC, Apache, Atrenta, Azuro, Cadence, Calypto, Chipvision, Entasys Design, Envis, Sequence Design

CPF Information Model CPF 1.1 Information Model prefix string Rule Power Switch enable_condition_1 expr enable_condition_2 expr acknowledge_receiver expr gate_bias_net power_net peak_ir_drop_limit float average_ir_drop_limit float State Retention restore_edge expr save_edge expr restore_level expr save_level expr restore_precondition expr save_precondition expr target_type {flop latch both} Isolation isolation_condition expr no_condition isolation_target {from to} isolation_output { high low hold tristate} Level Shifter Inter-domain from power_domain_list to power_domain_list exclude pin_list location {from to} within_hierarchy instance Scope * path port_mapping domain_mapping Si2 all rights reserved parameter_mapping CPF version hierarchy separator array_naming_style regisiter_naming_style power_unit power_target: leakage assertion Mode Transition start_condition expr end_condition expr cycles [integer:]integer clock_pin pin power_target: dynamic latency[float:]float Assertion Control time_unit shut_off_condition instances where used type {reset suspend} from to Power Module Design -honor_boundary_port_domain parameters external power, ground secondary Macro Power Domain -default shutoff_condition expr -external_controlled_shutoff default_isolation_condition expr default_restore_edge expr default_save_edge expr default_restore_level expr default_save_level expr power_up_states {high low random} user_attributes string_list transition_slope [float:]float transition_latency {from_nom latency_list} transition_cycles {from_nom cycle_list clock_pin} secondary cells secondary boundary Instance Pin base power, ground, pmos_bias, nmos_bias Module boundary Virtual Ports Net power_related_net user_attributes string_list peak_ir_drop_limit float average_ir_drop_limit float Bias supply voltage {float voltage_range} external_shutoff_condition expr internal Power Ground Power Mode -activity_file_weight weight peak_ir_drop_limit domain_voltage_list average_ir_drop_limit domain_voltage_list leakage_power_limit float dynamic_power_limit float group@mode domain@ condition Nominal Condition voltage float ground_voltage float state {on off standby} pmos_bias_voltage float nmos_bias_voltage float Illegal Domain Configuration power mode control groups SDC Activity File Power Mode Control Group active states condition expr Legend Power Domain Library Set user_attributes Library Group Library (.lib) Cell optional many 1 & only 1 heirarchy named CPF object Generalization unnamed object CPF object RTL/netlist object Analysis View user_attributes group@view domain@ corner Operating Corner voltage float ground_voltage float pmos_bias_voltage float nmos_bias_voltage float process float temperature float This CPF information model shows how the constraints in CPF interact with a design.

The syntax and grammar of the CPF commands in this guide are described with Extended Backus Naur form (EBNF). Extendend Backus Naur Form A vertical bar separates a list of alternative items. Only one item from the list is used. set_power_unit { pw nw uw mw W } Examples set_power_unit pw set_power_unit nw set_power_unit uw set_power_unit mw set_power_unit W error set_power_unit MW since MW (Megawatt) is not an list item Square brackets [ ] indicate than an argument is optional. Everything enclosed between the two brackets is not used if that option is not used. set_time_unit [ns us ms] Curly braces } enclose a hierarchical lists of items create_power_domain -name power_domain { { -default [-instances instance_list] [-boundary_ports pin_list] } { -instances instance_list [-boundary_ports pin_list] } { -instances instance_list } } Curly braces { }+ indicate that one or more of the previous list can be used create_level_shifter_rule {-pins pin_list -from power_domain_list -to power_domain_list } + The data type of each argument is specified set_switching_activity { -all -pins pin_list -instances instance_list [-hierarchical]} { -probability float -toggle_rate float [-clock_pins pin_list] -toggle_percentage float } [-mode mode] set_time_unit ns set_time_unit us set_time_unit ms current_unit set_time_unit no argument returns the current time unit create_power_domain -name PD1 -default create_power_domain -name PD1 -default / -instances {inst_a inst_b} create_power_domain -name PD2 / -instances {inst_a inst_b} create_level_shifter_rule -name shiftup / -pins {adder[0] adder[1]} -from {PD1 PD2} / -pins {adder[15] adder[16]} -from {PD1 PD2} / -pins {adder[30] adder[31]} -from {PD1 PD2} set_switching_activity -pins {enable[1] enable[2]} \ -probability 0.65 -toggle_rate 300000124.5

CPF Command Syntax assert_illegal_domain_configurations { -domain_conditions domain_condition_list -group_modes group_modes_list -domain_conditions domain_condition_list -group_modes group_mode_list } create_analysis_view -mode mode [ -user_attributes string_list] { -domain_corners domain_corner_list -group_views group_view_list -domain_corners domain_corner_list -group_views group_view_list} create_assertion_control { -assertions assertion_list -domains power_domain_list } [ -exclude assertion_list] [ -shutoff_condition expression] [ -type {reset suspend} ] create_bias_net -net net [-driver pin] [-user_attributes string_list] [-peak_ir_drop_limit float] [-average_ir_drop_limit float] create_global_connection -net net -pins pin_list [-domain domain -instances instance_list] create_ground_nets -nets net_list [-voltage {float voltage_range}] [-external_shutoff_condition expression -internal] [-user_attributes string_list] [-peak_ir_drop_limit float] [-average_ir_drop_limit float] create_isolation_rule [-isolation_condition expression -no_condition] {-pins pin_list -from power_domain_list -to power_domain_list}+ [-exclude pin_list] [-isolation_target {from to}] [-isolation_output { high low hold tristate}] [-secondary_domain power_domain] Description and Examples Asserts that a particular configuration of domain conditions and/or power mode control group conditions is illegal. Creates an analysis view and associates a list of operating corners with a given mode. Inhibits evaluation of any selected assertion instance when its related power domain is powered down. Specifies or creates a bias net to be used as a power supply to either forward or backward bias a transistor. Specifies how to connect a global net to the specified pins. A global net can be a data net, bias net, power net or ground net. Specifies or creates a list of ground nets. Defines a rule for adding isolation cells and specify which net segments must be isolated.

create_level_shifter_rule {-pins pin_list -from power_domain_list -to power_domain_list}+ [-exclude pin_list] create_mode_transition -from power_mode -to power_mode -start_condition expression [-end_condition expression] [ -cycles [integer:]integer -clock_pin clock_pin -latency [float:]float ] create_nominal_condition -voltage float [-ground_voltage float] [-state {on off standby}] [-pmos_bias_voltage float] [-nmos_bias_voltage float] create_operating_corner -voltage float [-ground_voltage float] [-pmos_bias_voltage float] [-nmos_bias_voltage float] [-process float] [-temperature float] -library_set library_set create_power_domain -name power_domain [-instances instance_list] [-boundary_ports pin_list] [-default] [-shutoff_condition expression [-external_controlled_shutoff]] [-default_isolation_condition expression ] [-default_restore_edge expr -default_save_edge expr -default_restore_edge expr -default_save_edge expr -default_restore_level expr -default_save_level expr ] [-power_up_states {high low random} ] [-active_state_conditions active_state_condition_list ] [-base_domains domain_list] create_power_mode [-default] {-domain_conditions domain_condition_list -group_modes group_mode_list -domain_conditions domain_condition_list -group_modes group_mode_list } Defines a rule for adding level shifters. Describes how the transition between two power modes is controlled, and the time it takes for each power domain to complete the transition. Creates a nominal operating condition with the specified voltage Defines an operating corner and associate it with a library set. Creates a power domain and specifies the instances, boundary ports and pins that belong to this power domain. Defines a power mode. One and only one power mode can be the default power mode.

create_power_nets -nets net_list [-voltage {float voltage_range}] [-external_shutoff_condition expression -internal] [-user_attributes string_list] [-peak_ir_drop_limit float] [-average_ir_drop_limit float] create_power_switch_rule -domain power_domain {-external_power_net net -external_ground_net net} create_state_retention_rule { -domain power_domain -instances instance_list } [ -exclude instance_list ] [ -restore_edge expr -save_edge expr -restore_edge expr -save_edge expr -restore_level expr -save_level expr ] [ -restore_precondition expr] [ -save_precondition expr] [ -target_type {flop latch both}] [ -secondary_domain domain] define_library_set -name library_set -libraries list [-user_attributes string_list] end_design [ module ] end_macro_model [ macro_cell ] end_power_mode_control_group get_parameter parameter_name Specifies or creates a list of power nets. The power nets are created within the current scope. Specifies how a single on-chip power switch must connect the external power or ground nets to the primary power or ground nets of the specified power domain. Defines a rule for replacing either the selected registers in the instance list or all of the registers in the specified power domain with state retention registers. Creates a library set. Used with a set_design command, groups a number of CPF commands that apply to the current design or top design. Used with a set_macro_model command, groups a number of CPF commands that apply to the described macro cell. Used with a set_power_mode_control_group command, groups a set of CPF commands that define the power modes and power mode transitions that apply to the group defined by the preceding set_power_mode_control_group command. Returns the value of a predefined parameter in the current design.

identify_always_on_driver -pins pin_list [-no_propagation] identify_power_logic -type isolation {-instances instance_list -module name} identify_secondary_domain -secondary_domain domain { -instances instance_list -cells cell_list } [ -domain power_domain [ -from power_domain -to power_domain]] include file set_array_naming_style [string] set_cpf_version [value] set_design module [-ports port_list] [-honor_boundary_port_domain] [-parameters parameter_value_list] set_equivalent_control_pins -master pin -pins pin_list { -domain domain -rules rule_list } set_floating_ports port_list set_hierarchy_separator [character] Specifies a list of pins in the design that must be driven by always-on buffer or inverter instances. Identifies any generic logic used for isolation that is instantiated in RTL or the gate-level netlist. Identifies the secondary power domain for the selected instances with multiple power and ground pins. The primary power and ground nets of this secondary power domain are connected to the non-switchable power and ground pins of the identified instances. Includes a CPF file or a Tcl file within a CPF file. Specifies the format used to name the design objects in the netlist starting from multi-bit arrays in the RTL description. Specifies the version of the format. Specifies the name of the module to which the power information in the CPF file applies. Specifies a list of pins that are equivalent with a master control pin. The master control pin is part of the definition of a shutoff condition, isolation condition or state retention condition. The referred condition can contain only the master control pin in its expression. Specifies a list of ports of a macro cell that are not connected to any logic inside the macro cell. Specifies the hierarchy delimiter character used in the CPF file.

set_input_voltage_tolerance -ports port_list -bias [float:]float set_instance [instance [-design design -model macro_model] [-port_mapping port_mapping_list] [-domain_mapping domain_mapping_list] [-parameter_mapping parameter_mapping_list]] set_macro_model macro_cell set_power_mode_control_group -name group { -domains domain_list -groups group_list -domains domain_list -groups group_list} set_power_target { -leakage float -dynamic float -leakage float -dynamic float} set_power_unit [pw nw uw mw W] set_register_naming_style [string%s] set_switching_activity { -all -pins pin_list -instances instance_list [-hierarchical]} { -probability float -toggle_rate float [-clock_pins pin_list] -toggle_percentage float } [-mode mode] set_time_unit [ns us ms] set_wire_feedthrough_ports port_list Specifies a list of input ports of a macro cell that can be driven by a signal with a higher voltage than the power supply voltage defined by the associated power domain of these ports without the need for level shifters. Changes the scope to the specified instance or links a previously defined CPF model to the specified instance. Indicates the start of the CPF content of a custom IP. Groups a list of power domains and other power mode control groups. Specifies the targets for the average leakage and dynamic power of the current design across all the power modes. All power targets must be specified in the units specified by the set_power_unit command. Specifies the unit for all power values in the CPF file. Specifies the format used to name flip-flops and latches in the netlist starting from the register names in the RTL description. Specifies activity values (toggle rate and probability) for the specified pins. Specifies the unit for all time values in the CPF file. Specifies a list of input ports and output ports of a macro cell that are internally connected to each other by a physical wire only.

update_isolation_rules -names rule_list { -location {from to} -within_hierarchy instance -cells cell_list -prefix string -open_source_pins_only}+ update_level_shifter_rules -names rule_list { -location {from to} -within_hierarchy instance -cells cell_list -prefix string}+ update_nominal_condition -name condition -library_set library_set update_power_domain -name domain { -primary_power_net net -primary_ground_net net -equivalent_power_nets list_of_power_nets -equivalent_ground_nets list_of_ground_nets -pmos_bias_net net -nmos_bias_net net -user_attributes string_list -transition_slope [float:]float -transition_latency { from_nom latency_list} -transition_cycles { from_nom cycle_list clock_pin} }+ update_power_mode -name mode { -activity_file file -activity_file_weight weight -sdc_files sdc_file_list -setup_sdc_files sdc_file_list -hold_sdc_files sdc_file_list -peak_ir_drop_limit domain_voltage_list -average_ir_drop_limit domain_voltage_list -leakage_power_limit float -dynamic_power_limit float}+ update_power_switch_rule { -enable_condition_1 expression -enable_condition_2 expression -acknowledge_receiver_1 expression -acknowledge_receiver_2 expression -cells cell_list -gate_bias_net power_net -prefix string -peak_ir_drop_limit float -average_ir_drop_limit float }+ Appends the specified isolation rules with additional implementation information. At least one option besides -name, must be specified; several options may be updated together. Appends the specified level shifter rule with implementation information. Associates a library set with the specified operating condition. Specifies implementation aspects of the specified power domain. Specifies the constraints for the power mode. At least one option besides name must be specified; several options may be updated together Appends the specified rules for power switch logic with implementation information.

update_state_retention_rules -names rule_list { -cell_type string -cells cell_list -set_reset_control}+ Appends the specified rules for state retention logic with implementation information. Commands to configure the Cell Library define_always_on_cell -cells cell_list [-library_set library_set] [ {-power_switchable LEF_power_pin -ground_switchable LEF_ground_pin -power_switchable LEF_power_pin -ground_switchable LEF_ground_pin} -power LEF_power_pin -ground LEF_ground_pin ] Identifies the library cells in the.lib files with more than one set of power and ground pins that can remain powered on even when the power domain they are instantiated in is powered down. define_isolation_cell -cells cell_list [-library_set library_set] [-always_on_pins pin_list] [ {-power_switchable LEF_power_pin -ground_switchable LEF_ground_pin} -power LEF_power_pin -ground LEF_ground_pin ] [-valid_location { from to on off}] {-enable pin -no_enable {high low hold}} [-non_dedicated] Identifies the library cells in the.lib files that must be used as isolation cells.

define_level_shifter_cell -cells cell_list [-library_set library_set] [-always_on_pins pin_list] { -input_voltage_range {voltage voltage_range} -output_voltage_range {voltage voltage_range} -ground_input_voltage_range {voltage voltage_range} -ground_output_voltage_range {voltage voltage_range} -input_voltage_range {voltage voltage_range} -output_voltage_range {voltage voltage_range} -ground_input_voltage_range {voltage voltage_range} -ground_output_voltage_range {voltage voltage_range} } [-direction {up down bidir}] [-input_power_pin LEF_power_pin] [-output_power_pin LEF_power_pin] [-input_ground_pin LEF_ground_pin] [-output_ground_pin LEF_ground_pin] [-ground LEF_ground_pin] [-power LEF_power_pin] [-enable pin] [-valid_location {to from either}] define_open_source_input_pin -cells cell_list -pin pin [-library_set library_set] define_power_clamp_cell -cells cell_list -data pin -power pin [-ground pin_name] [-library_set library_set] Identifies the library cells in the.lib files that must be used as level shifter cells. Specifies a list of cells that contain open source input pins. Specifies a list of diode cells used for power clamp control.

define_power_switch_cell -cells cell_list [-library_set library_set] -stage_1_enable expression [-stage_1_output expression] [-stage_2_enable expression [-stage_2_output expression]] -type {footer header} [-enable_pin_bias [float:]float] [-gate_bias_pin LEF_power_pin] [-power_switchable LEF_power_pin -power LEF_power_pin -ground_switchable LEF_ground_pin -ground LEF_ground_pin ] [-stage_1_on_resistance float [-stage_2_on_resistance float]] [-stage_1_saturation_current float] [-stage_2_saturation_current float] [-leakage_current float ] define_related_power_pins -data_pins pin_list -cells cell_list [-library_set library_set ] {-power LEF_power_pin -ground LEF_ground_pin -power LEF_power_pin -ground LEF_ground_pin } define_state_retention_cell -cells cell_list [-library_set library_set] [-cell_type string] [-always_on_pins pin_list] [-clock_pin pin] {-restore_function expression -save_function expression -restore_function expression -save_function expression } [-restore_check expression] [-save_check expression] [-always_on_components component_list] [ {-power_switchable LEF_power_pin -ground_switchable LEF_ground_pin -power_switchable LEF_power_pin -ground_switchable LEF_ground_pin} -power LEF_power_pin -ground LEF_ground_pin ] Identifies the library cells in the.lib files that must be used as power switch cells. Specifies the relationship between the power pins and data pins for cells that have more than one set of power and ground pins. Identifies the library cells in the.lib files that must be used as state retention cells.

Example of CPF Constructs Example of CPF Constructs #----------------------------------- set_design mod_b create_power_domain -name PDX default create_state_retention_rule -name RETB1 -domain PDX end_design mod_b # CPF File of Top Design #------------------ set_design top # Set up logic structure for all power domains #--------------------------------------------- include IPB.cpf create_power_domain -name PD1 default create_power_domain -name PD2 -instances {inst_a} \ -shutoff_condition {!pm_inst.pse_enable[0]} -base_domains PD1 \ -default_restore_edge {!pm_inst.pge_enable[0]} create_power_domain -name PD3 -instances inst_c \ -shutoff_condition {!pm_inst.pse_enable[1]} -base_domains PD1 create_power_domain -name PD4 -instances inst_d \ -shutoff_condition {!pm_inst.pse_enable[2]} -base_domains PD1 # Define static behavior of all power domains and specify # timing constraints #---------------------------------------------------------------------- set_instance inst_b -domain_mapping { PDX PD2 } create_nominal_condition -name high -voltage 1.2 create_nominal_condition -name medium -voltage 1.1 create_nominal_condition -name low -voltage 1.0 create_power_mode -name PM1 -domain_conditions \ {PD1@high PD2@medium PD3@high PD4@low} update_power_mode -name PM1 -sdc_files../scripts/cm1.sdc \ -activity_file../sim/top_1.tcf -activity_file_weight 1 create_power_mode -name PM2 -domain_conditions \ {PD1@high PD3@high PD4@low} update_power_mode -name PM2 -sdc_files../scripts/cm2.sdc create_power_mode -name PM3 -domain_conditions {PD1@high PD4@low} create_power_mode -name PM4 -domain_conditions {PD1@low} # Set up required isolation and state retention rules for all domains #-------------------------------------------------------------------- create_state_retention_rule -name sr1 -domain PD3 \ -restore_edge {!pm_inst.pge_enable[1]} create_state_retention_rule -name sr2 -domain PD4 \ -restore_edge {!pm_inst.pge_enable[2]} -isolation_condition {pm_inst.ice_enable[0]} -isolation_output high create_isolation_rule -name ir2 -from PD3 \ -isolation_condition {pm_inst.ice_enable[1]} create_isolation_rule -name ir3 -from PD4 \ -isolation_condition {pm_inst.ice_enable[2]} create_level_shifter_rule -name lsr1 -to {PD1 PD3} end_design www.si2.org www.openeda.si2.org

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