ECE 545 Lecture 2 FPGA Resources George Mason University
Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2
What is an FPGA? Configurable Logic Blocks Block RAMs Block RAMs I/O Blocks Block RAMs 3
Modern FPGA RAM blocks Multipliers Multipliers/DSP units Logic Logic resources blocks (#Logic resources, #Multipliers/DSP units, #RAM_blocks) Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN 7567643 Copyright 24 Mentor Graphics Corp. (www.mentor.com) 4
CLB Structure George Mason University
Xilinx Spartan-6 CLB 6
SLICEX ECE 448 FPGA and ASIC Design with VHDL 7
4-input LUT (Look-Up Table) (used in earlier families of FPGAs) x x 2 x 3 x 4 y x x 2 x 3 x 4 LUT y x x 2 x 3 x 4 x x 2 x 3 x 4 y Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs x x 2 y y 8
6-Input LUT of Spartan-6 9
Reset and Set Configurations No set or reset Synchronous set Synchronous reset Asynchronous set (preset) Asynchronous reset (clear)
Three Different Types of Slices in Xilinx FPGAs 2
SLICEX 3
SLICEL 4
Fast Carry Logic u u Each CLB contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters Carry logic is independent of normal logic and routing resources MSB LSB Carry Logic Routing 5
Carry & Control Logic in Xilinx FPGAs x y COUT y CIN CIN y x y Propagate = x Å y Generate = y Sum= Propagate Å CIN = x Å y Å CIN
Carry & Control Logic in Spartan 3 FPGAs x y LUT Hardwired (fast) logic
x y Simplified View of a Xilinx FPGA Carry and Arithmetic Logic in One Logic Cell
2
Accessing Carry Logic u All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then ) Counters (count <= count +) 2
SLICEM 22
Xilinx Multipurpose LUT (MLUT) 6-bit 32-bit SR 6 64 x RAM 4-input 64 x ROM LUT (logic) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN 7567643 Copyright 24 Mentor Graphics Corp. (www.mentor.com) 23
MLUT as a 32-bit Shift Register (SRL32) 24
Question How many Xilinx LUTs are necessary to implement the following functions: A. f = x x 2 + x 3 x 4 + x 5 x 6 f 2 = x x 2 x 3 x 4 x 5 B. f = x x 2 + x 2 x 3 + x 3 x 4 + x 4 x 5 f 2 = x +x 2 +x 3 +x 4 +x 5 25
Question 2 How many Xilinx LUTs are necessary to implement: A. 4-to- MUX B. 2-to-4 decoder with enable C. 3-to-8 decoder with enable 26
Question 3 How many Xilinx LUTs are necessary to implement 4-bit priority encoder? w w w w 2 w 3 y y z y w 3 w 2 - w - - w y - - - d y d z 27
Question 4 How many Xilinx LUTs are necessary to implement the following circuit: 28
Question 5 Determine the amount of Xilinx FPGA resources needed to implement a given circuit George Mason University
Circuit : Top level w m run R R R2 R3 R4 R5 R6 R7 R8 R9 a b c d F y R R R2 R3 R4 R5 clk
2 3 4 5 6 7 cin x y cout s <<<3 x3 x2 x x y3 y2 y y w w En y3 y2 y y a b c d a b c d c a b e e f 3 2-to-4 Decoder Full Adder f g h g h y Circuit : F function
Circuit 2: Top level z d run R R R2 R3 R4 R5 R6 R7 a R8 b c F y R9 d e R R R2 R3 R4 R5 clk
2 3 4 5 6 7 x y cout s >>2 x3 x2 x x y3 y2 y y y y z w3 w2 w w a b c d a e f g h 3 Priority Encoder Half Adder g h i e i y a b c d Circuit 2: F function
Circuit 3: Top level
32 x 32 32 32 Circuit 4: Top level clk en clk en ena clk en R ena R ena clk R2 R3 en ena 32 y() y() 6 6 6 6 + 6 6 A A>B B
Input/Output Blocks (IOBs) ECE 448 FPGA and ASIC Design with VHDL George Mason University
Basic I/O Block Structure Three-State FF Enable Clock Set/Reset Output FF Enable D EC SR D EC SR Q Q Three-State Control Output Path Direct Input FF Enable Registered Input Q D EC SR Input Path 37
IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed 38
FPGA Design Flow George Mason University
FPGA Design process () Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 83 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds.. Specification / Pseudocode On-paper hardware design (Block diagram & ASM chart) Library IEEE; use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(3 downto ); data_output: out std_logic_vector(3 downto ); out_full: in std_logic; key_input: in std_logic_vector(3 downto ); key_read: out std_logic; ); end AES_core; VHDL description (Your Source Files) Functional simulation Synthesis Post-synthesis simulation
FPGA Design process (2) Implementation Timing simulation Configuration On chip testing
Synthesis George Mason University
Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A:STD_LOGIC; signal B:STD_LOGIC; signal Y:STD_LOGIC; signal MUX_, MUX_, MUX_2, MUX_3: STD_LOGIC; begin A<=A when (NEG_A='') else not A; B<=B when (NEG_B='') else not B; Y<=Y when (NEG_Y='') else not Y; end MLU_DATAFLOW; MUX_<=A and B; MUX_<=A or B; MUX_2<=A xor B; MUX_3<=A xnor B; with (L & L) select Y<=MUX_ when "", MUX_ when "", MUX_2 when "", MUX_3 when others; 43
Circuit netlist (RTL view) 44
Mapping LUT FF LUT LUT2 FF2 45
Implementation George Mason University
Implementation After synthesis the entire implementation process is performed by FPGA vendor tools 47
Mapping LUT FF LUT LUT2 FF2 48
Placing FPGA CLB SLICES 49
Routing FPGA Programmable Connections 5
Configuration Once a design is implemented, you must create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information 5
Synthesis Two main stages of the FPGA Design Flow Implementation Technology independent Technology dependent RTL Synthesis Map Place & Route Configure - Code analysis - Derivation of main logic constructions - Technology independent optimization - Creation of RTL View - Mapping of extracted logic structures to device primitives - Technology dependent optimization - Application of synthesis constraints -Netlist generation - Creation of Technology View - Placement of generated netlist onto the device -Choosing best interconnect structure for the placed design -Application of physical constraints - Bitstream generation - Burning device