ECE 3220 Digital Design with VHDL. Course Information. Lecture 1

Transcription

1 ECE 3220 Digital Design with VHDL Course Information Lecture 1

2 Course Information Course #: ECE 3220 Course Name: Digital Design with VHDL Course Instructor: Dr. Vida Vakilian Course Objective: To analyze and design combinational and sequential logic circuits. To write VHDL code to describe and synthesize both types of logic circuits.

3 Course Information Textbooks Main book: Fundamental of Digital Logic with VHDL Design, 3 th edition, Stephen Brown and Zvonko Vranesic, McGraw-Hill, 2008 Supplementary books: 1) Digital systems design using VHDL, Charles H. Roth, JR 2) Digital Electronics a Practical Approach with VHDL, 9 th edition, William Kleitz

4 Lab Information Labs performed weekly. In our Labs, we use Altera DE2 board

5 Homework Homework will be assigned on a weekly basis. Homework is due at the beginning of class on the date specified. No late submissions accepted. You can discuss the homework problems with one another. However, you must submit your own work. Copying solutions is considered cheating. Homework is essential to the learning process!

6 Exams One midterm exam. Midterm and final exams are closed-book. No make-up exams. In the case of an emergency, see me. Notify me in advance (whenever possible) if a conflict or problem exists.

7 Grading The final grade will be calculated as follows: Homework 10% Lab 20% Midterm 30% Final Exam 40%

8 Digital Hardware Design

9 First Integrated Circuit (IC) In 1958, Jack Kilby made the first IC when he was woking at Texas Instruments. He successfully interconnected several transistors, resistors and capacitors by hand on a single substrate.

10 First Integrated Circuit (IC)

11 First Microprocessor: Intel 4004 u In November 1971, Intel introduced the world's first single chip microprocessor, called the Intel 4004.

12 Development Process Required product Design specifications Initial design Simulation Design correct? No Redesign The development process begins with the definition of product specifications. The most obvious requirements are that the product must function properly. ü ü Meet an expected level of performance Its cost should not exceed a given target Yes Prototype implementation Make corrections Yes In the case of large errors in testing, it is necessary to redesign the product and repeat all the steps. Testing Meets specifications? Yes No Minor errors? No When the prototype passes all the tests, then the product is deemed to be successfully designed and it can go into production. Finished product

13 Digital Hardware System A chip comprises a number of subcircuits, which are interconnected to build the complete circuit. Each of these subcircuits is a logic circuit, comprises a network of connected logic gates. Logic gates are built with transistors, implemented by fabricating various layers of material on a silicon chip.

14 Two design methodologies ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array designed all the way from behavioral description to physical layout designs must be sent for expensive and time consuming fabrication in semiconductor foundry no physical layout design;; design ends with a bitstream used to configure a device bought off the shelf and reconfigured by designers themselves

15 FPGA vs. ASIC

16 FPGA vs. ASIC ASICs High performance Low power High cost FPGAs Off-the-shelf Low development costs Short time to the market Reconfigurability

17 What is FPGA? Configurable Logic Blocks Block RAMs Block RAMs I/O Blocks Block RAMs

18 What is FPGA?

19 FPGA Design Process (1) Specification / Pseudocode On-paper hardware design (Block diagram & ASM chart) Library IEEE; use ieee.std _ lo g ic_ all; use ieee.std _ lo g ic_ u n sig n ed.all; entity RC5 _ core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: outstd_logic; ); end AES_core; VHDL description (Your Source Files) Functional simulation Synthesis Post-synthesis simulation

20 FPGA Design Process (2) Implementation Timing simulation Configuration On chip testing