EE586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu
Lecture 1 (Introduction) Why is designing digital ICs different today than it was before? Will it change in future?
The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17,470
ENIAC - The first electronic computer (1946)
The Transistor Revolution First transistor Bell Labs, 1948
The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola 1966
Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation
Intel Pentium (IV) microprocessor
Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months
Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 Electronics, April 19, 1965.
Evolution in Complexity
Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 10,000 1,000 100 10 8086 i486 Pentium i386 80286 Pentium III Pentium II Pentium Pro Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Courtesy, Intel Projected
Moore s law in Microprocessors Transistors (MT) 1000 100 10 1 0.1 2X growth in 1.96 years! 286 386 486 P6 Pentium proc 8085 8086 Transistors 0.01 on Lead Microprocessors double every 2 years 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Courtesy, Intel
Die Size Growth 100 Die size (mm) 10 8080 8008 4004 386 286 8086 8085 486 P6 Pentium proc ~7% growth per year ~2X growth in 10 years 1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore s Law Courtesy, Intel
Frequency Frequency (Mhz) 10000 1000 100 10 1 0.1 8085 8008 4004 8080 8086 Doubles every 2 years 286 386 P6 Pentium proc 486 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel
Power Dissipation 100 Power (Watts) 10 1 8085 8080 8008 4004 8086 286 386 486 P6 Pentium proc 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel
Power will be a major problem Power (Watts) 100000 10000 1000 100 10 1 0.1 286 8086 8085 386 486 8080 8008 4004 Pentium proc 18KW 5KW 1.5KW 500W 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel
Power density Power Density (W/cm2) 10000 1000 100 10 1 4004 8008 8080 8086 Rocket Nozzle Nuclear Reactor Hot Plate 8085 286 386 486 P6 Pentium proc 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Courtesy, Intel
Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 48M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments)
MOS Transistor Scaling (1974 to present) Scaling factor s=0.7 per node (0.5x per 2 nodes) Metal pitch Technology Node set by 1/2 pitch (interconnect) Poly width Gate length (transistor)
Ideal Technology Scaling (constant field) Quantity Before Scaling After Scaling Channel Length L L = L * s Channel Width W W = W * s Gate Oxide thickness t ox t ox = t ox * s Junction depth x j x j = x j * s Power Supply V dd V dd = Vdd * s Threshold Voltage V th V th = V th * s Doping Density, p n+ N A N D N A = N A / s N D = N D / s
Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them!
Productivity Trends 10,000,000 10,000 1,000,000 1,000 100,000 100 10,000 10 1,0001 100 0.1 0.01 10 Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000,000 100,000 10,000 1,0001 100 0.1 0.001 1 10 0.01 1981 1983 1985 1987 1989 1991 1993 Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo. 1995 1997 1999 2001 2003 2005 2007 2009 Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap
Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction
Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE n+ D
Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function
Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area
NRE Cost is Increasing
Die Cost Single die Wafer Going up to 12 (30cm) From http://www.amd.com
Cost per Transistor cost: -per-transistor 1 0.1 Fabrication capital cost per transistor (Moore s law) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
What about Interconnect Global wires Non-scalable delay Delay exceeds one clock cycle Non-scalable interconnects Excessive power dissipation Non reliability in signal transmission
Emerging Interconnect Technologies Three Dimensional Integration Optical Interconnects Wireless/RF Interconnects Lower Latency and Energy Dissipation
Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this course Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation
Course Structure MOS Transistors MOS Inverter Circuits Static MOS Gate Circuits High-Speed CMOS Logic Design Transfer Gate and Dynamic Logic Design Semiconductor Memory Design Advanced Devices beyond CMOS
Course Structure Extensive use of CAD tools Homework assignments One to two midterm exams and one final exam Course Project
Suite of two courses EE 466/586 and EE587 will cover various aspects starting from circuits to systems
References Textbook: CMOS VLSI Design, Weste and Harris, Fourth Edition Additional Reference: Analysis and Design of Digital Integrated Circuits - In Deep Submicron Technology, Hodges, Jackson and Saleh, McGraw-Hill, Third Edition, 2004. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective. Second Edition, Prentice Hall, 2003. Important announcements will be posted in the course website www.eecs.wsu.edu/~ee586