Lecture #1. Teach you how to make sure your circuit works Do you want your transistor to be the one that screws up a 1 billion transistor chip?

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1 Instructor: Jan Rabaey EECS141 1 Introduction to digital integrated circuit design engineering Will describe models and key concepts needed to be a good digital IC designer Models allow us to reason about circuit behavior Allow analysis and optimization of the circuit s performance, power, cost, etc. Understanding circuit behavior is key to making sure it will actually work Teach you how to make sure your circuit works Do you want your transistor to be the one that screws up a 1 billion transistor chip? EECS

2 CMOS devices and manufacturing technology CMOS gates Combinational and sequential circuits Arithmetic building blocks Interconnect Memories Propagation delay, noise margins, power Timing and clocking Design methodologies EECS141 3 Understanding, designing, and optimizing digital circuits for various quality metrics: Performance (speed) Power dissipation Cost Reliability EECS

3 Instructor Prof. Jan Rabaey 563 Cory Hall, , Office hours: We 3:30pm-5:00pm TAs: David Chen, (OH: Th am) Tsung-Te Liu, (OH: Th. 1-2pm) Reader: Shinwon Kang, Web page: EECS141 5 Discussion sessions Th 4-5pm, Tsung-Te (400 Cory) Fr 9-10am, David (293 Cory) Same material in all sessions! Labs (353 Cory) M 1-4pm Tu 11am-2pm Please choose one lab session and stick with it! EECS

4 M Lab1 (David) 353 Cory T W Lab2 (Tsung-Te) 353 Cory Lec (Jan) 203 McLaughlin Office Hours (Jan) 563 Cory R Office Hours (David) F DISC2 (David) 293 Cory Office Hours (Tsung-Te) Lec (Jan) 203 McLaughlin DISC1 (Tsung-Te) 400 Cory Problem Sets Due EECS Assignments One design project (with a few phases) Labs: 5 software 2 midterms, 1 final Midterm 1: Fr Febr 18, evening (TBD) Midterm 2: We April 15, evening (TBD) Final: Fr. May 15, 5-8pm (TBD) EECS

5 Please use the newsgroup for asking questions (news://news.csua.berkeley.edu/ucb.class.ee141) Can work together on homework But you must turn in your own solution Lab reports due 1 week after the lab session Project is done in pairs No late assignments Solutions available shortly after due date/time Don t even think about cheating! Use the Microphone!!! EECS141 9 Homeworks: 10% Labs: 10% Projects: 20% Midterms: 30% Final: 30% EECS

6 Textbook: Digital Integrated Circuits A Design Perspective, 2 nd ed, by J. Rabaey, A. Chandrakasan, B. Nikolic Class notes: Web page Lab Reader: Web page Check web page for the availability of tools EECS The sole source of information Class and lecture notes Assignments and solutions Lab and project information Exams Many other goodies Print only what you need: Save a tree! EECS

7 Cadence Widely used in industry Online tutorials and documentation HSPICE and Spectre for simulation EECS Assignment 1: Getting SPICE to work see web-page Due next Friday, January 30, 5pm NO discussion sessions or labs this week. First discussion sessions in Week 2 First software lab in Week 3 EECS

8 Digital Integrated Circuit Design: The Past, The Present and The Future What made Digital IC design what it is today Why is designing digital ICs different today than it was before? Will it change in the future? EECS The Babbage Difference Engine 25,000 parts cost: 17,470 EECS

9 EECS First transistor Bell Labs, 1948 EECS

10 Bipolar logic 1960 s ECL 3-input Gate Motorola 1966 EECS Intel, ,300 transistors (12mm 2 ) 740 KHz operation (10µm PMOS technology) EECS

11 Intel, ,000,000 transistors (112mm2) 3.8 GHz operation (90nm CMOS technology) EECS Intel, ,000,000 transistors (143mm2) 3 GHz operation (65nm CMOS technology) EECS

12 Transistor Counts in Intel's Microprocessors 100 Pentium 4 Itanium II Core2 Transistors [in millions] DX DX Pentium Pro Pentium Pentium II 486DX4 Pentium MMX Itanium Pentium III Doubles every 2 years EECS In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months EECS

13 Electronics, April 19, EECS EECS

14 Frequency Trends in Intel's Microprocessors Frequency [MHz] DX 386DX Pentium II Pentium Pro Pentium 486DX4 Pentium III Pentium MMX Pentium 4 Itanium Has been doubling every 2 years, but is now slowing down EECS Core2 Itanium II Power (Watts) Pentium proc 18KW 5KW 1.5KW 500W Year Did this really happen? Courtesy, Intel EECS

15 Power Trends in Intel's Microprocessors Power [W] Has been > doubling every 2 years 486DX 386DX Pentium Pro Pentium Itanium Pentium III Pentium II Itanium II Has to stay ~constant EECS Pentium 4 Core 2 Power Density (W/cm2) Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Hot Plate P6 Pentium proc Year Power density too high for cost-effective cooling S. Borkar EECS

16 *Pictures from EECS Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction EECS

17 Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) EECS DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? 1/DSM Macroscopic Issues Complexity Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! EECS

18 10,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity Logic Transistor per Chip (M) 2007 Productivity (K) Trans./Staff - Mo Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap EECS SYSTEM MODULE GATE CIRCUIT S n G DEVICE n D EECS

19 Introduce basic metrics for design of integrated circuits how to measure cost, delay, power, etc. EECS