ECE 637 Integrated VLSI Circuits Introduction EE141 1 Introduction
Course Details Instructor Mohab Anis; manis@vlsi.uwaterloo.ca Text Digital Integrated Circuits, Jan Rabaey, Prentice Hall, 2 nd edition Grading Project 35%, Presentation 15%, Final 50% EE141 2 Introduction
Course Outline Introduction this lecture (1) Diode (3) Static behavior; Parasitic capacitances and dynamic behavior; Secondary effects & SPICE model MOS Transistor (6) Static behavior; Parasitic capacitances and dynamic behavior; Short channel effects; scaling; SPICE MOS models; Process variations & process impact MOS Inverter (7) Properties; Static behavior; Dynamic behavior; Power, energy consumption and power-delay, energy-delay products; Layout considerations/design rules EE141 3 Introduction
Course Outline (Contd.) Combinational Circuits (8) Implementation styles - static, ratioed, pass transistor; CPL, dynamic logic ; Signal integrity issues in dynamic circuits; Cascading dynamic circuits; Low power, high performance circuits Sequential Circuits (6) Timing metrics for sequential circuits; Static and dynamic flip-flops and latches; High speed pipeline circuits Arithmetic Circuits (6) Adder, circuits and architectures EE141 4 Introduction
Project Topics Design of a high performance 16-b adder 64-b priority encoder Project requirements Individual effort All project must involve circuit design, transistor sizing, simulations EE141 5 Introduction
Project (Contd.) Deadlines 1 page proposal that states: objectives, project outline, milestones, workload distribution (week 3) 2 page progress report (week 8) <20 pages project report (week 13); single report per project EE141 6 Introduction
What will you learn? Understanding, designing, and optimizing digital circuits in the deep-submicron regime with respect to different quality metrics: cost, speed, power dissipation, and reliability
Introduction Why is designing digital ICs different today than it was before? Will it change in future?
Intel 4004 Micro-Processor (1971) 1971 1000 transistors 1 MHz operation NMOS only replacing PMOS based integrated circuits (higher speed)
Intel Pentium (IV) microprocessor (2000) In the early 1970s, CMOS technology replaced NMOS-only logic which started suffering from high power consumption. Ever since, CMOS has been the dominant digital technology. Interestingly enough, power consumption concerns are rapidly becoming dominant in CMOS designs as well, and this time there does not seem to be a new technology around the corner to alleviate this problem.
Issues in Digital IC Design - Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months (# of transistors that can be integrated on a single die would grow exponentially with time). 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 19, 1965.
Transistor Counts An intriguing case study is offered by the microprocessor. From its inception in the early seventies, the microprocessor has grown in performance and complexity at a steady and predictable pace. The number of transistors and the clock frequency for a number of landmark designs are collected in Figure 1.3. The million-transistor/chip barrier was crossed in the late eighties. Clock frequencies double every three years and have reached Transistors (MT) 1000 100 10 1 2X growth in 1.96 years! 486 Courtesy, Intel P6 Pentium proc 0.1 286 386 8085 8086 0.01 4004 8008 0.001 1970 1980 1990 2000 2010 Year Transistors on Lead Microprocessors double every 2 years
Die Size Growth 100 Die size (mm) 10 8080 8085 8008 4004 8086 286386 486 P6 Pentium proc ~7% growth per year ~2X growth in 10 years 1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore s Law Courtesy, Intel
Frequency Clock frequencies doubled every 3 years in the past decade and have reached the GHz range. Frequency (Mhz) 10000 1000 Doubles every 2 years 100 P6 Pentium proc 486 10 8085 286 386 8086 1 8080 8008 0.1 4004 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years This trend has not shown any signs of a slowdown. Courtesy, Intel
Impact on Design => Hierarchical approach Custom/Handcrafted This revolution has had a profound impact on how digital circuits are designed. Early designs were truly hand-crafted. Every transistor was laid out and optimized individually and carefully fitted into its environment, for example the design of the Intel 4004 microprocessor. This approach is, obviously, not appropriate when more than a million devices have to be created and assembled. With the rapid evolution of the design technology, time-to-market is one of the crucial factors in the ultimate success of a component. Hierarchical Designers have, therefore, increasingly adhered to rigid design methodologies and strategies that are more amenable to design automation. The impact of this approach is apparent from the layout of one of the later Intel microprocessors, the Pentium IV. Instead of the individualized approach of the earlier designs, a circuit is constructed in a hierarchical way: a processor is a collection of modules, each of which consists of a number of cells on its own. Cells are reused as much as possible to reduce the design effort and to enhance the chances for a first-time-right implementation. The fact that this hierarchical approach is at all possible is the key ingredient for the success of digital circuit design and also explains why, for instance, very large scale analog design has never caught on.
Design Abstraction Levels Question: Why hierarchal design approach is feasible in digital world and not in analog designs? Answer: Abstraction! At each design level, the internal details of a complex module can be abstracted away and replaced by a black box view or model. This model contains virtually all the information needed to deal with the block at the next level of hierarchy. For instance, once a designer has implemented a multiplier module, its performance can be defined very accurately and can be captured in a model. The performance of this multiplier is in general only marginally influenced by the way it is utilized in a larger system. For all purposes, it can hence be considered a black box with known characteristics. As there exists no compelling need for the system designer to look inside this box, design complexity is substantially reduced. (Analogous to to a library of software routines) + SYSTEM MODULE GATE Cell libraries: contain complete documentation and characterization of the behavior of the cells. Typically stacked in rows and interconnected by routing channels. This abstraction facilitated the design of Computer-aided frameworks for digital ICs S n+ G CIRCUIT DEVICE D n+
Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function Depending on the application, more significance is given to one design criterion over another.
Power Dissipation 100 Power (Watts) 10 1 8085 8080 8008 4004 8086 286 386 486 P6 Pentium proc 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel
Power will be a major problem Power (Watts) 100000 10000 1000 100 10 1 0.1 8085 8086286 386 486 4004 80088080 Pentium proc 18KW 5KW 1.5KW 500W 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel
Power density Power Density (W/cm2) 10000 1000 100 10 1 4004 8008 8080 8086 Rocket Nozzle Nuclear Reactor Hot Plate 8085 286 386 486 P6 Pentium proc 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Courtesy, Intel
Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 48M 86M 162M 260M 435M Power Management Analog Baseband (data from Texas Instruments) Digital Baseband (DSP + MCU)
Challenges in Digital Design Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them!
Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this course Understanding the design metrics that govern digital design is crucial Reliability, speed, power and energy dissipation