Enabling MIPI Physical Layer Test

Enabling MIPI Physical Layer Test High Speed Test and Characterization High Speed Digital Test

The Explosion of Functions within Mobile Devices Multiple RF functions GPS Bluetooth WCDMA GSM WLAN FM Multiple Peripherals Camera Display Audio in /out Mobile TV DVB-H Other IOs Request for more bandwidth High speed serialization Digitization of IQ Power Management Page 2

Emergence of Standard Digital Interconnects From Analog to Digital The Digital Interface Is easier and cheaper to implement Will consume less battery power Provides higher bandwidth Reduces the number of IC pins Allows for easier plug and play between devices BUT Breaking the GBit barrier requires dedicated jitter stress test on clock and data separately Power safe requires wake up and therefore different signal extremes, low power and high speed Wireless Domain Digital Domain MIPI DPHY CSI MIPI DPHY DSI RF IC DigRF BB IC AP Wireless Handset Mobile Industry specific standards LTE WiMAX Standards inherited from the computer industry Page 3

Agilent Solution Offering Digital Domain Wireless Domain Wireless Protocol Layer Validation Wireless Physical Layer Validation Digital Protocol Layer Debug / Validation Digital Physical Layer Debug / Validation Protocol Viewer Pulse Function Arbitrary Noise Generator BERT Dig RF tester Wide Band Oscilloscope Page 4

The MIPI Evolution Test & Debug Port Physical layers Protocol layers Status BB-IC debug ports Shared pins DigRF v3 MIPI DPhy DigRF v3 DSI Display - Shipping today - In development CSI Camera Unipro Other - DPhy is in definition, almost final - Physical layer solution volume Shipment Oct 08 MIPI MPhy DigRF v4 - MPhy definition to start end of the year - DPhy Solution also requires Logic Analyzer. Minor adaptations to configuration are possible because standard is not defined yet! Page 5

How to Get Confidence on the Physical Layer Characterizing the Parameters TX Tests: Data bus timing Transition times Timing Levels Signal Integrity DC levels and AC swing Low Power / High Speed mode switching Jitter RX 2.5G 3GPP RX Tests: Data bus timing Min. pulsewidth TX MIPI D-Phy DSI MIPI D-Phy CSI TX BB-IC TX RX RX DigRF v3 MIPI D-Phy TXRF-IC RX WiMAX Sensitivity (min/max amplitude) Jitter Tolerance on Clock and Data Camera Differential and common mode, termination switching Page 6

Enabling MIPI D-PHY Physical Layer Test Control the transition MIPI D-PHY operates in two modes with dynamic transitions Low Power Signaling High Speed Signal Low Power Signaling Low Power Signal - Max 20 Mbit -Single ended - CMOS High Speed Signal - > 1 Gbit -Differential -LVDS The ParBERT 81250A - Generates the signal you need - Controls the sequences - Forces the bus through low to high speed transition and vice versa - Glitch free change of timing parameters High Speed Digital Test

Enabling Physical Layer Test Bit Error Testing Stress your device to its limits RX Tests: Sensitivity and jitter tolerance on clock and data Stress Generator Solution RX Device Under Test Expected Data Compare Data Analyzer Error Detector Bit Error Ratio - For several lanes at least 2 data and clock - Devices show immunity at combined jitter testing; data and clock needs to be tested independently - For all kinds of jitter and stress test - Jitter injection from 81150A via delay line to the ParBERT 81250A High Speed Digital Test

Enabling MIPI D-PHY Physical Layer Test Characterization at your fingertips Next Level of Performance and Convenience through Test Automation N5990A Test Automation Software and MIPI Frame Generator One button Rx and Tx compliance tests and characterization MIPI D-PHY Editor Pre-canned test pattern Calibrated test cases Easy post processing SQL data base interface Interaction with legacy code Page 9 July 3, 2008

The Stimulus Test Setup Full coverage of stimulus signal generation with flexible signal conditioning Full Stress / Jitter tolerance testing Modular configuration for 1, 2 or multiple lanes Test Automation Software with MIPI Editor and pre-canned test pattern Multi-application support by ParBERT platform (e.g. HDMI) Depending on device design, full BER Analysis possible Economic High speed Tester 3.35 Gbit/s 81150A Noise / Jitter source Multi Application Tester 7 Gbit/s E4438C Signal Generator / clock source 81150A Noise / Jitter source 81250A ParBERT 81250A ParBERT N5990A Test Automation Software N5990A Test Automation Software High Speed Digital Test

Agilent MIPI D-PHY Physical Layer Test High Speed From nominal to stress test Transition between LP and HS is critical Agilent 81250A ParBERT Agilent 81150A Noise Source N5990A Test Automation Software Generate the signal you need Control and synchronize transitions between different modes and channels Ease-of-use through test automation Multiple Lanes with separate Clock and Data Low Power Signaling High Speed Signal Low Power Signaling High Speed Digital Test

Appendix Test Details Page 12

Design For Testability Display RX MIPI D-Phy DSI MIPI D-Phy CSI TX BB-IC RX TX RX MIPI D-Phy MIPI M-Phy TX RX RF-IC TX Camera Provide Access Point and Method by Design / Standardization Page 13

Recommended ParBERT MIPI D-PHY Configurations Configurations vary in max data rate and jitter injection capabilities: 3.35 GBit/s economic with 500 ps jitter injection capability The maximum data rate of 3.35 GBit/s limits the usage of ParBERT modules for other standards respectively applications 7 GBit/s multi-application setup With 7GBit/s ParBERT modules the setup can support a wider range of standards and applications Page 14 July 3, 2008

Jitter Injection Capabilities of ParBERT Configurations Separate jitter on clock and data lanes Jitter capabilities Externally jittered ParBERT clock Economic Solution Possible setup suggests clean clock lane and jitter on data lanes only 500ps delay line Not possible Multi-application solution Possible setup suggests clean clock lane and jitter on data lanes only 200ps delay line plus jittered ParBERT clock (see below) UI 78 7.15 Data rate dependent example at 1 GBit/s.4 4 40 MHz Max supported jitter Data Clock 500ps 500ps (capability not used in setup) Jittered Clock + 200ps Jittered Clock + 200ps (capability not used in setup) Page 15 July 3, 2008

Noise Generation Capability of ParBERT Configurations Same for economic and multiple application setups Suggest to test either noise or jitter at one time use the same equipment for both and change setup (parallel test would require more accessories) Perform noise test only on one lane at a time in a setup with mutliple data lanes this means to test all lanes sequentially and change setup in-between (parallel test would require more accessories) Page 16 July 3, 2008

Economic ParBERT 3.35 GBit/s System Configuration Single Lane Shown 675M 675M Generator Generator internal channel add Data Out Noise Generation 11636B Pwr Divider 8493C 6dB 1250-1159 Adapter 11636B Pwr Divider Trigger Out LP Signal Generation 11636B Pwr Divider 8493C 6dB 675M 675M Generator Generator internal channel add Data Out 1250-2015 Adapter 15438A 2ns Transition Time Converter 15438A 2ns Transition Time Converter Scope Trigger 11636B Pwr Divider Start In Data Out 15432B 250ps Transition Time Converter 11667B Pwr Splitter 11667B Pwr Splitter HS Signal Generation 3.35G Generator + D-Phy - Clock or Data Lane 3.35G Generator 15432B 250ps Transition Time Converter Data Out all SMA cables 15442-61601 Delay Control In Lane 1 11636B Pwr Divider 1250-1159 Adapter Lane 1 Lane 2 11636B Pwr Divider Lane 2 81150A opt 002 Lane 3 11636B Pwr Divider 1250-2015 Adapter Lane 3 Jitter Generation (4 lanes shown) Lane 4 11636B Pwr Divider 11636B Pwr Divider Lane 4 11636B Pwr Divider 81150A opt 002 81150A opt 002 Page 17 July 3, 2008

Economic ParBERT 3.35 GBit/s System Summary 1 clock 1 data lane 1 clock 2 data lanes 1 clock 4 data lanes Comments Signal Generation 4x 675MBit/s generators 1x E4832A with 4x E4838A 2 3 5 LP signaling and HS offset 2x 3.35GBit/s generators 1x E4861B with 2x E4862B 2 3 5 HS signaling 250ps transition time converter 15432B 4 6 10 HS transition time 2ns transition time converter 15438A 4 6 10 LP transition time, 3rd part product power splitter 11667B 4 6 10 combine HS and LP signals set of 4 SMA cables 15442-61601 3 5 (2 cables not used) 8 (2 cables not used) signal connect Other ParBERT Items clock module E4808A 1 1 1 HS clock clock module E4805B 1 1 1 LP clock ParBERT mainframe 81250A-149 1 1 1 IEEE 1394 PC link to VXI 81250A-013 1 1 1 ParBERT 81250 software license E4875A 1 1 1 software Laptop including PCMCIA IEEE 1394 card 81250A-015 1 1 1 PC to operate the setup power divider 11636B 1 1 1 split LP trigger out to HS and scope set of 4 SMA cables 15442-61601 1 (1 cable not used) 1 (1 cable not used) 1 (1 cable not used) trigger signals Jitter Generation 81150A with two channels 81150A, option 002 1 1 2 noise generator BNC to SMA adapter 1250-2015 1 1 2 81150 output adapter SMA to SMA adapter 1250-1159 0 2 4 connect power dividers power divider 11636B 1 3 6 split noise to ParBERT delay lines set of 4 SMA cables 15442-61601 1 (1 cable not used) 2 (3 cables not used) 3 (2 cables not used) Noise Generation (one lane - use equipment for jitter generation) power divider 11636B 2 0 0 re-use power divider for jitter generation 6dB attenuator 8493C 2 2 2 SMA to SMA adapter 1250-1159 2 0 0 re-use adapter for jitter generation BNC to SMA adapter 1250-2015 0 0 0 re-use adapter for jitter generation set of 4 SMA cables 15442-61601 0 0 0 re-use cables for jitter generation Other 9GHz or better DSO 90000 Scope options t.b.d 1 1 1 differential probe 1169A 2 2 2 timing and level measurement with DSO differential probe head 5380A 2 2 2 timing and level measurement with DSO high impedance probe head t.b.d 2 2 2 level measurement with DSO Control Software and Test Automation N5990A option t.b.d 1 1 1 control software LAN hub no Agilent part 1 1 1 remote control instruments LAN cable no Agilent part 3 3 4 remote control instruments set of 4 SMA cables 15442-61601 1 (2 cables not used) 1 (2 cables not used) 1 (2 cables not used) to connect scope set of 4 SMA cables 15442-61601 -1-2 -1 balance unused SMA cables Page 18 July 3, 2008

Multi Application ParBERT 7 GBit/s System Configuration Single Lane Shown Clock In Start In Trigger Out Clock In Start In Clock In HS Clock System 7G Generator 7G Generator to D-Phy Clock Lane (LP clock generation not shown) Noise Generation Scope Trigger 11636B Pwr Divider 8493C 6dB 675M Generator 1250-1159 Adapter 11636B Pwr Divider LP Clock and Data System 675M Generator internal channel add Data Out 1250-1159 Adapter 11636B Pwr Divider 11636B Pwr Divider 11636B Pwr Divider 8493C 6dB 675M Generator 675M Generator internal channel add Data Out 1250-2015 Adapter 15438A 2ns Transition Time Converter 15438A 2ns Transition Time Converter 81150A opt 002 1250-1743 Adapter 8120-1839 BNC cable clean clock clock w SJ ESG 1 ESG 2 10 MHz 11636B Pwr Divider 7G Generator Data Out 15432B 250ps Transition Time Converter 11667B Pwr Splitter 11667B Pwr Splitter HS Data System + D-Phy - Clock or Data Lane 7G Generator Data Out 15432B 250ps Transition Time Converter Delay Control In 1250-1744 Adapter Lane 2 Lane 4 Lane 1 Lane 3 11636B 11636B Pwr Pwr Divider Divider 11636B 11636B Pwr Pwr Divider Divider 11636B 11636B 1250-1159 Pwr Pwr Divider Divider Adapter 1250-2015 Adapter 81150A opt 002 Random Jitter Generation (4 lanes shown) Page 19 July 3, 2008

Multi Application 7GBit/s System Summary Page 20 1 clock, 1 data lane 1 clock, 2 data lanes 1 clock, 4 data lanes Comments Signal Generation 4x 675MBit/s generators 1x E4832A with 4x E4838A 2 3 5 LP signaling and HS offset 7GBit/s generator N4874B 4 6 10 HS signaling 250ps transition time converter 15432B 4 6 10 HS transition time 2ns transition time converter 15438A 4 6 10 LP transition time, 3rd part product power splitter 11667B 4 6 10 combine HS and LP signals adapter 3.5mm(f) to 2.4mm(m) N4911A-002 8 12 20 2.4mm 50 Ohm termination N4912A 8 12 20 terminate unused outputs of 7G ParBERT 3.5mm 50 Ohm termination 1250-2206 4 6 10 terminate unused outputs of 7G ParBERT set of 4 SMA cables 15442-61601 3 5 (2 cables not used) 8 (2 cables not used) signal connect Other ParBERT Items clock module E4809A 2 2 2 HS clock clock module E4805B 1 1 1 LS clock ParBERT mainframe 81250A-149 1 1 1 IEEE 1394 PC link to VXI 81250A-013 1 1 1 ParBERT extender mainframe with IEEE1394 link 81250A-152 0 1 1 ParBERT 81250 software license E4875A 1 1 1 Laptop including PCMCIA IEEE 1394 card 81250A-015 1 1 1 PC to operate the setup BNC cable 8120-1839 1 1 1 synchronize ESGs power divider 11636B 3 3 3 clock and triggering ESG E4438C, options 1E5, 506, 601 2 2 2 signal generators adapter n to 3.5mm (m) 1250-1743 1 1 1 ESG output to power divider adapter n to 3.5mm (f) 1250-1744 1 1 1 ESG output to SMA cable SMA to SMA adapter 1250-1159 1 1 1 combine power splitters for triggering set of 4 SMA cables 15442-61601 2 (1 cable not used) 2 (1 cable not used) 2 (1 cable not used) Jitter Generation 81150A with two channels 81150A, option 002 1 1 1 noise generator BNC to SMA adapter 1250-2015 1 2 2 81150 output adapter SMA to SMA adapter 1250-1159 0 0 4 connect power dividers power divider 11636B 1 2 6 split noise to ParBERT delay lines set of 4 SMA cables 15442-61601 1 (1 cable not used) 2 (2 cables not used) 3 (2 cables not used) 1, 2 or 4 needed to distribute noise Noise Generation (one lane - use equipment for jitter generation) power divider 11636B 2 0 0 re-use power divider for jitter generation 6dB attenuator 8493C 2 2 2 SMA to SMA adapter 1250-1159 2 0 0 re-use adapter for jitter generation BNC to SMA adapter 1250-2015 0 0 0 re-use adapter for jitter generation set of 4 SMA cables 15442-61601 0 0 0 re-use cables for jitter generation Other 9GHz or better DSO 90000 Scope options t.b.d 1 1 1 differential probe 1169A 2 2 2 timing and level measurement with DSO differential probe head 5380A 2 2 2 timing and level measurement with DSO high impedance probe head t.b.d 2 2 2 level measurement with DSO Control Software and Test Automation N5990A option t.b.d 1 1 1 LAN hub no Agilent part 1 1 1 remote control instruments LAN cable no Agilent part 5 5 5 remote control instruments set of 4 SMA cables 15442-61601 1 (2 cables not used) 1 (2 cables not used) 1 (2 cables not used) clock to data skew measurement with DSO set of 4 SMA cables 15442-61601 -1-1 -1 balance unused SMA cables July 3, 2008

Combined D-PHY High Speed And Low Power Signal Generated by ParBERT Page 21

Transition Details: High Speed Signaling to Low Power Signaling Page 22

Voltage Levels as defined 1300mV 1300mV 1100mV 880mV 880mV 550mV 550mV 450mV 460mV 330mV 200mV 70mV 50mV -50mV -40mV max Differential input high threshold V IDTH = 70mV min Differential input low threshold V IDTL =-70mV Page 23

MIPI D-PHY Application Programming Tool for simple editing of data rate, pattern, timing and levels Page 24

How Does D-Phy Compliance Test Work MIPI Standard Workgroup (key industry players, including Agilent, lead the effort) defines Base Specification work with industry leaders subcontract University of New Hampshire Interoperability Lab (UNH-IOL) loan equipment for CTS developement Agilent (LPT, DVD, HSDT) owner defines defines CTS is based on main specification Compliance Test Specification (CTS) MOI is based on CTS Method of Implementation (MOI) generic test description how to do test with specific instrument Protocol tester Scopes BERTs Page 25

Enabling MIPI D-PHY Physical Layer Test Characterization at your fingertips Next Level of Performance and Convenience through Test Automation N5990A Test Automation Software and MIPI Frame Generator One button Rx and Tx compliance tests and characterization MIPI D-PHY Editor Pre-canned test pattern Calibrated test cases Easy post processing SQL data base interface Interaction with legacy code Page 26 July 3, 2008

ParBERT System Configuration Timing and Trigger, based on 7 Gb/s data modules 10 MHz ESG 1 ESG 2 Clock (clean) Clock (SJ) ParBERT Clock System ParBERT HS Data System ParBERT LP Data System Start In Start In Trigger Out To Scope Trigger 1 BNC cable for 10 MHz synchronization 4 SMA cables for clock distribution + 1 power divider 5 SMA cables for trigger distribution + 2 power dividers Page 27

ParBERT System Configuration High Speed Jitter Distribution, based on 7 GBit/s data modules ARB Power Divider To Delay Control Inputs ParBERT Clock System ParBERT HS Data System ParBERT LP Data System 1 BNC-to-SMA adapter 7 SMA cables 3 power dividers Page 28

Enabling MIPI D-PHY Physical Layer Test High Speed Test and Characterization with Agilent 81250A ParBERT Agilent 81150A Pulse Function Arbitrary Noise Generator Agilent N5990A Test Automation Platform 3 Reasons to go with 81250A: 81150A Noise Source - 1. Full coverage of stimulus signal with flexible & modular signal & stress generation 2.Easy-to-use MIPI D-Phy Editor and Test Automation including pre-canned test pattern 3.Depending on device design, full BER analysis possible High Speed Digital Test

MIPI Test Software N5990A Test Automation and MIPI Frame Generator Features and Pattern Page 30 Enabling MIPI Physical Agilent Layer Restricted Test July July, 3, 2008

Overview MIPI Frame Generator N5990A-362 Manual Test Tool for MIPI Receiver Testing using the 81250A as a generic MIPI Stimulus Page 31 July 3, 2008

Features Included: Automatically setting up the 81200A for generating MIPI conformance signals and pattern Modify HS and LP pattern Modify Data Rates of HS and LP transmission Modify Timing between LP and HS data transfer switching Modify Voltage Levels Adding Jitter to HS data Not included: Measure and analyze bit error ratio Generate complete video frames for testing displays Switching between Receiver and Transmitter mode PPI capability for DUT control Page 32 July 3, 2008

Pattern Capabilites (beta)= already available in beta version end of March (final)= will be part of the final version Pure LP pattern transmission (beta) Pure HS pattern transmission (beta) Predefined pattern (high transition density, low transition density, lonely 0/1 bit, PRBS) (beta) Integrated protocol layer for LP-HS-LP transmission with variable timing (beta) LP Triggers (Table 8 MIPI Spec): Low-Power Data Transmission, Ultra-Low Power State, Reset-Trigger (final) Programmable Escape Mode State Machine (final) User-defined pattern for LP and HS data separately (transmission switch protocol will be automatically added by the software) Integrated 8/9 bit coding Page 33 July 3, 2008

Overview N5990A Test Automation Software Full test automation (Rx, Tx, Rx test system calibration) Generic, common N5990A user interface On- button compliance tests and expert mode for characterization, debugging and margin test Open, modular software platform N5990A-010, -160, -260, -361 (-001 and -500 recommended) Page 34 July 3, 2008

ParBERT 81250A System Configuration Jitter Injection Capabilities (1) Economic solution (based on 3.4 Gb/s generator) 500 ps delay line, 200 MHz bandwidth All jitter types as available from 81150A (RJ, SJ, custom) Multi application solution (based on 7 Gb/s generator) 200 ps delay line + SJ from ESG Delay line can create any jitter type as available from 81150A Page 35

Generated Pattern All measurements done into 50 Ohms Low-power = 10MHz, high-speed = 1GHz Page 36

D-Phy Timing MIN: 50ns MIN: 40ns+4*UI MAX: 85ns+6*UI MIN: 145ns+10*UI- T HS-Prepare 1GB/s: UI=1ns HS-PREPARE: MIN: 44ns MAX: 91ns HS-ZERO: MIN: 64ns = 145ns+10*1ns-91ns MAX: 35ns MAX: 35ns+4*UI Wide range of flexibility MAX: 105ns+n*12*UI MIN: max{n*8*ui, 60ns+n*4*UI} MIN: 40ns MAX: 55ns+4*UI n=1 forward direction HS mode n=4 backward direction HS mode UI: 1GB/s = 1ns MIN: 100ns Page 37

T HS-Prepare Page 38

T HS-Zero Page 39

T HS-Trail Page 40

Voltage Levels 1300mV 1300mV 1100mV 880mV 880mV 550mV 450mV 550mV 460mV 330mV 200mV 50mV -50mV 70mV -40mV max Differential input high threshold V IDTH = 70mV min Differential input low threshold V IDTL =-70mV Page 41

V OH-Max >1.2V with 3dB Attenuators Page 42

High Speed Offset Example 1: 47mV Page 43

High Speed Offset Example 2: 198mV Page 44

Transition Details: Low Power Signaling to High Speed Signaling Page 45

Transition Details: High Speed Signaling to Low Power Signaling Page 46

High Speed Signal Details Page 47

Spikes During Low Power Mode MAX: 300 V*ps MIN: 2*50ns MIN: 20ns MIN: 880mV MAX: 550mV 300V*ps: 0.9V 333ps 1V 300ps 1.5V 200ps 2V 150ps Do complete low speed pattern including spikes with high-speed generator Max spike level: 1.8V (single ended) Spike and low speed data at same amplitude Page 48

Signal With Spikes Page 49

1.8V 1 -Spike Page 50

1.8V 0 -Spike Page 51