Serial ATA Gen2 Jitter Tolerance Testing
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1 Serial ATA Gen2 Jitter Tolerance Testing Abstract Guy Foster SyntheSys Research, Inc. February 21, 2006 SR-TN054 Serial ATA [i] is an increasingly common serial bus technology aimed at disk drive applications. Electrical receivers are required to pass a test of their jitter tolerance using a stressed eye. This paper gives context to the requirements, and describes the construction of a compliant stressed eye signal. Agenda Introduction...2 Gen2 Jitter Tolerance Testing...5 Practical Construction of the Stressed Eye Signal...6 Sinusoidal Interference...8 ISI Board vs. Filter...8 PC Power Supply...8 Test Setups...9 Summary...10 Acknowledgment...10 References...10
2 2 Introduction A common theme in computer-related communications is the move from parallel multi-lane buses to higher speed serial buses. These provide faster throughput and easier routing than their predecessors. Examples of the new generation computer buses include Serial ATA (disk drives), PCI Express (graphics cards) and Fully Buffered DIMM (faster RAM memory). A cost of this changeover is the speed of an individual lane is now such that microwave effects must be taken into consideration for successful design. Serial ATA is aimed at storage. It has had a close association with another related standard, Serial Attached SCSI (SAS). A summary of selected characteristics from the standard is given in Table 1. An example hard drive with short distance ( i specification) capability at 1.5 Gb/s ( Gen1) and 3 Gb/s ( Gen2 ) is shown in Figure 1. In Figure 2, a short range i connector is shown, alongside a test fixture [ii] which was used for connection to our drive under test. Designation Bit Rate Distance Application Description based on Standard Example Application Diagrams Gen2i Gen1i 3.0 Gb/s 1.5 Gb/s Shortest PC Mother board to device Generation 1 Electrical Specifications: These are the 1.5 Gb/s electrical specifications previously released in Serial ATA 1.0a for PC motherboard to device applications. Generation 2 Electrical Specifications: These are 3.0 Gb/s electrical specifications aimed at PC motherboard to device applications. Gen2m Gen1m 3.0 Gb/s 1.5 Gb/s Medium Short backplane and external device. Like "i" application, except longer distance so more transmit amplitude and higher receiver sensitivity Generation 1 (2) Electrical Specifications for Short Backplane and External Desktop Applications: These are the 1.5 Gb/s (3Gb/s) electrical specifications previously released in Serial ATA II: Extensions to Serial ATA 1.0 aimed at short 1.5 Gb/s (3 Gb/s) internal backplane applications and the Single-Lane Desktop Cable application. These include only modified Transmitter and Receiver Differential Swing specifications. All other electrical specifications relating to Gen1m (2m) compliance points are identical to Gen1i (2i) specifications. This specification is for these limited applications only and is not intended for any other system topology. Table 1: Summary of Serial ATA descriptions from reference [i] (Continued on next page)
3 3 Gen1x Gen2x 1.5 Gb/s 3.0 Gb/s Longest Extended length - long backplanes and system to system Extended Length 1.5 Gb/s(3Gb/s) Electrical Specification or Gen1x ( 2x ): These electrical specifications are aimed at 1.5 Gb/s (3Gb/s) links in "long" backplanes and system-to-system applications. These specifications are based upon Serial Attached SCSI Electrical specifications (CT/CR specifications as called out in SAS). Table 1: Summary of Serial ATA descriptions from reference [i] Figure 1: A Serial ATA Gen2i disk drive with the high speed Serial ATA connector highlighted.
4 4 Figure 2: Test fixture showing Serial ATA cable and connections to test equipment.
5 5 Gen2 Jitter Tolerance Testing A test procedure for the construction of, and test with, the jitter tolerance signal is shown in Table 2, below. Gen 2i 2m 2x Notes Connection of ISI board? Optional (one method to generate DJ and slow rise time) Optional (one method to generate DJ and slow rise time) Required Clock Divide Ratio Compliant channel with 3.9dB more loss at 1.5 GHz than at 300 MHz 1. Set Initial Amplitude 750mVpp 750mVpp 1600mVpp Differential, maximum amplitude. V diffrx, Table 24, page Set pattern to Check that test source 20-80% rise/fall times are Transition time converter may be within range ps used to generate additional rise time control or use ISI board. t 20-80RX, Table 24, page Adjust eye amplitude opening to target value 4. Add following amount of common mode Sinusoidal Interference (SI) at 200 MHz to eye Steps to calibrate stressed eye 275mVdiff 240mVdiff 275mVdiff Differential, minimum amplitude. V diffrx, Table 24, page mVpp 100mVpp 150mVpp Table 24, page 139 V cm,acrx & f cm,acrx 5. Connect Clock Recovery, set to the following loop bandwidths. 6 MHz 6 MHz 1.8 MHz (300 MHz loop bandwidth is also called for, but seldom tested with) Type 2 roll-off and damping factor between and Change pattern to SATA COMP pattern. Patterns described in Section 7.2.4, starting on page Add DJ (BUJ or SJ) to following amounts 8. Add RJ until TJ reaches following amounts 0.42 UI 0.42 UI 0.35 UI (inc. ISI from board) Measured on Jitter Peak Table 24, page UI 0.6 UI 0.65 UI Some instrument RJ will be present, add to get correct answer at BER level of 1x Apply to DUT. Measure BER of DUT. Must be better than 1x Reduce SI frequency down to 2 MHz in steps of 1 or 10MHz, monitor Will be adjusting frequency down to 2 BER and ensure better than 1x MHz Use splitter & sig. gen. for low range. (See page 219, Figure 120.) 11. Change pattern to LBP (Lone Bit Pattern). Verify DJ, RJ settings. Patterns described in Section 7.2.4, starting on page Apply to Device Under Test. Repeat BER measurements while As above. See note (b) below. adjusting SI from 200 to 2 MHz. Notes: 1. Table & page references relate to reference [i]. The table referenced also points to test method details and parameter definitions elsewhere in the document. 2. There is discussion currently about verifying that the lone bit pattern is being received correctly; when in loop back mode, the pattern may be looped and re-transmitted, but with whichever legitimate version of the pattern is required to maintain parity. This means two possible patterns might be returned, and correct operation be occurring. A BERT looking for one pattern but receiving the other might see this as an error condition. Table 2: Test procedure for stressed eye construction
6 6 Practical Construction of the Stressed Eye Signal Table 3: Walking step by step through the eye calibration procedure detailed in Table 2. (Continued on next page)
7 7 Table 3: Walking step by step through the eye calibration procedure detailed in Table 2. Walking through the procedure of Table 2, an example eye construction is shown in Table 3. Some miscellaneous practical notes follow.
8 8 Sinusoidal Interference Suitable commercially available stress generating pattern generators include sources of sinusoidal interference. Commonly the frequency of interference does not cover the full range required for Serial ATA of 2-200MHz, with solutions having a low end cutoff of 100MHz. For lower frequencies, a recommended equipment configuration is given in the standard using an external sine wave generator and microwave splitters (see Figure 3 below). Figure 3: Recommended test setup for SI for testing below the 100MHz cutoff supplied by commonly available stressed pattern generators. ISI Board vs. Filter The 2x variant requires use of a compliant channel as part of the test setup. Although not compulsory for our example of a 2i setup, we ve used such an ISI board to provide some DJ and to limit the fast rise times of the pattern generator. The test board has the desired affect, but has a characteristic slow tail lasting far into the bit period (see Figure 4). If desired, use of a suitably designed microwave filter iii may be used. This can limit the rise time, but leave less of the remaining bit period affected, leaving the eye more open. Figure 4: Rise time limiting achieved by use of the ISI test board. PC Power Supply Some test devices will be whole or partial disk drives. A common method of powering such devices is to use a power supply from a PC, such as is shown in Figure 5. A quick practical note is that some PC
9 9 power supplies are equipped with load sensing capabilities, such that if insufficient current is being drawn from the supply, it will shut down. For this reason, evident in Figure 5 is the test device connected to the supply, and also one of the other outlets loaded with some high wattage resistors to ensure the supply is loaded sufficiently to operate. Test Setups The procedure of Tables 2 and 3 was used on a disk drive controller board, shown in Figures 5 and 6. The general test setup is detailed in Figure 5, and the stress signal constructed in Table 3 is being applied to the test device in Figure 6. The BER of the test device is being monitored on the laptop computer using chip control software. The setup in Figure 5 has also been used for transmitter compliance measurements. Figure 5: Basic test setup showing the main elements.
10 10 Figure 6: Testing with ISI board in place. Summary Using the ratified version 2.5 of the Serial ATA document, we have looked at one possible procedure for the construction of a compliant receiver jitter tolerance test signal. We have looked at a variety of practical aspects of SATA test and stepped through the calibration of a suitable stressed eye. Acknowledgment Thanks are due to Eric Kvamme and Hollis Poche for their assistance with this work. References [i] Serial ATA Revision 2.5 Revision 1.0RC, 16-August 2005, available at no charge from: [ii] Serial ATA Test Card, CTV-3 Molex P/N use search function with the 9 digit part number listed. [iii] A suitable rise time limiting filter is available from Picosecond Pulse Labs, Model PS, Copyright 2006 SyntheSys Research, Inc. SyntheSys is a registered trademark of SyntheSys Research, Inc. All rights reserved.
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