Design Entry: Schematic Capture and VHDL ENG241: Digital Design Week #4

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Design Entry: Schematic Capture and VHDL ENG241: Digital Design Week #4 1

References Kenneth Sort, VHDL For Engineers, Prentice Hall, 2009. Peter Ashenden, The designer s guide to VHDL, 2 nd edition, Morgan Kaufmann publishers, 2002. Douglas Perry, VHDL, 3 rd Edition, McGraw Hill. Sudhakar Yalamanchili, Introductory VHDL: From Simulation to Synthesis, Prentice Hall, 2001. Sudhakar Yalamnachili, VHDL: A Starter s Guide, 2 nd Edition, Prentice Hall, 2005. 2 2

Design Entry Schematic capture What you already did in previous labs. Hardware Description Language (HDL) VHDL Verilog Electronic System Level (ESL) Higher level possible C-like and Java-like» ImpulseC, HandelC, Catapult C, Vivado HLS 3 3

Schematic Design 4 4

What is HDL? o Hardware Description Languages (HDLs) are languages used to document (model), Communicate design, simulate, and synthesize digital circuits and systems. 5 5

VHDL: Introduction VHDL is an acronym for VHSIC Hardware Description Language. VHSIC is an acronym for Very High Speed Integrated Circuits program. It was a US government sponsored program that was responsible for developing a standard HDL. VHDL supports modeling and simulation of digital systems at various levels of design abstraction. 6 6

Basic Modeling Concepts External Interface circuit Inputs A B Internal Functionality E Outputs 7 7

Basic Modeling Concepts 8 8

Basic Modeling Concepts External Interface modeled by entity VHDL construct. Port Entity name Port name entity ckt1 is port (X,Y,Z : in bit; F : out bit); end entity ckt1; Port mode VHDL port construct models data input/output. 9 9

Basic Modeling Concepts Internal Functionality modeled by architecture VHDL construct Architecture name architecture behav of ckt1 is begin F <= X or (not Y and Z); end architecture behav; Entity name 10 10

Lexical Elements Comments: - A comment line in VHDL is represented by two successive dashes - -. - A comment extends from - - to the end of the line. Identifiers: - Identifiers are names that can be given by the user. - rules: >> must start with an alphabetic letter. >> can contain alphabetic letters, decimal digits and underline character _. >> cannot end with _. >> cannot contain successive _. 11 11

Legal vs. Illegal Identifiers Valid identifiers A, X0, counter, Next_Value Invalid identifiers last@value contains illegal character 5bit_coutner starts with nonalphabetic _A0 starts with an underline A0_ ends with underline clock pulses two successive underlines 12 12

Libraries A library refers to a collection of declarations (type, entity, sub-program) and their implementations (architecture, sub-program body). The actual specification of a library varies from one simulation package to another. In VHDL we usually use the IEEE library and have to declare that at the beginning of our VHDL program. 13 13

Library: Example For standard logic (std_logic) the basic package is ieee.std_logic_1164. This package defines the values and basic logic operators for type std_logic. The declarations can be made visible in our model file by : library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Library Package 14 14

std_logic type Demystified Value Meaning U X Not Initialized Forcing (Strong driven) Unknown 0 Forcing (Strong driven) 0 1 Forcing (Strong driven) 1 Z W L H High Impedance Weak (Weakly driven) Unknown Weak (Weakly driven) 0. Models a pull down. Weak (Weakly driven) 1. Models a pull up. Signals are used to connect different parts of a design. They can be thought of as wire in conventional sense. Every signal has a type. - Don't Care 15 15

Complete Program -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt1 is Port (X,Y,Z: in std_logic; F : out std_logic); end ckt1; -- Architecture Declaration architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav; 16 16

VHDL Design Styles VHDL Design Styles dataflow Concurrent statements structural Components and interconnects behavioral (algorithmic) Sequential statements Registers State machines Test benches Subset most suitable for synthesis ENG241/Digital Design 17 17

Example: Concurrent Statements This circuit could be modelled as following: f <= z or w; z <= x and y; x <= not a; w <= a and b; y <= not b; ENG241/VHDL Tutorial 18 18

Bit type Bit is also a predefined enumerated type type bit is ( 0, 1 ); Operations Logical: =, /=, <, >, <=, >= Boolean:and, or, nand, nor, xor, xnor, not Shift:sll, srl, sla, sra, rol, ror 19 19

Mapping the Design onto Digilent FPGA Board -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt1 is Port (X,Y,Z : in std_logic; F : out std_logic); end ckt1; Synthesis Netlist -- Architecture Declaration architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav; Download Map, Place and Route Generate Bitstream 000111010100000000011111001010101010000 010100101010101010001100101010110011000 20 20

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