2014 EE261: Intro to Digital Design Project 3: Four Bit Full Adder Abstract: This report serves to teach us, the students, about modeling logic and gives a chance to apply concepts from the course to a feasible application. It also gives us a chance to learn and/or practice technical writing. Zack Rauen Computer Engineering 0384482 rauenzi@clarkson.edu Jeremy Teed Electrical Engineering 0477392 teedjo@clarkson.edu Prof. Chen Liu Clarkson University 4/6/2014
TABLE of CONTENTS Title....... Page 1 Abstract... Page 1 Table of Contents..... Page 2 Objectives... Page 3 Discussion. Page 3 Schematics Page 4 Waveforms.. Page 5 Implementation Utilization.. Page 6 Self-Evaluations Page 6 Source Design Page 6 Test Bench.. Page 7 Zack Rauen & Jeremy Teed Page 2
Objectives: In this experiment the student will demonstrate: The ability to create logic design using VHDL with Xilinx PlanAhead Software. The characteristics of a four bit full adder. The ability to perform with design and time constraints Discussion: Design Characteristics of a four bit Full Adder: Must be represented by the following logic symbol Required to conform to the following truth table 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 Can be defined by the following Boolean equations o = o = +( ) Zack Rauen & Jeremy Teed Page 3
Characteristics of a four bit full adder: A four bit full adder takes 4 A inputs and 4 B inputs along with a carry in and adds the binary numbers together and represents it with 5 outputs. These outputs include 4 sums and 1 carry out. This is accomplished by hooking four of the previously described full adders together. The carry out of the individual adder gets hooked into each subsequent full adder as the carry in until the end where the carry out is the overall carry out. Schematics: Zack Rauen & Jeremy Teed Page 4
Waveforms: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0000 + 0000 + 0 = 0000 1000 + 0100 + 1 = 1101 0111 + 1000 + 1 = 0000 carry 1 0101 + 0010 + 1 = 1000 1000 + 0101 + 0 = 1101 1010 + 1101 + 1 = 1000 carry 1 1011 + 0010 + 1 = 1110 0101 + 1010 + 0 = 1111 1100 + 0100 + 0 = 0000 carry 1 1111 + 1111 + 0 = 1110 carry 1 Waveform, truth table, and manual calculations all agree Zack Rauen & Jeremy Teed Page 5
Implementation Utilization LUT = 1%, Slice = 1%, IO = 6%. Self-Evaluation: Zack Rauen: When making the 4 bit adder, at first I neglected to change the name of the entity in the testbench so I kept receiving undefined outputs. I quickly noticed it and changed it to match the entity that I had named in the source file. Other than that, there were no issues with this project. Jeremy Teed: Deriving truth tables from the waveform was confusing at first because it involves a range of values and looks different than usual. Once I figured it out, the rest of the project was fairly straightforward. Appendices Source Design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FullAdd is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Cout : out STD_LOGIC; Sum : out STD_LOGIC); end FullAdd; architecture Behavioral of FullAdd is begin Sum<=(A xor B) xor Cin; Cout<=(A and B) or (Cin and (A xor B)); end Behavioral; Zack Rauen & Jeremy Teed Page 6
LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FourBitAdd is port (A, B: in std_logic_vector(3 downto 0); Cin: in std_logic; Sum: out std_logic_vector(3 downto 0); Cout: out std_logic); -- A,B,Sum are 4 bit arrays end entity FourBitAdd; architecture FourBitFunc of FourBitAdd is signal C: std_logic_vector(3 downto 1); -- array of internals component FullAdd is port (A, B: in std_logic; Cin: in std_logic; Sum: out std_logic; Cout: out std_logic); end component FullAdd; begin FA1: FullAdd port map(a=>a(0), B=>B(0), Cin=>Cin, Sum=>Sum(0), Cout=>C(1)); FA2: FullAdd port map(a=>a(1), B=>B(1), Cin=>C(1), Sum=>Sum(1), Cout=>C(2)); FA3: FullAdd port map(a=>a(2), B=>B(2), Cin=>C(2), Sum=>Sum(2), Cout=>C(3)); FA4: FullAdd port map(a=>a(3), B=>B(3), Cin=>C(3), Sum=>Sum(3), Cout=>Cout); end architecture FourBitFunc; Testbench: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity my_4bit_fa_testbench is end my_4bit_fa_testbench; architecture behavior of my_4bit_fa_testbench is Zack Rauen & Jeremy Teed Page 7
component FourBitAdd Port ( A : in std_logic_vector (3 downto 0); B : in std_logic_vector (3 downto 0); Cin : in std_logic; Sum : out std_logic_vector (3 downto 0); Cout : out std_logic); end component; signal A: std_logic_vector (3 downto 0); signal B: std_logic_vector (3 downto 0); signal Cin: std_logic; signal Sum: std_logic_vector (3 downto 0); signal Cout : std_logic; --local signal declaration begin -- Component Instantiation UUT : FourBitAdd port map( A => A, B => B, Cin => Cin, Sum => Sum, Cout => Cout); -- Cycle through test vectors and evaluate the results process begin A <= "0000"; B <= "0000"; Cin <= '0'; A <= "1000"; Zack Rauen & Jeremy Teed Page 8
B <= "0100"; Cin <= '1'; A <= "0111"; B <= "1000"; Cin <= '1'; A <= "0101"; B <= "0010"; Cin <= '1'; A <= "1000"; B <= "0101"; Cin <= '0'; A <= "1010"; B <= "1101"; Cin <= '1'; A <= "1011"; B <= "0010"; Cin <= '1'; Zack Rauen & Jeremy Teed Page 9
A <= "0101"; B <= "1010"; Cin <= '0'; A <= "1100"; B <= "0100"; Cin <= '0'; A <= "1111"; B <= "1111"; Cin <= '0'; wait; end process; END; Zack Rauen & Jeremy Teed Page 10