VLSI Design I; A. Milenkovic 1

CPE/EE 427, CPE 527 VLSI Design I L0 Department of Electrical and Computer Engineering University of Alabama in Huntsville What is this course all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability 8/25/2003 VLSI Design I; A. Milenkovic 2 Digital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures 8/25/2003 VLSI Design I; A. Milenkovic 3 VLSI Design I; A. Milenkovic

The First Computer The Babbage Difference Engine (832) 25,000 parts cost: 7,470 8/25/2003 VLSI Design I; A. Milenkovic 4 ENIAC - The first electronic computer (946) Vacuum tube based digital computer The Giant Brain as labeled by the press ENIAC facts Occupied,800 sq. feet Weighted 30 tons 8000 vacuum tubes Application: calculate firing tables for World War II artillery guns 8/25/2003 VLSI Design I; A. Milenkovic 5 The Transistor Revolution First transistor Bell Labs, 948 8/25/2003 VLSI Design I; A. Milenkovic 6 VLSI Design I; A. Milenkovic 2

The First Integrated Circuits Bipolar logic 960 s ECL 3-input Gate Motorola 966 8/25/2003 VLSI Design I; A. Milenkovic 7 IC Evolution SSI Small Scale Integration (early 970s) contained 0 logic gates MSI Medium Scale Integration logic functions, counters LSI Large Scale Integration first microprocessors on the chip VLSI Very Large Scale Integration now offers 64-bit microprocessors, complete with cache memory (L and often L2), floating-point arithmetic unit(s), etc. 8/25/2003 VLSI Design I; A. Milenkovic 8 IC Evolution Bipolar technology TTL (transistor-transistor logic), 962; higher integration density ECL (emitter-coupled logic), 974; high-performance MOS (Metal-oxide-silicon) although invented before bipolar transistor (925, 935), was initially difficult to manufacture nmos (n-channel MOS) technology developed in late 970s required fewer masking steps, was denser, and consumed less power than equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market. aluminum gates for replaced by polysilicon by early 980 CMOS (Complementary MOS): n-channel and p-channel MOS transistors => lower power consumption, simplified fabrication process 8/25/2003 VLSI Design I; A. Milenkovic 9 VLSI Design I; A. Milenkovic 3

Introduction date: November 5, 97 Clock speed: 08 KHz Intel 4004 Number of transistors: 2,300 (0 microns) Bus width: 4 bits Addressable memory: 640 bytes Typical use: calculator, first microcomputer chip, arithmetic manipulation 8/25/2003 VLSI Design I; A. Milenkovic 0 0.8-micron process technology (2,.9,.8,.7,.6,.5, and.4 GHz) Introduction date: August 27, 200 (2,.9 GHz);...; November 20, 2000 (.5,.4 GHz) Level Two cache: 256 KB Advanced Transfer Cache (Integrated) System Bus Speed: 400 MHz SSE2 SIMD Extensions Transistors: 42 Million Typical Use: Desktops and entrylevel workstations 0.3-micron process technology (2.53, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 52 KB Advanced Transistors: 55 Million Pentium 4 8/25/2003 VLSI Design I; A. Milenkovic Introduction date: Mid 2002 Caches: 32KB L, 256 KB L2, 3MB L3 (on-chip) Clock: GHz Transistors: 22 Million Area: 464mm 2 Typical Use: High-end servers Future versions: 5GHz, 0.3-micron technology Intel s McKinley 8/25/2003 VLSI Design I; A. Milenkovic 2 VLSI Design I; A. Milenkovic 4

Moore s Law In 965, Gordon Moore noted that the number of transistors on a chip doubled every 8 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 8 months 8/25/2003 VLSI Design I; A. Milenkovic 3 Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION 6 5 4 3 2 0 9 8 7 6 5 4 3 2 0 959 960 96 962 963 964 965 966 967 968 969 970 97 972 973 974 975 Electronics, April 9, 965. 8/25/2003 VLSI Design I; A. Milenkovic 4 Evolution in Complexity 8/25/2003 VLSI Design I; A. Milenkovic 5 VLSI Design I; A. Milenkovic 5

Transistor Counts K,000,000 00,000 0,000,000 00 Billion Transistors Pentium III Pentium II Pentium Pro Pentium i486 i386 80286 0 8086 Source: Intel 975 980 985 990 995 2000 2005 200 Courtesy, Intel Projected 8/25/2003 VLSI Design I; A. Milenkovic 6 Moore s law in Microprocessors Transistors (MT) 000 00 0 0. 0.0 0.00 2X growth in.96 years! P6 Pentium proc 486 286 386 8085 8086 4004 8008 8080 970 980 990 2000 200 Year Transistors on Lead Microprocessors double every 2 years Courtesy, Intel 8/25/2003 VLSI Design I; A. Milenkovic 7 Die Size Growth 00 Die size (mm) 0 8080 8085 8008 4004 8086 286386 P6 486 Pentium proc ~7% growth per year ~2X growth in 0 years 970 980 990 2000 200 Year Die size grows by 4% to satisfymoore s Law Courtesy, Intel 8/25/2003 VLSI Design I; A. Milenkovic 8 VLSI Design I; A. Milenkovic 6

Frequency Frequency (Mhz) 0000 000 00 0 0. 8085 8080 8008 4004 Doubles every 2 years P6 Pentium proc 486 386 286 8086 970 980 990 2000 200 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel 8/25/2003 VLSI Design I; A. Milenkovic 9 Power (Watts) 00 0 0. Power Dissipation 8085 8080 8008 4004 286 8086 P6 Pentium proc 8/25/2003 VLSI Design I; A. Milenkovic 20 386 486 97 974 978 985 992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel Power (Watts) 00000 0000 Power will be a major problem 000 00 0 0. 8085 8086286 386 486 4004 80088080 Pentium proc 8KW 5KW.5KW 500W 97 974 978 985 992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel 8/25/2003 VLSI Design I; A. Milenkovic 2 VLSI Design I; A. Milenkovic 7

Power Density (W/cm2) 0000 000 00 Power density Rocket Nozzle Nuclear Reactor 8086 0 4004 Hot Plate 8008 8085 8080 286 386 486 P6 Pentium proc 970 980 990 2000 200 Year Power density too high to keep junctions at low temp Courtesy, Intel 8/25/2003 VLSI Design I; A. Milenkovic 22 Technology Directions: SIA Roadmap Year 999 2002 2005 2008 20 204 Feature size (nm) 80 30 00 70 50 35 Logic trans/cm 2 6.2M 8M 39M 84M 80M 390M Cost/trans (mc).735.580.255.0.049.022 #pads/chip 867 2553 3492 4776 6532 8935 Clock (MHz) 250 200 3500 6000 0000 6900 Chip size (mm 2 ) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 0 Power supply (V).8.5.2 0.9 0.6 0.5 High-perf pow (W) 90 30 60 70 75 83 8/25/2003 VLSI Design I; A. Milenkovic 23 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) 996 997 998 999 2000 48M 86M 62M 260M 435M Power Management Analog Baseband (data from Texas Instruments) Digital Baseband (DSP + MCU ) 8/25/2003 VLSI Design I; A. Milenkovic 24 VLSI Design I; A. Milenkovic 8

Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? /DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! 8/25/2003 VLSI Design I; A. Milenkovic 25 Productivity Trends 0,000,000 0,000,000,000,000 00,000 00 0,000 0,000 00 0. 0.0 0 Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 2%/Yr. compound Productivity growth rate 00,000,000 0,000,000,000,000 00,000 0,000,000 00 0. 0.00 0 0.0 98 983 985 987 989 99 993 995 997 999 200 2003 2005 2007 Complexity 2009 Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap 8/25/2003 VLSI Design I; A. Milenkovic 26 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction 8/25/2003 VLSI Design I; A. Milenkovic 27 VLSI Design I; A. Milenkovic 9

Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE n+ D 8/25/2003 VLSI Design I; A. Milenkovic 28 Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function 8/25/2003 VLSI Design I; A. Milenkovic 29 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area 8/25/2003 VLSI Design I; A. Milenkovic 30 VLSI Design I; A. Milenkovic 0

NRE Cost is Increasing 8/25/2003 VLSI Design I; A. Milenkovic 3 Single die Die Cost Wafer From http://www.amd.com Going up to 2 (30cm) 8/25/2003 VLSI Design I; A. Milenkovic 32 Cost per Transistor cost: -per-transistor 0. 0.0 0.00 0.000 0.0000 0.00000 Fabrication capital cost per transistor (Moore s law) 0.000000 982 985 988 99 994 997 2000 2003 2006 2009 202 8/25/2003 VLSI Design I; A. Milenkovic 33 VLSI Design I; A. Milenkovic

Yield No. of good chips per wafer Y = 00% Total number of chips per wafer Wafer cost Diecost = Dies per wafer Dieyield ( ) 2 π wafer diameter/2 π wafer diameter Dies per wafer = diearea 2 diearea 8/25/2003 VLSI Design I; A. Milenkovic 34 Defects α defectsper unit area diearea dieyield= + α α is approximately 3 diecost = f (diearea) 4 8/25/2003 VLSI Design I; A. Milenkovic 35 Some Examples (994) Chip Metal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer Yield Die cost 386DX 2 0.90 $900.0 43 360 7% $4 486 DX2 3 0.80 $200.0 8 8 54% $2 Power PC 60 4 0.80 $700.3 2 5 28% $53 HP PA 700 3 0.80 $300.0 96 66 27% $73 DEC Alpha 3 0.70 $500.2 234 53 9% $49 Super Sparc 3 0.70 $700.6 256 48 3% $272 Pentium 3 0.80 $500.5 296 40 9% $47 8/25/2003 VLSI Design I; A. Milenkovic 36 VLSI Design I; A. Milenkovic 2

Reliability? Noise in Digital Integrated Circuits i(t) v(t) V DD Inductive coupling Capacitive coupling Power and ground noise 8/25/2003 VLSI Design I; A. Milenkovic 37 DC Operation Voltage Transfer Characteristic V(y) V OH f V(y)=V(x) VOH = f(vol) VOL = f(voh) VM = f(vm) V Switching Threshold M V OL V OL V OH V(x) Nominal Voltage Levels 8/25/2003 VLSI Design I; A. Milenkovic 38 Mapping between analog and digital signals V OH V out V OH Slope = - V IH Undefined Region V IL Slope = - 0 V OL V OL V IL V IH V in 8/25/2003 VLSI Design I; A. Milenkovic 39 VLSI Design I; A. Milenkovic 3

Definition of Noise Margins "" V OH V OL NM H NM L Noise margin high V IH Undefined Region V IL Noise margin low "0" Gate Output Gate Input 8/25/2003 VLSI Design I; A. Milenkovic 40 Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources 8/25/2003 VLSI Design I; A. Milenkovic 4 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; 8/25/2003 VLSI Design I; A. Milenkovic 42 VLSI Design I; A. Milenkovic 4

Regenerative Property out v 3 f(v) out v 3 finv(v) v v fin v(v) v 3 f (v) v 2 v 0 Regenerative in v 0 v 2 Non-Regenerative in 8/25/2003 VLSI Design I; A. Milenkovic 43 Regenerative Property v 0 v v 2 v 3 v 4 v 5 v 6 A chain of inverters 5 V (Volt) 3 v0 v v 2 Simulated response 2 0 2 4 6 8 0 t (nsec) 8/25/2003 VLSI Design I; A. Milenkovic 44 Fan-in and Fan-out N M Fan-out N Fan-in M 8/25/2003 VLSI Design I; A. Milenkovic 45 VLSI Design I; A. Milenkovic 5

(V) V out The Ideal Gate V out g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V in 8/25/2003 VLSI Design I; A. Milenkovic 46 5.0 An Old-time Inverter 4.0 NM L 3.0 2.0 V M.0 NM H 0.0.0 2.0 3.0 4.0 5.0 V in (V) 8/25/2003 VLSI Design I; A. Milenkovic 47 Delay Definitions V in 50% t V out t phl t plh 90% 50% t f 0% t r t 8/25/2003 VLSI Design I; A. Milenkovic 48 VLSI Design I; A. Milenkovic 6

Ring Oscillator v 0 v v 2 v 3 v 4 v 5 v 0 v v5 T = 2 t p N 8/25/2003 VLSI Design I; A. Milenkovic 49 A First-Order RC Network R vout vin C t p = ln (2) τ = 0.69 RC Important model matches delay of inverter 8/25/2003 VLSI Design I; A. Milenkovic 50 Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power: t+ T Vsupply t+ T P ave = p( t) dt= i ( ) t t supplyt dt T T 8/25/2003 VLSI Design I; A. Milenkovic 5 VLSI Design I; A. Milenkovic 7

Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p 8/25/2003 VLSI Design I; A. Milenkovic 52 A First-Order RC Network R vout vin C L E 0 T T Vdd = Pt ()dt = V dd i supply ()dt t = V dd C L dv out = C L V 2 dd 0 0 0 T T Vdd E cap = P cap ()dt t = V out i cap ()dt t = C L V out dv out = - C V 2 2 L dd 0 0 0 8/25/2003 VLSI Design I; A. Milenkovic 53 Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this book Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation 8/25/2003 VLSI Design I; A. Milenkovic 54 VLSI Design I; A. Milenkovic 8

Layout designers Circuit designers Architects Test engineers Fabrication engineers System designers CAD tool programmers Jobs in VLSI 8/25/2003 VLSI Design I; A. Milenkovic 55 VLSI Design I; A. Milenkovic 9