- Spring 2002 Introduction to Digital Integrated Circuits Tu-Th 9:30-am 203 McLaughlin What is this class about? Introduction to digital integrated circuits.» CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn?» Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability 2
Digital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates; timing Arithmetic building blocks Interconnect: R, L and C Memories and array structures Design methods 3 Interludium: Administrativia Instructor Jan M. Rabaey jan@eecs.berkeley.edu Office hours: 5 Cory Tu -3pm 4 2
The TA s and Reader Dejan Markovic Discussion + lab dejan@bwrc.eecs.berkeley.edu Office Hours: TBD Huifang Qin Discussion + lab huifangq@bwrc.eecs.berkeley.edu Office Hours: TBD Nuntachai Poobuapheun Reader nuntachp@eecs.berkeley.edu 5 The Web-Site The sole source of information http://bwrc.eecs.berkeley.edu/classes/ee4 Class and lecture notes Assignments and solutions Lab and project information Exams Many other goodies Save a tree! 6 3
Class Admission Class is overenrolled» Class room only seats 65 + 5» But videotaped» Also webcasted (http://webcast.berkeley.edu) Admission priorities» Graduating seniors» First-year grads» Juniors, other grads» Concurrent enrollment Make sure your name is on the class roll! 7 Discussions and Labs Discussion sessions» We 9-am, 293 Cory» We 2-3pm, 247 Cory» Pick any of the two (the are covering the same material)» One of them will be moved to another time slot (in 203 McLaughlin) Labs (353 Cory)» Mo 9-2am» Tu 2-5pm» Th 2:30-3:30pm» Pick the one that fits you the best (pending availability) and STICK TO IT! 8 4
Class Organization Assignments A couple of design projects ( term project) Labs: 6 software, hardware 2midterms,final» Midterm : Tu, February 25, 6:30-8:00pm» Midterm 2: Tu, April 5, 6:30-8:00pm» Final: Tu. May 20, 8-am 9 Grading Policy Homeworks: % Labs: % Projects: 20% Midterms: 30% Final: 30% 5
Class Material Textbook: Digital Integrated Circuits A Design Perspective, 2 nd Edition, by J. Rabaey, A. Chandrakasan, and B. Nikolic Lab Reader: Available on the web page! Selected material will be made available from Copy Central Check web page for the availability of tools Software MicroMagic» Schematic editor: Sue» Layout editor: Max» Online documentation and tutorials HSPICE and IRSIM for simulation 2 6
Getting Started Assignment : Getting SPICE to work see web-page NO discussion sessions or labs this week. First discussion sessions in Week 2 First Software Lab in Week 3 3 Introduction Why is designing digital ICs different today than it was before? Will it change in future? 4 7
The First Computer The Babbage Difference Engine (832) 25,000 parts cost: 7,470 5 ENIAC - The first electronic computer (946) 6 8
The Transistor Revolution First transistor Bell Labs, 948 7 The First Integrated Circuits Bipolar logic 960 s ECL 3-input Gate Motorola 966 8 9
Intel 4004 Micro-Processor 9 Evolution in Transistor Count 20
Intel Pentium (II) microprocessor 2 Moore s Law In 965, Gordon Moore noted that the number of transistors on a chip doubled every 8 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 8 months 22
Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION 6 5 4 3 2 9 8 7 6 5 4 3 2 0 959 960 96 962 963 964 965 966 967 968 969 970 97 972 973 974 975 Electronics, April 9, 965. 23 Evolution in Complexity 24 2
Transistor Counts,000,000 K Billion Transistors 0,000,000,000 0 Pentium III Pentium II Pentium Pro i486 Pentium i386 80286 8086 Source: Intel 975 980 985 990 995 2000 2005 20 Projected 25 Moore s law in Microprocessors Transistors (MT) 00 0 2X growth in.96 years! P6 Pentium proc 486 0. 286 386 8085 8086 Transistors 0.0 on Lead 4004 8008 8080 Microprocessors double every 2 years S. Borkar 0.00 970 980 990 2000 20 Year 26 3
Moore s Law - Logic Density 00 Logic Transistors/mm 2 Logic Density 0 386 i860 Pentium II (R) 486 Pentium Pro (R) Pentium (R) 2x trend.5µ.0µ 0.8µ 0.6µ Source: Intel 0.35µ 0.25µ 0.8µ 0.3µ Shrinks and compactions meet density goals New micro-architectures drop density 27 DieSizeGrowth 0 Die size (mm) 8080 8085 8008 4004 8086 286386 P6 486 Pentium proc ~7% growth per year ~2X growth in years 970 980 990 2000 20 Year Die size grows by 4% to satisfy Moore s Law S. Borkar 28 4
Frequency Frequency (Mhz) 000 00 0 0. Doubles every 2 years P6 Pentium proc 486 8085 386 8086 286 8080 8008 4004 S. Borkar 970 980 990 2000 20 Year Lead Microprocessors frequency doubles every 2 years 29 Processor Frequency Trend,000 Intel IBM Power PC DEC Gate delays/clock Processor freq scales by 2X per generation 0 Mhz,000 0 987 386 989 486 99 2264S 264A 2264 264A Pentium(R) 264 II 266 MPC750 604 604+ Pentium Pro 60, 603 (R) Pentium(R) 993 995 997 999 Frequency doubles each generation Number of gates/clock reduce by 25% 200 2003 2005 Gate Delays/ Clock V.De, S. Borkar ISLPED 99 30 5
Power 0 Power (Watts) 8085 8080 8008 4004 8086 286 386 486 P6 Pentium proc 0. 97 974 978 985 992 2000 Year S. Borkar Lead Microprocessors power continues to increase 3 0 Processor Power Max Power (Watts) 486 Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX 386 386.5µ µ 0.8µ 0.6µ 0.35µ 0.25µ 0.8µ 0.3µ Lead processor power increases every generation Compactions provide higher performance at lower power? Source: Intel 32 6
Power will be a problem Power (Watts) 0000 000 00 0 0. 8085 8086286 386 486 4004 80088080 Pentium proc 5KW 8KW.5KW 500W 97 974 978 985 992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive S. Borkar 33 Power density will increase Power Density (W/cm2) 000 00 0 4004 8008 8080 Rocket Nozzle Nuclear Reactor 8086 Hot Plate 8085 286 386 486 P6 Pentium proc 970 980 990 2000 20 Year S. Borkar Power density too high to keep junctions at low temp 34 7
Power delivery challenges Icc (amp),000.00 0.00 L(di/dt)/Vdd.00.00 P6 8086 Pentium proc 386 486 8080 286 0. 8085 4004 8008 0.0 970 980 990 2000 20 Year.E+07.E+06.E+05.E+04.E+03.E+02.E+0.E+00.E-0.E-02.E-03.E-04 8086 386 8080 286 8085 4004 8008 P6 Pentium proc 486 970 980 990 2000 20 Year S. Borkar High supply currents at low voltage: Challenges: IR drop and L(di/dt) noise 35 Not Only Microprocessors Cell Phone Small Signal RF Power RF Digital Cellular Market (Phones Shipped) 996 997 998 999 2000 Units 48M 86M 62M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) 36 8
Productivity Trends,000,000,000,000,000,000 Complexity Logic Transistor per Chip (M) 0,000 0,000,000 0 0. 0.0 Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 2%/Yr. compound Productivity growth rate 0,000,000,000,000,000,000 0,000,000,000 0 0. Productivity (K) Trans./Staff - Mo. 0.00 0.0 98 983 985 987 989 99 993 995 997 999 200 2003 2005 2007 2009 Source: Sematech Complexity outpaces design productivity 37 Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? /DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! 38 9
Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+ 39 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x How to design chips with more and more functions? Design engineering population does not double every two years Need to understand different levels of abstraction 40 20
Next Class Introduces basic metrics for design of integrated circuits how to measure delay, power, etc. Brief intro to IC manufacturing and design 4 2