Viterbi Algorithm - Implementation

Transcription

1 Viterbi Algorithm - Implementation Lecture 14 Vladimir Stojanović Communication System Design Spring 2006 Massachusetts Institute of Technology

2 Convolutional Codes Adding redundancy 1+D d i d i-1 d i-2 Channel D D+D 2 Generators: G 1 = 101 G 2 = D (00, 11, 10, 10) Communication System Design 2

3 Decisions at Each Step i i+1 i+2 In Gaussian channel: bm = (y k s k ) 2 In BSC: bm = d H (y k, s k ) = y k s k State (path) metrics Branch metrics d H is Hamming distance If received y k = 10 d H (10, 00) = 1 d H (10, 01) = Communication System Design 3

4 Trellis Diagram Time-indexed state diagram 00 i i+1 i+2 i+3 i+4 0/00 0/ /11 1/11 0/ / Communication System Design 4

5 The Viterbi Algorithm Illustrated by 2-state trellis sm1 n 1 bm1 sm1 n bm2 bm3 sm2 n 1 bm4 sm2 n t n 1 t n time sm1 n = min (sm1 n 1 + bm1, sm2 n 1 + bm3) sm2 n = min (sm1 n 1 + bm2, sm2 n 1 + bm4) Select Add Compare Add Communication System Design 5

6 Viterbi Decoder Implements Viterbi algorithm Three main components Branch metric calculation Path metric accumulation (add-compareselect recursion) Survivor path decode Communication System Design 6

7 Viterbi Decoder D Inputs Branch metrics unit Add- Compare- Select Survivor path decode Decoded bits Branch metrics unit Calculates the distances between the received signal and the ideal signals Add-Compare-Select unit Accumulates path metrics Survivor path decode Keeps track of the path through the trellis Communication System Design 7

8 Calculating Branch Metrics Assume G 1 and G 2 both output a 0 Soft decoder inputs are 0.1 and 0.25 instead Branch metrics: bm 00 = = 0.35 bm 01 = = 0.85 bm 10 = = 1.15 bm 11 = = Communication System Design 8

9 Calculating Branch Metrics Euclidean distances (AWGN channel) bm i = (y k s k ) 2 s k are usually integers bm i = y k 2-2C i y k + C i 2 Since y k terms are common to all branch metrics they drop out in ACS comparison, and can be eliminated. C i 2 are precomputed and 2C i y k are shifts and adds Communication System Design 9

10 Add-Compare-Select Recursion Eight state trellis Conventional add-compare-select unit Communication System Design 10

11 Add-Compare-Select Recursion bm1 5 sm1 sm2 8 8 Adder bm2 5 Adder 8 8 Subtractor MSB 2:1 Multiplexer Register New State Metric 8 Decision Communication System Design 11

12 Add-Compare-Select Recursion sm2 7 sm1 7 + diff sm2 6 sm1 6 + sm 7 sm2 5 sm1 5 + sm 6 bm2 4 sm2 4 bm1 4 sm1 4 + sm 5 bm2 3 sm2 3 bm1 3 + sm 4 bm2 2 sm2 2 bm1 2 + sm 3 bm2 0 sm2 0 bm1 0 sm1 0 bm2 1 sm2 1 bm sm 2 sm 1 sm Communication System Design 12

13 Add-Compare-Select Recursion Time Register Select C C C C C C C C Add Register Bit Communication System Design 13

14 Add-Compare-Select Recursion One step lookahead applied to an eight-state trellis Radix-4 add-compare-select unit Communication System Design 14

15 Add-Compare-Select Recursion 4-way ACS: bm1 5 bm2 5 bm3 5 sm3 sm1 sm2 sm Adder Adder Adder 2 additions + bm4 6 comparisons 5 Adder Inhibit sm3 Inhibit sm4 Subtractor MSB Subtractor MSB Subtractor MSB Subtractor MSB Select Subtractor MSB Subtractor MSB 4:1 Multiplexer Register Communication System Design Decision 8 New State Metric 15

16 2-state example Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture." IEEE Communications Magazine 29 (1991): Copyright 1991 IEEE. Used with permission Communication System Design 16

17 Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture." IEEE Communications Magazine 29 (1991): Copyright 1991 IEEE. Used with permission Communication System Design 17

18 Bit-level view MSB LSB Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture." IEEE Communications Magazine 29 (1991): Copyright 1991 IEEE. Used with permission Communication System Design 18

19 Turn into forward path and pipeline Figures from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture." IEEE Communications Magazine 29 (1991): Copyright 1991 IEEE. Used with permission Communication System Design 19

20 Add-Compare-Select Recursion Parallel compare-select-add unit Communication System Design 20

21 References Slides from Borivoje Nikolic and Bob Brodersen G. Fettweis and H. Meyr "High-speed parallel Viterbi decoding: algorithm and VLSI- architecture," Communications Magazine, IEEE vol. 29, no. 5, pp , Communication System Design 21