Indian Silicon Technologies 2013

Transcription

1 SI.No Topics IEEE YEAR 1. An RFID Based Solution for Real-Time Patient Surveillance and data Processing Bio- Metric System using FPGA 2. Real-time Binary Shape Matching System Based on FPGA 3. An Optimized RFID-Based Academic Library 4. FPGA based System for Enhancing Medication Safety and Healthcare for Inpatients Using RFID 5. Pulse Propagation Along Single-Wire Electric Fences 6. Multi-sensory system for obstacle detection on railways 7. Pulse Propagation Along Single-Wire Electric Fences(2008T) 8. An efficient FPGA implementation of secure cryptographic technique using Wireless Body Area Network. 9. Finger Print Based Authentication and Controlling System of Devices using FPGA 10. Implementation Of Tsunami Alert System Using FPGA 11. Designing Of VGA Character String Display Module Based On FPGA 12. High Throughput One Dimensional Median And Weighted Median Filters On FPGA 13. A HW/SW Co-Verification Technique For Field Programmable Gate Array (FPGA) Test 14. A Framework Of Transaction-Based HW/SW Co-Simulation For IC Verification 15. A Low Overhead Fault Detection And Recovery Method For The Faults In Clock Generators 16. Transaction Level Modeling For Early Verification On Embedded System Design 17. A Dynamically Reconfigurable Arithmetic Circuit For Complex Number And Double Precision Number 18. A Low-Power Delay Buffer Using Gated Driver Tree 19. Quadrature Phase Shift Keying Modulator &Demodulator For Wireless Modem 20. Low Power And Area Efficient Image Segmentation VLSI Architecture Using 2- Dimensional Pixel-Block Scanning 21. Broadband Receiver Design On FPGA 22. Embedded A Low Area 32-Bit AES For Image Encryption/Decryption Application 23. Medical Image Fusion Based On An Improved Wavelet Coefficient Contrast 24. On Line Wavelets Transform On A Xilinx FPGA Circuit To Medical Images Compression 25. Research On Image Median Filtering Algorithm And Its FPGA Implementation 26. A Framework Of Transaction-Based HW/SW Co-Simulation For IC Verification 27. Mean-Square Performance Of Selective Partial Update Sub-Band Adaptive Filters 28. Experiences Using The Xilinx Micro Blaze Soft Core Processor And μclinux In Computer Engineering Capstone Senior Design Projects. 29. Hand Gesture Recognition System Based On Associative Processors Real Time Design And Implementation Of Mobile Based Electrical Appliances Control For Industrial Automation 31. Improved Method To Increase AES System Speed 32. Design Of Reconfigurable LED Illumination Control System Based On FPGA 2012

2 33. Design And Development Of Activation And Monitoring Of Home Automation System Via SMS Through Microcontroller 34. Implementation Of A Hardware Functional Verification System Using System C Infrastructure

3 35. High Speed VLSI Implementation Of A Finite Field Multiplier Using Redundant Representation 36. Full Coverage Manufacturing Testing For SRAM-Based FPGA 37. A Design Of Bi-Verification Vehicle Access Intelligent Control System Based On RFID 38. A Measurement System For The Performance Assessment Of Car-Integrated GSM Mobile Communications Systems 39. Design Of Video Compression System Based On DSP-FPGA 40. On Line Wavelets Transform On A Xilinx FPGA Circuit To Medical Images Compression 41. Design And Implementation Of Mobile Based Electrical Appliances Control For Industrial Automation 42. Dynamic Power Analysis For Custom Designs 43. High-Speed FPGA Implementation For DWT Of Lifting Scheme 44. FPGA Based Remote Integrated Security System Based WAP 45. Throughput Efficient Parallel Implementation Of SPIHT Algorithm 46. Real-Time Invariant Textural Object Recognition With FPGAs 47. VLSI Architectures Of Perceptual Based Video Watermarking For Real-Time Copyright Protection 48. A New Digital Watermarking Scheme Based On Text 49. HW/SW Co-Simulation Platforms For VLSI Design 50. Significance Of Tree Structures For Zero Tree-Based Wavelet Video CODECS 51. Image Coprocessor: A Real-Time Approach Towards Object Tracking 52. Transistor Count Optimization Of Conventional CMOS Full Adder & Optimization Of Power And Delay Of New Implementation Of 18 Transistor 1-V, High Speed, Low Leakage CMOS 53. A Novel Cost-Effective Combine Generation And Cross-Talk Mitigation In Optical OFDM Signal Using Optical IFFT Circuits 54. Design Optimization Of FPGA Based Viterbi Decoder 55. Removal Of Sign-Extension Circuitry From Booth's Algorithm Multiplier-Accumulators 56. An Optimized Tag Sorting Circuit In WFQ Scheduler Based On Leading Zero Counting 57. VLSI Implementation Of WIMAX Convolutional Code Encoder And Decoder 58. Design & Implementation Of A Low Power Differential Amplifier 59. Comprehensive Analysis And Control Of Design Parameters For Power Gated Circuits 60. Low-Power Leading-Zero Counting And Anticipation Logic For High-Speed Floating Point Units (Verilog) 61. GPS-GSM Based Bus Stop Automation 62. Flexible Hardware Architecture Of Hierarchical K-Means Clustering For Large Cluster Number 63. A New And Efficient Algorithm For The Removal Of High Density Salt And Pepper Noise In Images And Videos 64. Performance Evaluation Of DES And Blowfish Algorithms 65. FPGA-Based GPS Application System Design 2012

4 66. Hellfire: A Design Framework For Critical Embedded Systems Applications 67. Design And Implementation Of Different Multipliers Using VHDL 68. FPGA-Based Implementation Of A Low Cost And Area Real-Time Motion Detection Energy-Efficient Design Methodologies: High-Performance VLSI Adders

5 70. An Integrated Library Management System For Book Search And Placement Tasks 71. System Level Simulation Guided Approach To Improve The Efficiency Of Clock-Gating Adaptive 2-D Wavelet Transform Based On The Lifting Scheme With Preserved Vanishing Moments 73. Design Of Low-Power High-Speed Truncation-Error-Tolerant Adder And Its Application In Digital Signal Processing 74. An Enhanced Railway Transport System Using FPGA Through GPS & GSM 75. Design And Sensitivity Analysis Of A New Current-Mode Sense Amplifier For Low-Power SRAM 76. System Level Simulation Guided Approach To Improve The Efficacy Of Clock-Gating 77. Motion Human Detection Based On Background Subtraction 78. A Wide-Range All-Digital Delay-Locked Loop In 65nm CMOS Technology 79. A High Performance Binary To BCD Converter For Decimal Multiplication 80. A New VLSI Architecture Of Parallel Multiplier Accumulator Based On Radix-2 Modified Booth Algorithm 81. An FPGA Implementation Of The Time Domain Deadbeat Algorithm For Control Applications 82. Implementation Of Convolutional Encoder And Viterbi Decoder Using VHDL 83. Standby Leakage Power Reduction Technique For Nano - scale CMOS VLSI Systems 84. Dual Stack Method: A Novel Approach To Low Leakage And Speed Power Product VLSI Design 85. Message Encoding In Images Using Lifting Schemes 86. A Color Image Segmentation Based On Region Growing 87. Design Of FFT Processor Based On FPGA 88. Reconfigurable Hardware For Median Filtering For Image Processing Applications 89. SIM Card Based Smart Banking Using FPGA 90. FPGA Based Inexpensive Automobile Refuge System 91. A Pipeline VLSI Architecture For High-Speed Computation Of The 1-D Discrete Wavelet Transform 92. Low-Power And Area-Efficient Carry Select Adder 93. Design Of A Low Power Flip-Flop Using CMOS Deep Submicron Technology 94. Ground Bounce Noise Reduction Of Low Leakage 1-Bit Nano - CMOS Based Full Adder Cells For Mobile Applications 95. Image Edge Detection Based On FPGA 96. An FPGA-Based Architecture For Linear And Morphological Image Filtering 97. Keyless Car Entry Through Face Recognition Using FPGA 98. Flexible Hardware Architecture Of Hierarchical K-Means Clustering For Large Cluster Number 99. Power Estimation Of Embedded Multiplier Blocks In FPGAs 100. Design And Implement Of The Embedded Elevator Monitor System Based On Wireless Communication 101. Variability Resilient Low-Power 7T-SRAM Design For Nano - Scaled Technologies (2010C

6 102. Design And Analysis Of Two Low-Power SRAM Cell Structures 103. Optimization Of Processor Architecture For Image Edge Detection Filter

7 104. Enhancing NBTI Recovery In SRAM Arrays Through Recovery Boosting 105. Design And FPGA Implementation Of Modified Distributive Arithmetic Based DWT IDWT Processor For Image Compression 106. Enhancing Efficiency In SRAM Arrays Through Recovery Boosting 107. Adiabatic Technique For Energy Efficient Logic Circuits Design 108. Operation Improvement Of Indoor Robot By Gesture Recognition 109. Removal Of High Density Salt & Pepper Noise Through Modified Decision Based Un- Symmetric Trimmed Median Filter 110. Low-Power and Area-Efficient Carry Select Adder 111. Low-Power and Area-Efficient Carry Select Adder On Modulo 2n-1 Adder Design 113. A_Low-Cost_VLSI_Implementation_for_Efficient_Removal_of_Impulse_Noise-QR Compressive_Acquisition_CMOS_Image_Sensor_From_the_Algorithm_to_Hardware_Imp lementation-1cq 115. Graphics LCD, LED displays COntroller and Driver implemenattion in VHDL usingfpga 116. Implementation of RC4 Encryption Decryption Algorithm in VHDL for WiFi security 117. Position Control of an AC Servo Motor Using FPGA and VHDL 118. A STUDY OF TRANSLATION LOOKASIDE BUFFER STRUCTURES FOR LOW POWER CONSUMPTION 119. VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)