On the Generation of Multiplexer Circuits for Pass Transistor Logic

Transcription

1 Preprint from Proeedings of DATE 2, Paris, rane, Marh 2 On the Generation of Multiplexer Ciruits for Pass Transistor Logi Christoph Sholl Bernd Beker Institute of Computer Siene Albert Ludwigs University D 79 reiburg im Breisgau, Germany <name>@informatik.uni-freiburg.de Abstrat Pass Transistor Logi has attrated more and more interest during last years, sine it has proved to be an attrative alternative to stati CMOS designs with respet to area, performane and power onsumption. Existing automati PTL synthesis tools use a diret mapping of (deomposed) BDDs to pass transistors. Thereby, strutural properties of BDDs like the ordering restrition and the fat that the selet signals of the multiplexers (orresponding to BDD nodes) diretly depend on input variables, are imposed on PTL iruits although they are not neessary for PTL synthesis. General Multiplexer Ciruits an be used instead and should provide a muh higher potential for optimization ompared to a pure BDD approah. Nevertheless to the best of our knowledge an optimization of general Multiplexer Ciruits (MCs) for PTL synthesis was not tried so far due to a lak of suitable optimization approahes. In this paper we present suh an algorithm whih is based on effiient BDD optimization tehniques. Our experiments prove that there is indeed a high optimization potential by the use of general MCs both onerning area and depth of the resulting PTL networks. Introdution Pass Transistor Logi (PTL) has proved to be an attrative alternative to stati CMOS designs with respet to area, performane and power onsumption [23, 5, 9, 2]. In earlier works using PTL the main disadvantage was that the PTL iruits were designed by hand and there was a lak of automati synthesis tools. Reently, several approahes for an automati PTL synthesis flow were proposed [22, 6, 3,, 8, 3]. They are all based on a mapping of BDDs [5] (in most ases of deomposed BDDs) to PTL. The advantage of this method is that the PTL iruits originating from BDDs are sneak-pathfree [3, 6], i.e. there is no assignment to the inputs whih produes a onduting path from power supply to ground. However, BDDs use an ordering restrition, whih is not neessary for PTL synthesis. Moreover even the restrition to free BDDs [2] or general BDDs [] is not neessary. It is easy to see that we an also use general Multiplexer Ciruits (MCs) as a basis to synthesize PTL iruits without losing the property of sneak-path absene. Of ourse, there are more degrees of freedom for MC optimization ompared to BDD optimization, sine BDDs an be viewed as speial ases of MCs. Thus, MCs should provide better PTL solutions than BDDs. However to the best of our knowledge all existing automati PTL synthesis proedures are based on BDDs. One reason for this ould be the fat, that there are effiient BDD pakages (see e.g. [2]), whih provide effiient BDD optimization tehniques by variable reordering like [6], whereas powerful optimization tehniques for MCs have been missing. In this paper we present suh a powerful optimization proedure for MCs, whih makes use of the additional degrees of freedom ompared to BDDs. Our novel tehnique is able to improve on both size and depth of BDD based iruits (see Setion 5). Although the result of our algorithm are MCs, we an make use of well matured and effiient BDD optimization tehniques to ompute the MCs. In Setion 2 we give a omparison between BDDs and MCs. Setion 3 reviews how BDDs or MCs are mapped to Pass Transistor Logi. In Setion 4 we present our algorithm for MC minimization. After giving experimental results for PTL synthesis using this algorithm in Setion 5 we onlude the paper with Setion 6. 2 BDDs versus MCs BDDs provide a anonial representation of Boolean funtions. As defined in [5], they are ordered, i.e. on eah MCs are basially the same as if-then-else DAGs [].

2 path from their root to a terminal node eah input variable ours only one and on eah path the input variables our in the same order. In ontrast, Multiplexer Ciruits (MCs) are more general: Definition A Multiplexer Ciruit (MC) M is modeled as a direted ayli graph (V,E). The node set V is partitioned into four sets V onst, V inp, V inv and V mux : The nodes of V onst are onstants, have indegree and are labeled by or. The nodes of V inp are inputs, have indegree and are labeled by Boolean variables. The nodes of V inv are inverters and have indegree. The nodes of V mux are multiplexers and have indegree 3. There is a bijetive mapping IN : {,..., V inp } V inp suh that IN(i) defines the ith input of the funtion defined by the MC M. There is a mapping OUT : {,...,m} V suh that OUT(i) defines the ith output of the funtion defined by the MC M. Thus MCs are Boolean iruits onsisting only of multiplexers, inverters and onstants and it is straightforward to define the Boolean funtion represented by an MC. Sine a BDD node labeled by a variable x i an be viewed as a multiplexer with selet input x i, it is lear, that BDDs an be viewed as a restrited lass of MCs. Beause BDDs orrespond only to a restrited lass of MCs, it is also lear, that there are more degrees of freedom in MC optimization ompared to BDD optimization. However the question arises how to exploit these additional degrees of freedom. Our answer to this question an be found in Setion 4. Before we deal with our approah to MC optimization, we give a brief review of Pass Transistor Logi (PTL) in the next setion. 3 Pass Transistor Logi Pass Transistor Logi has proved to be an attrative alternative to stati CMOS designs 2 with respet to area, performane and power onsumption [23, 5, 9, 2, 22, 6, 3,, 8, 3]. The basi unit in PTL is a MOS transistor whih is used as a swith. It is very easy to implement a multiplexer as a wired OR of two MOS transistors (see igure ). or this reason reent automati PTL synthesis tools use BDDs as a basis for PTL synthesis. igure 2 shows an example of a BDD mapped to an NMOS PTL implementation. Mapping BDDs to PTL is easy and has the additional advantage that the resulting iruits are sneak-path-free. But note that the same is also true for general Multiplexer Ciruits. 2 whih are in fat restrited ases of PTL G x H x G H igure. Implementation of a multiplexer by pass transistors b a = a b + igure 2. Mapping of a BDD to an NMOS PTL implementation 4 Our Algorithm for MC minimization A mapping to PTL is not only easy for BDDs, but also for general MCs. Sine MCs are more general, there is a higher potential for optimization both onerning area and depth. A BDD realizing an n input Boolean funtion typially ontains paths of BDD nodes/multiplexers of length n, suh that the delay of a orresponding PTL implementation is linear in n. More preisely, a hain of n transistors in series even has a quadrati delay in n [2] and buffers have to be inserted after a onstant number of levels to ahieve a linear delay. We will show in the following that a path of length n an be avoided by using MCs. To present our algorithm for MC minimization we need the following definition whih haraterizes speial nodes at the bottom of a BDD: Definition 2 A BDD node is alled a positive variable node iff its low son is onstant and its high son is onstant. It is alled a negative variable node iff its low son is onstant and its high son is onstant and it is alled a variable node iff it is a positive or a negative variable node. A BDD node is alled a multiplexer node iff both, low son and high son, are a onstant node or a variable node and at least one of the sons is a variable node. If both sons of a multiplexer node are variable nodes it is alled a true multiplexer node, otherwise a pseudo multiplexer node. Intuitively, our algorithm now suessively removes multiplexer nodes from the original BDD thereby replaing a b x a b

3 parts of the BDD by new variables. The meaning of the new variables is omputed in a separate MC. inally, the whole BDD has been transformed into an MC. Our algorithm starts with a BDD for a single-output Boolean funtion. (Note that it an easily be extended to multi-rooted BDDs and BDDs with omplemented edges [4].) The algorithm uses a mapping m map between {x,...,x n } and the input nodes of the MC, i.e., m map(x i ) gives the MC input node labeled by x i. In the ourse of the algorithm m map is extended to newly introdued variables x, here m map(x) gives the signal line in the MC orresponding to x. The algorithm now proeeds as follows (for illustration see also igure 3): Input: BDD B representing funtion f : {,} n {,} with input variables x,...,x n. Output: MC for f.. (a) Compute all multiplexer nodes of BDD B. (b) If there is a true multiplexer node, hoose v mux as the true multiplexer node with most inoming edges 3. If there are only pseudo multiplexer nodes, hoose v mux as the pseudo multiplexer node with most inoming edges. () Build the BDD BDD for a new intermediate variable. (d) Replae v mux and the orresponding sub-bdd in B by BDD. (e) A new multiplexer is introdued in the MC. If v mux is labeled by variable x, the selet input of the multiplexer is onneted to MC node m map(x). If the low son of v mux is onstant (), the -data-input of the multiplexer is onneted to onstant () node of the MC. If the low son is the positive variable y, the -data-input of the multiplexer is onneted to m map(y) and if the low son is the negative variable y, the -data-input of the multiplexer is onneted to a new inverter, whih itself is onneted to m map(y). The -data-input is assigned in the same way. 2. Optimize the resulting BDD B by variable reordering. 3. Repeat steps and 2 until the BDD onsists only of one variable node. Note that reordering an ause a hange of the variable label of the next multiplexer node to be replaed. (Experiments using our algorithm for MC optimization show that this happens indeed.) 3 The intuition behind this seletion is that this multiplexer node is the most important for the omputation of the BDD in some sense. In eah step of the algorithm the initial Boolean funtion f is represented by two parts: a BDD part and a MC part. Of ourse, we may interpret the BDD part as an MC. If we onnet the selet-inputs of the multiplexers for BDD nodes labeled by variable x to m map(x), then we obtain an MC for f. The MC size ahieved so far an be determined by the size of the already onstruted MC part and the size of the remaining BDD. Optimizing the size of the remaining BDD orresponds to optimizing this preliminary size. But we an also optimize the depth of the urrent MC iruit: Eah variable of the BDD orresponds to a primary input variable or a multiplexer of the already onstruted MC. This means that a iruit depth information an be assigned to eah BDD variable. If we interpret the BDD part as an MC again, we an ompute the urrent depth of the iruit. Changing the variable order of the BDD does also hange the depth of the iruit. To optimize size and depth of the resulting MC (step 2. of the algorithm) we use a variant of [6], whih we all delay. (Ordinary) is based on finding the loally optimal position of a variable assuming that all other variables remain fixed. To determine the optimal position of a variable in the variable order it is sifted to all possible positions and then, the position, where the resulting BDD size is minimized, is seleted. The ost funtion during is only the size of the resulting BDD. To take aount of our two optimization goals (area and depth) we hange the ost funtion of : We use some ombination of BDD size and depth of the overall iruit. or eah position of the variable we determine the new size size new of the resulting BDD and the new depth of the overall iruit depth new. Then we hoose the position for the variable where the expression α sizenew depthnew +( α) sizeold depth old () is minimized. (size old and depth old, respetively, mean the BDD size and depth of the overall iruit before moving the variable, α is a number between and to influene the trade off between BDD sizes and depth.) If the already onstruted part of the MC iruit gives depth information d x for variable x at level i, we say that x provides depth ontribution d x + i. The depth of the overall iruit is estimated by the maximum depth ontribution over all levels i. This gives us only an approximation of the total depth, but the approah has the advantage that the depth estimation an adjusted loally during level exhange, suh that asymptoti omplexity of delay remains the same as for original. igure 4 gives an interesting example for our algorithm to optimize MCs. We onsider the exor funtion with 8 inputs. Note that for this example in eah step of the al-

4 x j k i + + k k i BDD x j i igure 3. Illustration of step ) of the algorithm: x j is a primary input variable, i and k intermediate variables for multiplexers introdued in previous steps of the algorithm. The multiplexer node labeled by k is replaed by a the BDD BDD for a new variable and a new multiplexer is introdued in the MC whih omputes the assignment of. After reordering in step 2) the next seleted multiplexer node is not neessarily labeled by k. gorithm the funtion represented by the remaining BDD is totally symmetri, suh that hanging the position of a variable does not hange the BDD size, i.e. in formula only the seond part onerning depth plays any role. Starting from a BDD with linear depth our algorithm onstruts step by step a MC for the same funtion. The resulting MC has logarithmi depth. The improvement on the depth is due to the fat that intermediate variables are used as selet inputs of multiplexers in our approah. 5 Experimental Results In this setion we present our results for PTL synthesis using the MC optimization algorithm of Setion 4. or our experiments we use the implementation of [6] whih is integrated in the sis environment [8]. Buh et al. [6] transform a Boolean iruit into a so-alled deomposed BDD to prevent a size explosion of a monolithi BDD approah. BDDs are onstruted starting from the inputs. When a ertain size or depth limit of the resulting BDD would be reahed, an intermediate variable or ut point is introdued. The result is a set of lusters of the iruit, whih are represented by BDDs depending on primary input variables or intermediate ut point variables. After that in [6] the BDDs for these lusters are mapped to PTL. A PTL ell is omputed for eah luster. To ope with the quadrati delay of transistors in series buffers are inserted for the outputs of the PTL ells. In this paper we replae the BDD based PTL mapping of [6] by an MC based mapping as desribed in Setion 4. (Of ourse our MC optimization approah an also be used as a post-proessing step of other BDD based PTL synthesis tools like [, 8] to optimize the PTL ells originating from BDD representations.) In the following we will all our synthesis tool, whih uses an MC based PTL mapping, m map. Sine the lusters produed by [6] are very small (the depth of the BDDs is not larger than 3) and we made the experiene that the optimization potential of the MC approah an be inreased using larger lusters, we also present results for a seond version of our MC based PTL mapping tool, whih first enlarges the lusters to some extent to inrease the optimization potential. In this version we remove ut point variables by omposition as long as the overall BDD size will not inrease in this way and as long as a maximum BDD size for a luster is not exeeded (in our experiments we use a limit of ). In the following we will all this seond version of our PTL synthesis tool m map+. We tried two different optimization strategies: optimization only for area (weight α =., see Setion 4) and optimization for a ombination of area and depth with α =.2. Our depth minimization makes use of depth information assigned to the already onstruted MC part as desribed in Setion 4. As already proposed in [6], we an additionally use also depth informations for the inputs of the luster, whih is presently optimized, sine the lusters whih ompute these input signals are optimized before. We start with Table whih shows the results of m map and m map+ using area optimization (α =.) for IS- CAS89 benhmarks and ompare them to the initial solution of the tool from [6]. Columns 2 4 show the results of the tool from [6], olumns 5 8 the results of our tool m map with area minimization and olumns 9 2 the results of m map+ with area optimization. Columns

5 replaement replaement x x 3 x 5 x 7 ) x x 3 x 5 x 7 ) 2) 3) x x x x 6 6 x 3 x 3 x 5 4 x x x 8 x x 8 6 x 7 x 7 replaement replaement x 3 x x 7 x x 3 x x 7 x ) ) 2 5 x 5 2 x 7 x 3 x ) x 4 x 3 3 x 5 2 x 7 result, replaement,, replaement replaement igure 4. Computation of an MC for exor(x,..., ). Here we use BDDs with omplement edges. The numbers beside the BDD nodes represent the depth information whih is assigned to the nodes and whih is used by delay. mux/inv give the numbers of multiplexers and inverters of the result, olumns area give the ative transistor area for a realization using only NMOS transistors (the size of an NMOS transistor is assumed to be.5λ λ) and olumns md give the maximum number of multiplexers on a path from primary inputs to primary outputs. Both [6] and our tool use buffer insertion to fore the maximum number of transistors in series to be 3. The experiments were performed on a SPARC Ultra 4 and we use Long s BDD pakage [4] for our implementation. Columns time give CPU times in seonds to transform the BDDs into MCs. The experiments prove that there is indeed a high optimization potential of MC minimization ompared to BDD minimization: Our area minimization is able to ahieve onsiderable improvements on the multiplexer/inverter ounts and thus also on the transistor area in omparison to [6]. In all ases the multiplexer ounts are improved (up to 2.7% for C7552 and m map and up to 39.3% for C7552 and m map+). On the average the multiplexer and inverter ounts are improved by 2.% and 6.% respetively by m map and by 28.4% and 32.2% respetively by m map+. The transistor area is improved by 4.5% by m map and by 3.8% by m map+. Interestingly already the area optimization is able to improve the depths of the PTL iruits in 8 out of ases for m map and in 9 out of ases for m map+. The overall depth improvement for m map is 3.2% and for m map+ the overall improvement is 2.9%. The results for our ombined area and depth minimization an be found in Table 2, whih has the same struture as Table. As expeted, the ombined area and delay optimization needs slightly more area than our results for pure area minimization, but is still better than the results of [6]. (It remains an average area improvement of 6.2% for m map and 2.6% for m map+.) The experiments show that we an really exploit an area/depth trade off by our parameter for delay. In all ases the depth results of [6] are improved (up to 3.3% for C88 and m map and up to 4.6% for C88 and m map+) while maintaining better area results. On the average the depth results of the area optimization are further improved by 22.4% for m map (24. % for m map+), suh that ompared to [6] m map ould improve the depth by 24.9% and m map+ ould improve depth by 33.8%. As already mentioned, an inspetion of the resulting MC iruits of our optimization algorithm shows, that they are

6 Berkeley m map (area) m map+ (area) iruit mux/inv area md mux/inv area md time mux/inv area md time C7 7/ / / C432 27/ / / C499 44/ / / C88 354/ / / C355 5/ / / C98 46/ / / C / / / C354 2/ / / C535 92/ / / C / / / C / / / / / / Table. Comparison for PTL synthesis (area optimization, α =.). Berkeley m map (depth) m map+ (depth) iruit mux/inv area md mux/inv area md time mux/inv area md time C7 7/ / / C432 27/ / / C499 44/ / / C88 354/ / / C355 5/ / / C98 46/ / / C / / / C354 2/ / / C535 92/ / / C / / / C / / / / / / Table 2. Comparison for PTL synthesis (depth optimization, α =.2). substantially different from BDD realizations, sine we get rid both of the ordering restrition and the restrition to MCs with only input variables as seletor inputs of the multiplexers. Thus, we really obtained a general MC struture by using algorithms working on the (restrited) BDD strutures. 6 Conlusions and uture Work In this paper we presented for the first time an automati PTL synthesis approah whih is based on general Multiplexer Ciruits rather than on BDDs. Our experiments show, that we are able to exploit the additional degrees of freedom both for area and delay optimization. These degrees of freedom arise from removing restritions of BDDs, whih are important for verifiation appliations, but not for PTL synthesis. We put our experiments on top of the results of [6], but it is obvious, that our MC optimization approah an also be used as a post-proessing step of other BDD based PTL synthesis tools like [, 8] to optimize the PTL ells originating from BDD representations. As a future work we plan to inorporate don t are onditions into our approah. Don t ares an be used to minimize the BDD part during the MC omputation using methods from [7, 9, 7]. There are two types of don t are informations during MC omputation for a luster of the iruit: satisfiability and observability don t ares whih originate from the environment of the luster and don t ares whih originate from the MC part of the luster that is already omputed. Referenes [] P. Ashar, A. Ghosh, and S. Devadas. Boolean satisfiability and equivalene heking using general binary deision diagrams. In Int l Conf. on CAD, 99. [2] J. Bern, J. Gergov, C. Meinel, and A. Slobodová. Boolean manipulation with free BDD s. irst experimental results. In European Design & Test Conf., pages 2 27, 994. [3] V. Bertao, S. Minato, P. Verplaetse, L. Benini, and G. De Miheli. Deision diagrams and pass transistor logi synthesis. In Int l Workshop on Logi Synth., 997.

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