SEQ without stages. valc register file ALU. Stat ZF/SF. instr. length PC+9. R[srcA] R[srcB] srca srcb dstm dste. Data in Data out. Instr. Mem.
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- Lawrence Sharp
- 5 years ago
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Transcription
1 Exam Review 1
2 SEQ without stages 2 0xF 0xF %rsp valc register file PC+9 PC + Instr. Mem. instr. length ra rb %rsp 0xF 0xF %rsp srca srcb dstm dste R[srcA] R[srcB] next R[dstM] next R[dstE] 0 8 ALU alua vale alub add/sub xor/and (function of instr.) Data in Data out Addr Mem. in write? function of opcode Stat ZF/SF
3 SEQ with stages fetch decode 0xF 0xF %rsp valc register file execute PC+9 memory PC + Instr. Mem. instr. length ra rb %rsp 0xF 0xF %rsp srca srcb dstm dste R[srcA] R[srcB] next R[dstM] next R[dstE] 0 8 ALU alua vale alub add/sub xor/and (function of instr.) Data in Data out Addr Mem. in write? function of opcode Stat ZF/SF writeback 3
4 SEQ with stages fetch decode 0xF 0xF %rsp valc register file execute PC+9 memory PC + Instr. Mem. instr. length ra rb %rsp 0xF 0xF %rsp srca srcb dstm dste R[srcA] R[srcB] next R[dstM] next R[dstE] 0 8 ALU alua vale alub add/sub xor/and (function of instr.) Data in Data out Addr Mem. in write? function of opcode Stat ZF/SF writeback 3
5 SEQ with stages %rsp 0xF rule: signal to next stage (except flow control) fetch decode 0xF valc register file execute PC+9 memory PC + Instr. Mem. instr. length ra rb %rsp 0xF 0xF %rsp srca srcb dstm dste R[srcA] R[srcB] next R[dstM] next R[dstE] 0 8 ALU alua vale alub add/sub xor/and (function of instr.) Data in Data out Addr Mem. in write? function of opcode Stat ZF/SF writeback 3
6 SEQ with stages (actually sequential) fetch PC + Instr. Mem. instr. length decode ra rb %rsp 0xF 0xF %rsp 0xF 0xF %rsp valc register file srca srcb dstm dste R[srcA] R[srcB] next R[dstM] next R[dstE] 0 writeback execute 8 ALU alua vale alub add/sub xor/and (function of instr.) PC+9 memory Data in Data out Addr Mem. in write? function of opcode Stat ZF/SF 4
7 adding pipeline registers fetch decode 0xF 0xF %rsp valc register file execute PC+9 memory PC + Instr. Mem. instr. length ra rb %rsp 0xF 0xF %rsp srca srcb dstm dste R[srcA] R[srcB] next R[dstM] next R[dstE] 0 8 ALU alua vale alub add/sub xor/and (function of instr.) Data in Data out Addr Mem. in write? function of opcode Stat ZF/SF writeback 5
8 adding pipeline registers decode not shown control logic fetch 0xF 0xF %rsp valc register file execute PC+9 memory PC + Instr. Mem. instr. length ra rb %rsp 0xF 0xF %rsp srca srcb dstm dste R[srcA] R[srcB] next R[dstM] next R[dstE] 0 8 ALU alua vale alub add/sub xor/and (function of instr.) Data in Data out Addr Mem. in write? function of opcode Stat ZF/SF writeback 5
9 pipeline with different hazards 6 example: 4-stage pipeline: fetch/decode/execute+memory/writeback // 4 stage // 5 stage addq %rax, %r8 // // W subq %rax, %r9 // W // M xorq %rax, %r10 // EM // E andq %r8, %r11 // D // D
10 pipeline with different hazards 6 example: 4-stage pipeline: fetch/decode/execute+memory/writeback // 4 stage // 5 stage addq %rax, %r8 // // W subq %rax, %r9 // W // M xorq %rax, %r10 // EM // E andq %r8, %r11 // D // D addq/andq is hazard with 5-stage pipeline addq/andq is not a hazard with 4-stage pipeline
11 exercise: different pipeline 7 split execute into two stages: F/D/E1/E2/M/W result only available after second execute stage where does forwarding, stalls occur? cycle # addq %rcx, %r9 F D E1 E2 M W addq %r9, %rbx F D D E1 E2 M W addq %rax, %r9 F F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W
12 exercise: different pipeline 8 split execute into two stages: F/D/E1/E2/M/W cycle # addq %rcx, %r9 F D E1 E2 M W addq %r9, %rbx F D E1 E2 M W addq %r9, %rbx F D D E1 E2 M W addq %rax, %r9 F D E1 E2 M W addq %rax, %r9 F F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W
13 exercise: different pipeline 8 split execute into two stages: F/D/E1/E2/M/W cycle # addq %rcx, %r9 F D E1 E2 M W addq %r9, %rbx F D E1 E2 M W addq %r9, %rbx F D D E1 E2 M W addq %rax, %r9 F D E1 E2 M W addq %rax, %r9 F F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W
14 exercise: different pipeline 8 split execute into two stages: F/D/E1/E2/M/W cycle # addq %rcx, %r9 F D E1 E2 M W addq %r9, %rbx F D E1 E2 M W addq %r9, %rbx F D D E1 E2 M W addq %rax, %r9 F D E1 E2 M W addq %rax, %r9 F F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W
15 exercise: different pipeline 8 split execute into two stages: F/D/E1/E2/M/W cycle # addq %rcx, %r9 F D E1 E2 M W addq %r9, %rbx F D E1 E2 M W addq %r9, %rbx F D D E1 E2 M W addq %rax, %r9 F D E1 E2 M W addq %rax, %r9 F F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W
16 exercise: different pipeline 8 split execute into two stages: F/D/E1/E2/M/W cycle # addq %rcx, %r9 F D E1 E2 M W addq %r9, %rbx F D E1 E2 M W addq %r9, %rbx F D D E1 E2 M W addq %rax, %r9 F D E1 E2 M W addq %rax, %r9 F F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W rmmovq %r9, (%rbx) F D E1 E2 M W
17 ex.: dependencies and hazards (1) 9 addq %rax, %rbx subq %rax, %rcx irmovq $100, %rcx addq %rcx, %r10 addq %rbx, %r10 where are dependencies? which are hazards in our pipeline? which are resolved with forwarding?
18 ex.: dependencies and hazards (1) 9 addq %rax, %rbx subq %rax, %rcx irmovq $100, %rcx addq %rcx, %r10 addq %rbx, %r10 where are dependencies? which are hazards in our pipeline? which are resolved with forwarding?
19 ex.: dependencies and hazards (1) 9 addq %rax, %rbx subq %rax, %rcx irmovq $100, %rcx addq %rcx, %r10 addq %rbx, %r10 where are dependencies? which are hazards in our pipeline? which are resolved with forwarding?
20 ex.: dependencies and hazards (1) 9 addq %rax, %rbx subq %rax, %rcx irmovq $100, %rcx addq %rcx, %r10 addq %rbx, %r10 where are dependencies? which are hazards in our pipeline? which are resolved with forwarding?
21 ex.: dependencies and hazards (2) 10 mrmovq 0(%rax) %rbx addq %rbx %rcx foo: jne foo addq %rcx %rdx mrmovq (%rdx) %rcx where are dependencies? which are hazards in our pipeline? which are resolved with forwarding?
22 11 adding associativity 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value multiple places to put values with same index avoid conflict misses
23 11 adding associativity 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value set set
24 adding associativity 11 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value way 0 way
25 11 adding associativity 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value m = 8 bit addresses S = 2 = 2 s sets s = 1 (set) index bits B = 2 = 2 b byte block size b = 1 (block) offset bits t = m (s + b) = 6 tag bits
26 adding associativity 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value mem[0x00] 0 mem[0x01] address (hex) result (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset 11
27 adding associativity 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value mem[0x00] 0 mem[0x01] address (hex) result (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset 11
28 adding associativity 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value mem[0x00] mem[0x01] mem[0x62] mem[0x63] 0 address (hex) result (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset 11
29 adding associativity index valid tag value valid tag value mem[0x00] mem[0x01] mem[0x62] mem[0x63] address (hex) 2-way set associative, 2 byte blocks, 2 sets result mem[0x60] mem[0x61] (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset 11
30 adding associativity index valid tag value valid tag value mem[0x00] mem[0x01] mem[0x62] mem[0x63] address (hex) 2-way set associative, 2 byte blocks, 2 sets result mem[0x60] mem[0x61] (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset 11
31 adding associativity index valid tag value valid tag value mem[0x00] mem[0x01] mem[0x62] mem[0x63] address (hex) 2-way set associative, 2 byte blocks, 2 sets result mem[0x60] mem[0x61] (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset 11
32 adding associativity 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value mem[0x00] mem[0x01] mem[0x62] mem[0x63] mem[0x60] mem[0x61] 0 address (hex) result (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset needs to replace block in set 0! 11
33 adding associativity index valid tag value valid tag value mem[0x00] mem[0x01] mem[0x62] mem[0x63] address (hex) 2-way set associative, 2 byte blocks, 2 sets result mem[0x60] mem[0x61] (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss tag indexoffset 11
34 cache operation (associative) index offset valid tag data valid tag data AA BB tag 1 11 B4 B = data (B5) AND = AND OR is hit? (1)
35 cache operation (associative) index offset valid tag data valid tag data AA BB tag 1 11 B4 B = data (B5) AND = AND OR is hit? (1)
36 cache operation (associative) index offset valid tag data valid tag data AA BB tag 1 11 B4 B = data (B5) AND = AND OR is hit? (1)
37 associative lookup possibilities 13 none of the blocks for the index are valid none of the valid blocks for the index match the tag something else is stored there one of the blocks for the index is valid and matches the tag
38 Tag-Index-Offset formulas (complete) 14 m memory addreses bits (Y86-64: 64) E number of blocks per set ( ways ) S = 2 s number of sets s (set) index bits B = 2 b block size b (block) offset bits t = m (s + b) tag bits C = B S E cache size (excluding metadata)
39 replacement policies 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value LRU mem[0x00] mem[0x01] mem[0x60] mem[0x61] mem[0x62] mem[0x63] 0 1 address (hex) result (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss how to decide where to insert 0x64? 15
40 replacement policies 2-way set associative, 2 byte blocks, 2 sets index valid tag value valid tag value LRU mem[0x00] mem[0x01] mem[0x60] mem[0x61] mem[0x62] mem[0x63] 0 1 address (hex) result (00) miss (01) hit (63) miss (61) miss (62) hit (00) hit (64) miss track which block was read least recently updated on every access 15
41 example replacement policies 16 least recently used and approximations take advantage of temporal locality exact: log 2 (E!) bits per set for E-way cache good approximations: E to 2E bits first-in, first-out counter per set where to replace next (pseudo-)random no extra information!
42 write-through v. write-back 17 option 1: write-through 1 write 10 to 0xABCD CPU Cache ABCD: FF RAM 11CD: 42 ABCD: FF
43 write-through v. write-back 17 option 1: write-through 1 write 10 to 0xABCD 2 write 10 to 0xABCD CPU Cache ABCD: 10 RAM 11CD: 42 ABCD: 10
44 write-through v. write-back 17 option 2: write-back 1 write 10 to 0xABCD CPU Cache ABCD: 10 (dirty) RAM 11CD: 42 ABCD: FF
45 write-through v. write-back option 2: write-back 1 write 10 to 0xABCD 3 write 10 to ABCD CPU 2 read Cache from ABCD: 10 0x11CD (dirty) (conflicts) when replaced send value to memory RAM 11CD: 42 ABCD: 10 17
46 write-through v. write-back 17 1 write 10 to 0xABCD 3 write 10 to ABCD CPU 2 Cache 4 read read RAM ABCD: 10 from from (dirty) 11CD: 42 0x11CD 0x11CD ABCD: 10 (conflicts) read new value to store in cache
47 18 writeback policy changed value! 2-way set associative, 4 byte blocks, 2 sets index valid tag value dirty valid tag value dirty LRU mem[0x00] mem[0x01] mem[0x60]* mem[0x61]* mem[0x62] mem[0x63] = dirty (different than memory) needs to be written if evicted
48 allocate on write? 19 processor writes less than whole cache block block not yet in cache two options: write-allocate fetch rest of cache block, replace written part write-no-allocate send write through to memory guess: not read soon?
49 20 write-allocate 2-way set associative, LRU, writeback index valid tag value dirty valid tag value dirty LRU mem[0x00] mem[0x01] mem[0x60]* mem[0x61]* mem[0x62] mem[0x63] writing 0xFF into address 0x04? index 0, tag
50 20 write-allocate 2-way set associative, LRU, writeback index valid tag value dirty valid tag value dirty LRU mem[0x00] mem[0x01] mem[0x60]* mem[0x61]* mem[0x62] mem[0x63] writing 0xFF into address 0x04? index 0, tag step 1: find least recently used block
51 20 write-allocate 2-way set associative, LRU, writeback index valid tag value dirty valid tag value dirty LRU mem[0x00] mem[0x01] mem[0x60]* mem[0x61]* mem[0x62] mem[0x63] writing 0xFF into address 0x04? index 0, tag step 1: find least recently used block step 2: possibly writeback old block
52 20 write-allocate 2-way set associative, LRU, writeback index valid tag value dirty valid tag value dirty LRU mem[0x00] mem[0x01] xFF mem[0x05] mem[0x62] mem[0x63] writing 0xFF into address 0x04? index 0, tag step 1: find least recently used block step 2: possibly writeback old block step 3a: read in new block to get mem[0x05] step 3b: update LRU information
53 21 write-no-allocate 2-way set associative, LRU, writeback index valid tag value dirty valid tag value dirty LRU mem[0x00] mem[0x01] mem[0x60]* mem[0x61]* mem[0x62] mem[0x63] writing 0xFF into address 0x04? step 1: is it in cache yet? step 2: no, just send it to memory
54 fast writes 22 write 10 to 0xABCD write buffer 0xABCD: 10 0x1234: 20 CPU write 20 to 0x1234 Cache RAM write appears to complete immediately when placed in buffer memory can be much slower
55 exercise (1) 23 initial cache: 64-byte blocks, 64 sets, 8 ways/set If we leave the other parameters listed above unchanged, which will probably reduce the number of capacity misses in a typical program? (Multiple may be correct.) A. quadrupling the block size (256-byte blocks, 64 sets, 8 ways/set) B. quadrupling the number of sets C. quadrupling the number of ways/set
56 exercise (2) 24 initial cache: 64-byte blocks, 8 ways/set, 64KB cache If we leave the other parameters listed above unchanged, which will probably reduce the number of capacity misses in a typical program? (Multiple may be correct.) A. quadrupling the block size (256-byte block, 8 ways/set, 64KB cache B. quadrupling the number of ways/set C. quadrupling the cache size
57 exercise (3) 25 initial cache: 64-byte blocks, 8 ways/set, 64KB cache If we leave the other parameters listed above unchanged, which will probably reduce the number of conflict misses in a typical program? (Multiple may be correct.) A. quadrupling the block size (256-byte block, 8 ways/set, 64KB cache B. quadrupling the number of ways/set C. quadrupling the cache size
58 C and cache misses (1) 26 int array[1024]; // 4KB array int even_sum = 0, odd_sum = 0; for (int i = 0; i < 1024; i += 2) { even_sum += array[i + 0]; odd_sum += array[i + 1]; } Assume everything but array is kept in registers (and the compiler does not do anything funny). How many data cache misses on a 2KB direct-mapped cache with 16B cache blocks?
59 C and cache misses (2) 27 int array[1024]; // 4KB array int even_sum = 0, odd_sum = 0; for (int i = 0; i < 1024; i += 2) even_sum += array[i + 0]; for (int i = 1; i < 1024; i += 2) odd_sum += array[i + 1]; Assume everything but array is kept in registers (and the compiler does not do anything funny). How many data cache misses on a 2KB direct-mapped cache with 16B cache blocks? Would a set-associtiave cache be better?
60 thinking about cache storage (1) 28 2KB direct-mapped cache with 16B blocks set 0: address 0 to 15, (0 to 15) + 2KB, (0 to 15) + 4KB, set 1: address 16 to 31, (16 to 31) + 2KB, (16 to 31) + 4KB, set 127: address 2032 to 2047, (2032 to 2047) + 2KB,
61 thinking about cache storage (1) 28 2KB direct-mapped cache with 16B blocks set 0: address 0 to 15, (0 to 15) + 2KB, (0 to 15) + 4KB, set 1: address 16 to 31, (16 to 31) + 2KB, (16 to 31) + 4KB, set 127: address 2032 to 2047, (2032 to 2047) + 2KB,
62 thinking about cache storage (1) 28 2KB direct-mapped cache with 16B blocks set 0: address 0 to 15, (0 to 15) + 2KB, (0 to 15) + 4KB, block at 0: array[0] through array[3] set 1: address 16 to 31, (16 to 31) + 2KB, (16 to 31) + 4KB, block at 16: array[4] through array[7] set 127: address 2032 to 2047, (2032 to 2047) + 2KB, block at 2032: array[508] through array[511]
63 thinking about cache storage (1) 2KB direct-mapped cache with 16B blocks set 0: address 0 to 15, (0 to 15) + 2KB, (0 to 15) + 4KB, block at 0: array[0] through array[3] block at 0+2KB: array[512] through array[515] set 1: address 16 to 31, (16 to 31) + 2KB, (16 to 31) + 4KB, block at 16: array[4] through array[7] block at 16+2KB: array[516] through array[519] set 127: address 2032 to 2047, (2032 to 2047) + 2KB, block at 2032: array[508] through array[511] block at KB: array[1020] through array[1023] 28
64 thinking about cache storage (2) 29 2KB 2-way set associative cache with 16B blocks: block addresses set 0: address 0, 0 + 2KB, 0 + 4KB, set 1: address 16, KB, KB, set 63: address 1008, KB, KB
65 thinking about cache storage (2) 2KB 2-way set associative cache with 16B blocks: block addresses set 0: address 0, 0 + 2KB, 0 + 4KB, block at 0: array[0] through array[3] set 1: address 16, KB, KB, address 16: array[4] through array[7] set 63: address 1008, KB, KB address 1008: array[252] through array[255] 29
66 thinking about cache storage (2) 2KB 2-way set associative cache with 16B blocks: block addresses set 0: address 0, 0 + 2KB, 0 + 4KB, block at 0: array[0] through array[3] block at 0+1KB: array[256] through array[259] block at 0+2KB: array[512] through array[515] set 1: address 16, KB, KB, address 16: array[4] through array[7] set 63: address 1008, KB, KB address 1008: array[252] through array[255] 29
67 thinking about cache storage (2) 2KB 2-way set associative cache with 16B blocks: block addresses set 0: address 0, 0 + 2KB, 0 + 4KB, block at 0: array[0] through array[3] block at 0+1KB: array[256] through array[259] block at 0+2KB: array[512] through array[515] set 1: address 16, KB, KB, address 16: array[4] through array[7] set 63: address 1008, KB, KB address 1008: array[252] through array[255] 29
68 C and cache misses (3) typedef struct { int a_value, b_value; int boring_values[126]; } item; item items[8]; // 4 KB array int a_sum = 0, b_sum = 0; for (int i = 0; i < 8; ++i) a_sum += items[i].a_value; for (int i = 0; i < 8; ++i) b_sum += items[i].b_value; Assume everything but items is kept in registers (and the compiler does not do anything funny). How many data cache misses on a 2KB direct-mapped cache with 16B cache blocks? 30
69 C and cache misses (3, rewritten?) 31 item array[1024]; // 4 KB array int a_sum = 0, b_sum = 0; for (int i = 0; i < 1024; i += 128) a_sum += array[i]; for (int i = 1; i < 1024; i += 128) b_sum += array[i];
70 C and cache misses (4) typedef struct { int a_value, b_value; int boring_values[126]; } item; item items[8]; // 4 KB array int a_sum = 0, b_sum = 0; for (int i = 0; i < 8; ++i) a_sum += items[i].a_value; for (int i = 0; i < 8; ++i) b_sum += items[i].b_value; Assume everything but items is kept in registers (and the compiler does not do anything funny). How many data cache misses on a 4-way set associative 2KB direct-mapped cache with 16B cache blocks? 32
71 a note on matrix storage 33 A N N matrix represent as array makes dynamic sizes easier: float A_2d_array[N][N]; float * A_flat = malloc(n * N); A_flat[i * N + j] === A_2d_array[i][j]
72 locality exercise (1) 34 /* version 1 */ for (int i = 0; i < N; ++i) for (int j = 0; j < N; ++j) A[i] += B[j] * C[i * N + j] /* version 2 */ for (int j = 0; j < N; ++j) for (int i = 0; i < N; ++i) A[i] += B[j] * C[i * N + j]; exercise: which has better temporal locality in A? in B? in C? how about spatial locality?
73 array usage: block 35 A ik block (I K) A kj block (K J) B ij block (I J) inner loop keeps blocks from A, B in cache
74 array usage: block 35 A ik block (I K) A kj block (K J) B ij block (I J) B ij calculation uses strips from A K calculations for one load (cache miss)
75 array usage: block 35 A ik block (I K) A kj block (K J) B ij block (I J) A ik calculation uses strips from A, B J calculations for one load (cache miss)
76 array usage: block 35 A ik block (I K) A kj block (K J) B ij block (I J) (approx.) KIJ fully cached calculations for KI + IJ + KJ loads (assuming everything stays in cache)
77 cache blocking efficiency 36 load I K elements of A ik : do > J multiplies with each load K J elements of A kj : do I multiplies with each load I J elements of B ij : do K adds with each bigger blocks more work per load! catch: IK + KJ + IJ elements must fit in cache
78 cache blocking rule of thumb 37 fill the most of the cache with useful data and do as much work as possible from that example: my desktop 32KB L1 cache I = J = K = 48 uses elements, or 27KB. assumption: conflict misses aren t important
79 flat 2D arrays and cache blocks 38 A[0] A[N] A x0 A xn
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