An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture

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1 A Efficiet Implemetatio Method of Fractal Image Compressio o Dyamically Recofigurable Architecture Hidehisa Nagao, Akihiro Matsuura, ad Akira Nagoya NTT Commuicatio Sciece Laboratories 2-4 Hikaridai, Seika-cho, Soraku-gu, Kyoto, , JAPAN fagao, matsuura, agoyag@cslab.kecl.tt.co.jp Abstract. This paper proposes a method for implemetig fractal image compressio o dyamically recofigurable architecture. I the ecodig of this compressio, metric computatios amog image blocks are the most time cosumig. I our method, processig elemets (PEs) cofigured for each image block perform these computatios i a pipelie maer. By cofigurig PEs, we ca reduce the umber of adders, which are the mai computig elemets, by half eve i the worst case. This reductio icreases the umber of PEs that work i parallel. I additio, dyamic recofigurability of hardware is employed to omit useless metric computatios. Experimetal results show that the resources for implemetig the PEs are reduced to 60 to 70% ad the omissio of useless metric computatios reduces the ecodig time to 10 to 55%. 1 Itroductio Due to recet advaces i programmable logic devices such as Field Programmable Gate Arrays (FPGAs), recofigurable computig has become a realistic computig paradigm [1]. Some recofigurable devices have begu to support dyamic ad partial recofiguratio [2][3], ad recet research has made use of such recofigurability to accelerate solvig problems [4]. I this paper, we focus o the acceleratio of fractal image compressio usig dyamically recofigurable computig. Fractal image compressio [5] is expected to be a promisig compressio method for digital images i terms of its high compressio ratios ad fidelity. However, due to the uacceptable ecodig time, use of this compressio method is limited to areas where the ecodig time is ot critical. Therefore, acceleratio of the ecodig is idispesable to a variety of uses. I fractal-based image ecodig, a image is divided ito sub-blocks ad the root mea square metrics amog them are computed. These metric computatios carry the burde i ecodig the etire image because umerous metric computatios for the sub-blocks must be doe. I our method, processig elemets (PEs) are devoted to the correspodig subblocks. Each PE computes the metrics betwee the correspodig sub-blocks ad the cadidate sub-blocks i the pipelie. I each step of the pipelie, oe metric computatio is executed o a PE. I additio, plural PEs implemeted o the recofigurable architecture cocurretly perform the metric computatios. Our method has two advatages owig to the recofigurability of the hardware. Oe advatage is the structure of PEs. Sice each PE is recofigured for a sub-block, a umber of multiplicatios i the metric computatios ca be regarded as costat multiplicatios. This makes it possible to use shifts ad adders istead of variableby-variable geeral-purpose multipliers. By usig costat multiplicatios, the umber

2 of adders eeded for PEs is reduced, eve i the worst case, to half that of PEs i the straightforward implemetatio. This reduces the recofigurable resources eeded for the PE, ad cosequetly icreases the umber of PEs that work i parallel. The secod advatage is the omissio of useless metric computatios. We ca accelerate the ecodig by omittig metric computatios that do ot ifluece the fidelity of the decoded image. Such omissio ca be achieved by the partial recofiguratio of the hardware. Experimetal results show that the resources eeded to implemet the PEs ca be reduced to approximately 60 to 70% of the straightforward implemetatio, eve i the worst case. Results also show that omittig useless computatios reduces the ecodig time to 10 to 55%. Thus, our method utilizig recofigurability sigificatly accelerates the ecodig. This paper is orgaized as follows. Sect. 2 briefly describes fractal image compressio. I Sect. 3, we preset a dyamically recofigurable architecture of the ecoder for fractal image compressio. I Sect. 4, experimetal results are show ad aalyzed. Sect. 5 cocludes this paper. 2 Fractal Image Compressio I this sectio, we describe the outlie of fractal image compressio. A fractal-based image ecodig scheme was first promoted by M. Barsley [6]. The fractal image compressio for grey-scale images was developed by A. Jacqui. For a detailed survey ad extesios of fractal image compressio, we refer readers to a paper by Jacpui [7]. 2.1 Iterated Fuctio System (IFS) Here, we briefly preset the uderlyig mathematical priciples of fractal image compressio based o a theory of IFS [8][9]. A IFS cosists of a collectio of cotractive affie trasformatios fw i : M! Mj1 i mg, where w i maps a metric space M to itself. A trasformatio w is said to be cotractive whe there is a costat umber s(0 s<1) ad d(w(1);w(2)) sd(1;2) holds for ay poits 1;2 2 M, where d(1;2) deotes the S metric betwee 1 ad 2. The collectio of trasformatios defies a map W (S) = i=1 w i(s), where S M. Note that the map W is applied ot m to the set of poits i M but to the set of sub-sets i M. Let W be a cotractive map o a compact metric space of images with the bouded itesity, the the Cotractive Mappig Fixed-Poit Theorem asserts that there is oe special image x W, called the attractor, with the followig properties. 1. W (x W ) = x W : 2. x W = lim!1 W (S0), which is idepedet of the choice of a iitial image S0. Fractal image compressio relies o this theorem. Suppose the attractor of a cotractive map W is the origial image to be compressed. From property 2, the origial image is obtaied from ay iitial image by applyig W. The goal of fractal image compressio is to fid the cotractive map W whose attractor is sufficietly close to the origial image ad to store the parameters of W istead of the itesity values. 2.2 Image Compressio Usig IFS The fractal image compressio algorithm we focus o is based o the quad-tree decompositio scheme [5][8]. This scheme was developed for grey-scale images. Let R1;R2;:::;R p be o-overlappig sub-squares of B 2 B pixels i a image. These sub-squares are called rage blocks. The uio of the set of rage blocks covers

3 the etire image. All 2B 2 2B sub-squares, D1;D2;:::;D q, are called domai blocks, where all of the over-lappig sub-squares of this size are take ito accout. The collectio of all domai blocks is called the domai pool. The map W i Sect. 2.1 maps sub-sets of the domai pool to rage blocks. For each R k, we search for the domai block that approximates R k with the smallest metric out of the domai pool. A rage block that is approximated by a acceptable metric is said to be covered. A rage block for which acceptable domai blocks are ot foud is said to be ucovered. Note that before calculatig metrics, domai blocks are resized to the same size as rage blocks by averagig the itesity values of 222 pixels. Let the pixel itesities of the resized domai block be a1;a2;:::;a ad let those of the rage block be b1;b2;:::;b. The metric R(D P j ;R k ) betwee a domai block D j ad a rage block R k is defied as R(D j ;R k ) = i=1 (sa i + o 0 b i ) 2, where s is the scalig factor ad o is the offset factor. Differetiatig R by s ad o, s ad o that miimize R are calculated as P s = i=1 P P a ib i 0 i=1 ip a i=1 b i i=1 a2 0 (P i i=1 a i) 2 ; o = I this case, R(D j ;R k ) is calculated as X P P i=1 b i 0 s i=1 a i : (1) X R(D j ;R k ) = 1 ( b 2 i 0 ( b i ) 2 ) 0 s2 X i=1 i=1 ( a 2 i 0 ( a i ) 2 ): (2) i=1 i=1 The etire fractal image compressio scheme is show i Fig. 1. We call this algorithm EXAUS. The parameter tolerace settles the compressio ratio ad the fidelity. If a rage block is ucovered, that is, if tolerace is violated for all domai blocks, the rage block is divided ito four smaller rage blocks ad the best-match domais for these smaller rage blocks are searched. I this case, domai blocks with half the size i the side legth are evaluated. To icrease the probability of fidig good rage-domai matches, the domai pool may iclude sub-squares obtaied by rotatig domai blocks 90, 180, 270 ad 360 ad flippig them vertically (eight trasformatios). These sub-blocks are also called domai blocks. After fidig the best matches for all rage blocks, s ad o ad the umber specifyig the best-match domai block are stored for each rage block istead of their pixel itesities; as such, the ecodig is completed. For s ad o, the ecessary bit widths to be preserved are empirically kow to be 5 ad 7, respectively. O the other had, for decodig the image, the correspodig trasformatios are repeated. This iteratio is started from ay iitial image. Iteratios of 10 to 20 times are sufficiet to decode a image with good fidelity. With regard to the computig time, the iteratios i the decodig are ot so troublesome. However, the ecodig time is ofte ot acceptable due to the may iteratios of complex metric computatios. For example, i ecodig a pixel image, the umber of rage blocks of 828 pixels is 1024 ad the umber of domai blocks of pixels is (ot icludig the domai blocks obtaied by rotatig ad flippig). Therefore, the total umber of iteratios is about 60 millio. For reducig the ecodig time, some schemes that try to reduce the umber of rage-domai comparisos have bee proposed [7]. I these schemes, oly rage-domai comparisos amog sub-blocks with the same characteristics are evaluated. Ufortuately, the ecodig times usig these schemes are still uacceptable. I the ext sectio, we propose a method for implemetig fractal image compressio usig parallel computatio o a recofigurable hardware. Our method has two X

4 advatageous features for reducig the ecodig time. The first oe cocers acceleratig the iside of the iermost loop of EXAUS by usig pipelie processig. I each step of the pipelie, oe iteratio is executed P o a PE. P Lookig at the equatios (1) (2), we ca observe that may computatios, i=1 a i, i=1 a2, (P i i=1 a i) 2 P P, i=1 b i, i=1 b2, (P i i=1 b i) 2 P, ( i=1 a2 0 (P i i=1 a i) 2 P ) ad ( i=1 b2 0 (P i i=1 b i) 2 ), ca be performed i advace out of the iermost loop ad have to be doe oly oce for each domai block ad rage block. Therefore, ievitable computatios iside of the iermost loop are other computatios P for s ad R ad comparisos. More precisely, the idispesable burde is the part i=1 a ib i. The method preseted i this paper lightes this burde by executig it i a pipelie. The secod feature cocers reducig the umber of iteratios of metric computatios. I EXAUS, the metric computatios for all pairs of rage ad domai blocks are doe. With regard to the fidelity of the decoded image, it is ot ecessary to evaluate all rage-domai matches. Our scheme omits these useless computatios. This omissio is owig to the dyamic ad partial recofigurability of the hardware. I the ext sectio, we describe these features i detail. mi R = tolerace; For (j = 1 ; j um rage ; j++) f For (k = 1 ; k um domai ; k++) f compute s; if (0 s < 1:0) if (R(D j ;R k ) < mi R) f mi R = R(D j ;R k ); best domai[j] = k; g g if (mi R == tolerace) set R j ucovered ad divide it ito 4 smaller blocks; g 3 Ecoder Architecture Fig. 1. Pseudocode of EXAUS. I this sectio, we propose a ecoder of fractal image compressio implemeted o dyamically recofigurable hardware. I this paper we assume that the dyamically recofigurable hardware is costructed from fie-grai programmable logic elemets (LEs) with a register ad programmable wires amog them such as Xilix XC6200 series FPGAs [2] or Atmel AT40K FPGAs [3]. We also suppose that these LEs ad wires ca be cofigured by settig cofiguratio data dyamically ad partially. Some kid of architectures of LEs have bee proposed such as Look-Up-Table (LUT) based architectures, multiplexer based architectures ad others. However, geeralizig these LEs as oly programmable logic fuctio uits with limited iputs ad a output, for example, 3 or 4 iputs, we cosider the ecoder architecture idepedet from the architectures of LEs ad realized as wired logic of LEs. 3.1 A Pipelied PE Network Fig. 2 shows the overview of the proposed ecoder implemeted o dyamically recofigurable hardware. The PE performs computatios iside the iermost loop of EXAUS. Each PE is devoted to a give rage block ad fids the best-match domai amog all domai blocks that are give through the data path i pipelie. I each step of the pipelie, oe iteratio of the iside of the iermost loop is executed o each PE. After fidig the best match, the PE iforms the best-match domai to the cotrol uit. The, the PE is recofigured for aother rage block with the cofiguratio data give

5 GRPDLQXQLW GRPDLQ GDWD FRQWUROXQLW cofiguratio data best-match domai EXIIHU 3( EXIIHU 3( EXIIHU 3( Y Dyamically recofigurable hardware GDWDSDWK FRQWUROSDWK Fig. 2. Overview of the Ecoder. by the cotrol uit. These PEs are recofigured util o ucovered rage block exists. All PEs are coected by the data path ad perform the calculatios i a pipelie maer while trasferrig the domai data. The domai uit iputs the domai data ito the PE etwork util all rage blocks are checked agaist all domai blocks. A buffer trasfers domai data to the PE coected with it ad the eighborig buffer through the data path without the pipelie stole durig the recofiguratio of that PE. 3.2 Dyamically Recofigurable PE Here, we describe the PE architecture i detail. A PE performs the calculatios iside of the iermost loop of EXAUS. As stated i Sect. 2.2, the computatio P P of i=1 a ib i is the burde for computig R. Therefore, it is desirable that i=1 a ib i is calculated i parallel. The basic implemetatio is show i Fig. 3. The parameters a1;a2;:::;a are eter the PE i parallel P P ad i=1 a ib i is calculated i the pipelie. The hardware compoet for calculatig i=1 a ib i is deoted by P1. The hardware compoet for calculatig s, o ad R is deoted by P2. P2 fids the miimum R ad stores the idetity umber of the domai block that provides it. These computatios are also performed i the pipelie. I each step of the pipelie, oe iteratio of the iside of the iermost loop P Pis completed o a PE. Precomputable parameters for the domai block, such as i=1 a i, i=1 a2 i ad others, are give to the PEs through the data path i parallel cooperatig with the pipelie. The other precomputable parameters for the rage block are stored i P2. I order to implemet P1, we eed multipliers ad 0 1 adders. O the other had, the computatios performed i P2 are three multiplicatios, three comparisos, ad oe divisio. Sice the hardware resources eeded for P2 ad the buffer are much smaller tha those for P1, it is importat to reduce the hardware resources for P1 for total resource reductio. By reducig the resources for a PE, we ca implemet may PEs at the same time ad icrease the umber of rage blocks processed i parallel. Now, we describe a efficiet implemetatio method usig recofigurability. Note that the multipliers i P1 i Fig. 3 are implemeted with adders ad shifts. Sice shifts are implemeted by wirig o recofigurable devices, it is importat to reduce the umber of adders. Therefore, we implemet P1 as follows. Let the iteger b i be preseted as b i;l b i;l01 111b i;1 i the biary presetatio, where b i;j is 0 or 1, ad let the bit width of a i s ad b i s be l. The, multiplicatio a i b i is preseted as a i b i = f(a i b i;l ) (l 0 1)g +f(a i b i;l02 ) (l 0 2)g +111+fa i b i;1g, where a j deotes the j-bit shift of a to the left. The multiplicatio is implemeted by l 0 1 adders. I this case, the umber of adders for computig P i=1 a ib i at P1 is (l 0 1) +( 0 1) = l0 1: (3) O the other had, i the case of recofigurig a PE for a rage block, we ca make use of the fact that b i;j is a costat. Namely, we ca get rid of the part (a i b i;j ) if b i;j is 0.

6 D D Q D Q D D D D Q D D ' M data path precomputable parameters E E E Q Q D L E L L 3 3 3( First, we rearrage P i=1 a ib i as follows. X Fig. 3. PE architecture. a i b i = f(a1b1;1 + a2b2; a b ;1)g i=1 + f(a1b1;2 + a2b2; a b ;2) 1g f(a1b1;j + a2b2;j a b ;j ) (j 0 1)g f(a1b1;l + a2b2;l a b ;l ) (l 0 1)g: (4) The term of the j-th row of (4), (a1b1;j + a2b2;j a b ;j ); (5) ca be computed i a differet way by ivertig b i;j s for all i, 1 i, as follows. X a i 0 (a1b1;j + a2b2;j a b ;j ): (6) i=1 If the umber of o-zero bits amog b1;j;b2;j;:::;b ;j is more tha 2, we cofigure P1 usig (6) istead of (5). This is doe for all j. The, the umber of adders eeded to implemet P1 is l (7) i the worst case. Therefore, the umber of adders is reduced at least by half. The worst case happes whe the umber of o-zero bits of b1;j;b2;j;:::;b ;j is 2 or 2 +1 for all j(1 j l). I practice, sice b i s (1 i ) are itesities of a sub-block of a digital image, b i;j s (1 i ) ted to be the same, especially whe j is close to l. Therefore, the worst case rarely happes ad the umber of adders is expected to be much smaller tha that of the worst case. I Sect. 4, the scheme s experimetal results showp the reductio of adders ad resources for the PE. i=1 a ib i discussed here ca be implemeted by distributed arithmetic (DA) usig memories [10], if LEs are LUT based ad ca be used as memories. This implemetatio ca be space efficiet. However, the space efficiecy is terribly affected by the umber of iputs, M, of LEs (i.e., the umber of cotet bits possible for a LUT). Whe M is 3, the DA implemetatio is ot comparable eve with the our worst case implemetatio for practical ad l. I additio, the DA implemetatio is limited to LUT based architectures. Therefore, we would ot adopt the DA implemetatio.

7 3.3 A Compressio Algorithm Usig Dyamic Recofiguratio Next, we describe the improvemet of EXAUS. We use the dyamic partial recofigurability of the pipelied PE etwork stated i Sect I this PE etwork, each PE ca be recofigured without the pipelie stole sice buffers trasfer the domai data. Therefore, all PEs do ot have to be recofigured at the same time. I EXAUS, all domai blocks are checked for each rage block. However, by choosig the appropriate tolerace ad fidig oly oe rage-domai match that accepts the tolerace for each rage block, we ca obtai a decoded image with sufficietly good fidelity. Geerally, the fidelity of the decoded image is evaluated with the sigal-to-oise ratio (SNR) defied as SNR = 10 log10 (dr(s)2 =d e (S;S 0 )) (db). Here, dr(s) is the dyamic rage of the origial image S ad d e (S;S 0 ) is P the metric betwee S ad the decoded image S 0. d e (S;S 0 ) is defied as d e (S;S 0 t ) = i=1 ( i 0 0 )2 i, where i s ad 0 s are pixel itesities of S ad i S0.ASNR of approximately 28 to 32 db is sufficiet for fie fidelity. Now, we preset the improved algorithm that omits the exhaustive rage-domai matches i Fig. 4. We call this algorithm OMIT. This improvemet ca be implemeted o hardware by dyamically ad partially recofigurig each PE as soo as the first acceptable rage-domai match is foud. For (j = 1 ; j um rage ; j++) f flag = 0; For (k = 1 ; k um domai ; k++) f compute s; if (0 s < 1:0) if (R(D j ;R k ) < tolerace) f best domai[j] = k; flag = 1; break; g g if (flag == 0) set R j ucovered ad divide it ito 4 smaller blocks; g 4 Experimets Fig. 4. Pseudocode of OMIT. 4.1 Resources for PE First, we evaluate the umber of adders eeded to implemet a P1 ad the resources for PEs. Table 1 shows the umber of adders eeded to implemet P1 whe the rage size is 424 pixels ad 828 pixels for two bechmark images, Girl ( pixels, 8 b/p) of SIDBA ad Lea ( pixels, 8 b/p). NO-RECONF deotes the umber of adders eeded to implemet a P1 without usig recofigurability. WORST of RECONF Table 1. Number of adders. Rage size NO- RECONF (pixels) RECONF WORST AVERAGE Girl Lea (49.9%) 150 (29.3%) 136 (26.6%) (49.6%) 36 (28.3%) 29 (22.8%)

8 Table 2. Number of LEs for a PE Rage size NO- RECONF (pixels) RECONF WORST AVERAGE Girl Lea (62.2%) 4674 (44.4%) 4642 (44.1%) (73.3%) 2109 (59.7%) 2057 (58.1%) deotes the umber of adders usig recofigurability i the worst case ad its ratio to that of NO-RECONF. The values of WORST are calculated by (7) ad those of NO- RECONF is calculated by (3). AVERAGE of RECONF deotes the umber of adders i the average case usig recofigurability. Table 1 shows that the umber of adders is sigificatly reduced by utilizig recofigurability. Table 2 shows the total umber of LEs eeded for the PE. Agai, NO-RECONF deotes the umber of LEs for a PE implemeted without usig recofigurability. WORST of RECONF deotes the umber of LEs i the worst case usig recofigurability ad its ratio to the umber of NO-RECONF. AVERAGE of RECONF deotes these average umbers usig recofigurability. Here, we assume that a LE is a LUT with four iputs ad a output. Carry save adders are used for the adders for P1. The fial summatio ad the carry vector provided by these carry save adders is added by a carry look ahead adder at the ed. Therefore, oe carry look ahead adder is implemeted i P1. We evaluated the umber of LEs by coutig 1-bit full adders eeded for carry save adders of P1 ad assumig that a 1-bit full adder is implemeted with two LEs. Altera FPGA mappig tool MAX+Plus II was used to evaluate the umber of LEs for P2 ad the carry look ahead adder. The umber of LEs for P2 is 1556 whe the rage-size is 828, ad 1343 whe the rage-size is 424. Table 2 idicates that the value of WORST is approximately 60% of that of NO- RECONF whe the rage-size is 828. Whe the rage-size is 424, the ratio is approximately 70%. These reductios are importat for implemetig may PEs uder the resource limitatio to accelerate the ecodig. Although further ivestigatios for dyamic allocatio of PEs are eeded, the average case suggests that dyamically chagig the umber of PEs ad makig full use of limited resources is promisig. 4.2 Efficiecy of The Improved Algorithm Here, to cofirm the efficiecy of OMIT, we evaluate the umber of iteratios of the iside of the iermost loop by computer simulatio. The umbers of iteratio for EX- AUS ad OMIT are compared uder the same SNRs for Girl ad Lea. SNRs are evaluated with the decoded images obtaied after 20 iteratios of the mappig. The image was divided ito 828-size rage blocks at the begiig. Ucovered rage blocks were divided ito four 424-size rage blocks. Domai blocks obtaied by rotatig ad flippig are ot icluded i the domai pool. We evaluated the summatio of iteratios for 828 ad 424-size rage blocks. I each step i our pipelied PE etwork, a domai block is iputted to the etwork. Therefore, the umber we evaluated idicates the ecodig time whe oe PE is implemeted. Fig. 5 shows the evaluated values for Girl ad Lea. For Girl, the values for OMIT are from 55% to 70% of EXAUS whe the SNR is from 28 to 30 db. For Lea, these ratios are from 10% to 30%. Note that for Lea, o 828-size rage block is divided i EXAUS whe the SNR is 30 db. Therefore, the SNR does ot fall to less tha 30 db, ad the umber of iteratios caot be reduced more. The ratios for Lea are give by comparig the values of OMIT ad the miimum value of

9 iteratio umber (x10 6 ) iteratio umber (x10 6 ) EXAUS OMIT Girl SNR(dB) EXAUS OMIT Lea SNR(dB) Fig. 5. Number of iteratios EXAUS. As a result, the improvemet of the algorithm reduces the ecodig times for these images to 10 to 55% with fie fidelity. 5 Coclusio I this paper, we have proposed a method for implemetig fractal image compressio o a dyamically recofigurable architecture. I our method, PEs are specialized for image blocks ad cocurretly perform the computatios i a pipelie maer. Furthermore, plural PEs work i parallel. By usig the recofigurability, the recofigurable resources eeded for each PE is reduced to 60% to 70% of that of the straightforward implemetatio i the worst case. This reductio is quite importat for implemetig may PEs uder the resource limitatio i order to accelerate the ecodig. I additio, a improved fractal image compressio algorithm omittig useless computatios, which ca be achieved by dyamic ad partial recofigurability, ca reduce the ecodig time to 10 to 55%. As a result, by applyig these utilizatio of the recofigurability to the proposed pipelied PE etwork, the ecodig time of the PE etwork ca be sigificatly reduced uder the recofigurable resource limitatios. I future works, we pla to implemet the preseted ecoder ad cofirm the effectiveess of the preseted PE etwork i practice. Refereces 1. T. Miyazaki, Recofigurable Systems: A Survey, Proc. of ASP-DAC 98, pp , Feb Xilix, XC6200 Field Programmable Gate Arrays, Apr Atmel, AT40K FPGAs, Dec, J. R. Koza, F. H. Beett III, J. L. Hutchigs, S. L. Bade, M. A. Keae, ad D. Adre, Evolvig Computer Programs usig Rapidly Recofigurable Field-Programmable Gate Arrays, Proc. of FPGA 98, pp , Feb Y. Fisher (Ed.), Fractal Image Compressio: Theory ad Applicatio, Spriger, M. F. Barsley, V. Ervi, D. Hardi, ad J. Lacaster, Solutio of a Iverse Problem for Fractals ad Other Sets, Proc. of Natl. Acad. Sci USA, 83: , Apr A. E. Jacqui, Fractal Image Codig: A Review, Proc. of the IEEE, vol. 81, o. 10, pp , Oct Y. Fisher, Fractal Image Compressio, SIGGRAPH Course Notes, M. F. Barsley, Fractals Everywhere, AK Peters, S. A. White, Applicatios of Distributed Arithmetic to Digital Sigal Processig: A Tutorial Review, IEEE ASSP Magazie, pp. 4 19, July