Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation

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1 Improvemet of the Orthogoal Code Covolutio Capabilities Usig FPGA Implemetatio Naima Kaabouch, Member, IEEE, Apara Dhirde, Member, IEEE, Saleh Faruque, Member, IEEE Departmet of Electrical Egieerig, Uiversity of North Dakota, Grad Forks, ND Uiversity of North Dakota, Grad Forks, ND Abstract - Whe data is stored, compressed, or commuicated through a media such as cable or air, sources of oise ad other parameters such as EMI, crosstalk, ad distace ca cosiderably affect the reliability of these data. Error detectio ad correctio techiques are therefore required. Orthogoal Code is oe of the codes that ca detect errors ad correct corrupted data. A -bit orthogoal code has /2 1s ad /2 0s. I a previous work these properties have bee exploited to detect ad correct errors. I this paper we preset a ew methodology to ehace error detectio capabilities of the orthogoal code. The techique was implemeted experimetally usig Field Programmable Gate Arrays (FPGA). The results show that the proposed techique improves the detectio capabilities of the orthogoal code by approximately 50%, resultig i 99.9% error detectio, ad corrects as predicted up to (/-1) bits of error i the received impaired code with badwidth efficiecy. Idex Terms - FECC, FPGA, Orthogoal Code Covolutio 1. INTRODUCTION Whe data is stored, compressed, or commuicated through a media such as cable or air, sources of oise ad other parameters such as EMI, crosstalk, ad distace ca cosiderably affect the reliability of these data. Error detectio ad correctio techiques are therefore required. Some of those techiques ca oly detect errors, such as the Cyclic Redudacy Check [1, 2]; others are desiged to detect as well as correct errors, such as Salomo Codes [3]. However, the existig techiques are ot able to achieve high efficiecy ad to meet badwidth requiremets, especially with the icrease i the quatity of data trasmitted. Orthogoal Code is oe of the codes that ca detect errors ad correct corrupted data. Our objective i this paper is to ehace the error cotrol capabilities of orthogoal codes by meas of Field Programmable Gate Array (FPGA) implemetatio. 2. ORTHOGONAL CODES Orthogoal codes are biary valued ad they have equal umber of 1 s ad 0 s. A -bit orthogoal code has /2 1 s ad /2 0 s; i.e., there are /2 positios where 1 s ad 0 s differ [, 5]. Therefore, all orthogoal codes will geerate zero parity bits. The cocept is illustrated by meas of a 8- bit orthogoal code as show i Fig.1. It has 8-orthogoal codes ad 8-atipodal codes for a total of 16-biorthogoal codes. Atipodal codes are just the iverse of orthogoal codes; they are also orthogoal amog themselves. Orthogoal Code Atipodal Code P P Fig. 1. Illustratios of the proposed cocept. A 8-bit orthogoal code has 8 orthogoal codes ad 8-atipodal codes for a total of 16 bi-orthogoal codes. All orthogoal ad atipodal codes geerate zero parity. Sice there is a equal umber of 1 s ad 0 s, each orthogoal code will geerate a zero parity bit. Therefore, each atipodal code will also geerate a zero parity bit. A otable distictio i this method is that the trasmitter does ot have to sed the parity bit sice the parity bit is kow to be always zero [7]. Therefore, if there is a trasmissio error, the receiver will be able to detect it by geeratig a parity bit at the receivig ed. Before trasmissio a k-bit data set is mapped ito a uique -bit. For example, a -bit data set is represeted by a uique 8-bit orthogoal code which is trasmitted without the parity bit. Whe received, the data are decoded based o code correlatio. It ca be doe by settig a threshold midway betwee two orthogoal codes. This is give by the followig equatio d = (1) th Where is the code legth ad d th is the threshold, which is midway betwee two orthogoal codes. Therefore, for the 8- bit orthogoal code (Fig. 2), we have d th = 8/ = 2.

2 TABLE I Orthogoal Codes ad the Correspodig Chip Error Cotrol Capabilities. t METHODOLOGY AND FPGA IMPLEMENTATION 3.1 Desig Methodology Fig. 2. Illustratio of Ecodig ad Decodig. This mechaism offers a decisio process, where the icomig impaired orthogoal code is examied for correlatio with the eighborig codes for a possible match. The acceptace criterio for a valid code is that a -bit compariso must yield a good auto-correlatio value; otherwise, a false detectio will occur. This is govered by the followig correlatio process, where a pair of -bit codes x 1, x 2... x ad y 1, y 2 y is compared to yield, Rxy (, ) = xy 1 (2) i i i= 1 Where R(x, y) is the auto correlatio fuctio, is the code legth, d th is the threshold defied i (1). Sice the threshold (d th ) is i betwee two valid codes, a additioal 1-bit offset is added to (2) for reliable detectio. The average umber of errors that ca be corrected by meas of this process ca be estimated by combiig (1) ad (2), yieldig, t = R( x, y) = 1 (3) I (3), t is the umber of errors that ca be corrected by meas of a -bit orthogoal code. For example, a sigle error-correctig orthogoal code ca be costructed by meas of a 8-bit orthogoal code ( = 8). Similarly, a three-errorcorrectig orthogoal code ca be costructed by meas of a 16-bit orthogoal code ( = 16), ad so o. Table-1 below shows a few orthogoal codes ad the correspodig errorcorrectig capabilities: Sice there is a equal umber of 1 s ad 0 s, each orthogoal code will geerate a zero parity bit. If the data has bee corrupted durig the trasmissio the receiver ca detect errors by geeratig the parity bit for the received code ad if it is ot zero the the data is corrupted. However the parity bit does t chage for a eve umber of errors, hece the receiver ca oly detect errors 2 /2 combiatios of the received code. Therefore detectio percetage is 50% [6]. Our approach is ot to use the parity geeratio method to detect the errors, but a simple techique based o the compariso betwee the received code ad all the orthogoal code combiatios stored i a look up table. The techique which ivolves a trasmitter ad receiver is described below. 3.2 Trasmitter The trasmitter icludes two blocks: a ecoder ad a shift register. The ecoder ecodes a k-bit data set to =2 k-1 bits of the orthogoal code ad the shift register trasforms this code to a serial data i order to be trasmitted as show i Fig.3. For example, -bit data is ecoded to 8-bit (2 3 ) orthogoal code accordig to the lookup table show i Fig.2. The geerated orthogoal code is the trasmitted serially usig a shift register with the risig edge of the clock. 3.3 Receiver The received code is processed through the sequetial steps, as show i Fig.. The icomig serial bits are coverted ito -bit parallel codes. The received code is compared with all the codes i the lookup table for error detectio. This is doe by coutig the umber of oes i the sigal resultig from XOR operatio betwee the received code ad each combiatio of the orthogoal codes i the lookup table. A couter is used to cout the umber of oes i the resultig - bit sigal ad also searches for the miimum cout. However a value rather tha zero shows a error i the received code. The orthogoal code i the lookup table which is associated with the miimum cout is the closest match for the corrupted received code. The matched orthogoal code i the lookup table is the corrected code, which is the decoded to k-bit data. The receiver is able to correct up to (/)-1 bits i the received impaired code. However, if the miimum cout is

3 associated with more tha oe combiatio of orthogoal code the a sigal, REQ, goes high.. IMPLEMENTATION AND RESULTS A Sparta-3 hardware board ad ISE Xillix software have bee used for code testig. The simulatio has bee performed usig ModelSim XE software. The simulatio results were verified for most of the combiatios of 8-bit ad some of the 16-bit orthogoal code. The software simulatio results alog with the clock cycles are explaied for the trasmitter ad receiver i the followig sectios..1 Trasmitter Fig.5 shows a example of the results of the trasmitter simulatio correspodig to the iput data value 0110 labeled as data. This data has bee ecoded to the associated orthogoal code labeled ortho. The sigal EN is used to eable the trasmissio of the serial bits txcode of the orthogoal code with every risig edge of the clock..2 Receiver Upo receptio, the icomig serial data is coverted ito 8-bit parallel code rxcode. Couter is used to cout the umber of 1 s after XOR operatio betwee the received code ad all combiatios of orthogoal code i the lookup table. Cout gives the miimum cout of oes amog them. The orthogoal code ortho associated with the miimum cout is the closest match for the received code, which is the decoded to the fial data give by sigal data. Three differet cases result from this simulatio. I the first case, the received code has a match i the lookup table. As show i Fig.6, the received code is rxcode= , cout= 0 ad hece the received code is ot corrupted. The code is the decoded to the correspodig fial data I the secod case, the received code has o match i the lookup table. As show i Fig.7, the received code is rxcode= , the value of miimum cout is 1, which reveals a error. The correspodig orthogoal code is ortho= which is the closest match for the received code give by the miimum cout, ad the decoded fial data is I this case the sigle bit error is detected ad corrected by the receiver. I the third case, there is more tha oe possibility of closest match i the lookup table. As show i Fig.8, the received code is rxcode= The value of miimum cout is associated with more tha oe orthogoal code ad thus it is ot possible to determie the closest match i the lookup table for the received code. The the sigal labeled REQ goes high, which is a request for a retrasmissio..3 Results The results of the simulatio show that for a k-bit data, the correspodig -bit orthogoal code is able to detect ay faulty combiatio other tha the combiatios of orthogoal code i the lookup table. The umbers of these combiatios are 2 k. Hece the percetage of detectio is give by (2-2 k )/2 %. Similarly, the system is able to correct up to (/)-1 bit error ad the umber of clock cycles required to process the received code are (2+2). For example whe a -bit data is ecoded i to 8- bit orthogoal code; it has 2 = 16 combiatios of orthogoal code. Therefore, out of 256 possible combiatios of 8-bit received code the receiver will ot able to detect error i those codes which are oe of the combiatios of orthogoal code. Hece the detectio percetage for 8-bit orthogoal code is give by (2 8-2 ) /2 8 = 93.57% ad also able to correct sigle bit error. Similarly, the percetage of detectio for 16-bit orthogoal code is 99.95% ad gives 3-bit of error correctio. Table II shows a summary of the results ad their correspodig detectio rates for 8-bit, 16-bit, ad N-bit orthogoal codes. 8-bit Codes 16-bit Codes N-bit Code TABLE II Detectio rate computed from the results correspodig to 8-bit, ad 16-bit orthogoal codes. Number of combiatios N f Number of udetected combiatios Detectio Rate 256 N f = % N f = % 2 N N f =2N (2 N -N f )/ 2 N 5. CONCLUSION The results of the orthogoal code implemetatio show that this techique improved the error detectio from 50% to 93% for 8-bit orthogoal code ad 99.9% for 16-bit orthogoal code. The techique proposed ca be applied to ay ecodig system used for digital trasmissio. Future work icludes improvemet of correctio capasbilities of the orthogoal code ad paralell implemetatio to speed up the data processig. ACKNOWLEDGMENT This work was supported by the ND EPSCoR project through Natioal Sciece Foudatio grat # UND

4 -bit orthogoal code k-bit Data Ecoder (Mappig) Parallel to Serial Coverter (Shift register) Serial bits of code clk Fig. 3. Block diagram of the trasmitter. -bit orthogoal code Serial bits of code Serial To Parallel Coverter Error Detectio (XOR & Couter) Error Correctio (Mappig) Decoder Data Bits clk REQ Fig.. Block diagram of the receiver. Fig. 5. Example of the simulatio results of the trasmitter. Fig. 6. Example of case oe simulatio. Fig. 7. Example of case two simulatio.

5 Fig. 8. Example of case three simulatio. REFERENCES [1] Baicheva, T., S. Doduekov, ad P. Kazakov, Udetected error probability performace of cyclic redudacy- check codes of 16-bit redudacy, IEEE Proc. Comms., Vol. 17, No. 5, Oct. 2000, pp [2] A. Hokai, H. Delic, S. Sari, Two dimesioal CRC for efficiet trasmissio of ATM Cells over CDMA, IEEE Commuicatios Letters, Vol., No., April [3] Styliaakis V,Toptchiyski S, A Reed-Solomo codig/decodig structure for a ADS modem, Electroics, Circuits ad Systems, Proceedigs of ICECS apos ; 99. The 6th IEEE Iteratioal Coferece, Volume 1, Issue, 1999, pp [] S. Faruque, Broadbad Commuicatios Based o Code Divisio Parallel Access (CDPA), The Iteratioal Egieerig Cosortium (IEC), Aual Review of Commuicatios, Vol. 57, ISBN: , Nov [5] Saleh Faruque, Error Cotrol Codig Based o Orthogoal Codes, Wireless Proceedigs, Vol. 2, pp , 200. [6] S.Faruque, A.Dhirde,N.Kaabouch Forward error cotrol codig based o orthogoal code ad its implemetatio usig FPGA, 7th IASTED Iteratioal Coferece, Motreal, Quebec, Caada, May 30 Jue 1, 2007, Upublished. [7] B. Sklar, Digital Commuicatios Fudametals ad Applicatios, Pretice Hall, [8] Qualcomm, The CDMA Network Egieerig Hadbook, Vol. I, Cocepts i CDMA, 1993.