splitting tehniques that partition live ranges have been proposed to solve both the spilling problem[5][8] and the assignment problem[8][9]. The parti

Transcription

1 Load/Store Range Analysis for Global Register Alloation Priyadarshan Kolte and Mary Jean Harrold Department of Computer Siene Clemson University Abstrat Live range splitting tehniques divide the live ranges of variables into live range segments to improve global register alloation. We present a new tehnique for live range splitting alled load/store range analysis. This analysis loalizes the prots and the register requirements of every aess to every variable to provide a ne granularity of andidates for register alloation. Load/Store range analysis is based on the data ow analysis algorithm for def-use haining. Experiments on a small suite of C and FORTRAN benhmark programs show that a graph oloring register alloator operating on load/store ranges often provides better alloations than the same alloator operating on live ranges. Experimental results also show that the omputational ost of using load/store ranges for register alloation is moderately more than the ost of using live ranges. 1 Introdution The goal of register alloation is to map variables in an intermediate language program to either registers or memory so that the number of aesses to memory is minimized during program exeution. Sine there is a signiant dierene between aess times of registers and memory, a good register alloation sheme an produe appreiable speedup in program exeution time[15]. Various ompiler optimizations suh as ommon subexpression elimination, loop-invariant ode motion, proedure inlining and ode sheduling further inrease the demand for good register alloation. Register alloation onsists of two subproblems: register spilling and register assignment. Register spilling determines whih live ranges y will be assigned to registers (alloated live ranges) and whih live ranges will be assigned to memory (spilled live ranges). Then, register assignment maps alloated live ranges to registers so that no register ontains more than one live range at eah program statement. Graph oloring on interferene graphs of live ranges is an established paradigm for register alloation[6][7]. The nodes of an interferene graph are live ranges and there are edges between nodes that are simultaneously live at any statement in the program. Sine both the spilling and the oloring problems are NPomplete[12][20], the graph oloring method uses heuristis to obtain a register alloation. However, using live ranges as nodes of the interferene graph unneessarily onstrains the register alloator sine a register must be alloated for the entire live range of a variable. To produe better register alloations, live range This work was p artially supported by NSF grant CCR to Clemson University. y The live range of a variable is the set of statements in the program over whih the variable is live (has a value).

2 splitting tehniques that partition live ranges have been proposed to solve both the spilling problem[5][8] and the assignment problem[8][9]. The partitions of a live range of a variable may be assigned to dierent registers or even spilled to memory in dierent regions of the program. Although live range splitting is promising, there is no theoretial or empirial evidene that these live range splitting tehniques provide better alloations than the graph oloring algorithm using live ranges. In this paper, we overview a new tehnique to split live ranges alled load/store range analysis that addresses the register spilling problem. A load/store range is a minimal partition z of a live range that an be independently and protably alloated (or spilled). We ompute load/store ranges using standard iterative data ow analysis algorithms[1]. Then, we onstrut the interferene graph of a program using load ranges and store ranges instead of live ranges, and use existing heuristis to spill and olor the nodes of this graph. We inorporated our load/store range analysis into a register alloator that uses Chaitin's graph oloring sheme[7] with delayed spilling[3] and the Haifa suite of spill heuristis[2], and we ompared it with a similar register alloator that used live range interferene graphs. Experimental results using several well known C and FORTRAN benhmark programs show that the graph oloring alloator operating on load/store ranges often produes better spilling than the same algorithm operating on live ranges. The main benet of our approah is that, unlike live ranges that are oarse and do not adequately aount for lustered aesses of variables[8][16], our tehnique provides a ne granularity of andidates for register alloation that are based on the aess patterns of variables. Additionally, sine our new load/store ranges an be used instead of live ranges with any existing graph oloring algorithms, our tehnique an easily be inorporated into existing ompilers that use graph oloring for register alloation. Finally, we report the eetiveness of our load/store range analysis by omparing its alloations with those using live range analysis. This approah ontrasts with previous experiments [8][17] that ompare the memory aesses produed by a register alloator using the proposed live range splitting sheme with the memory aesses in the program without any register alloation. We are urrently experimenting to show the overall eetiveness of our tehnique on program run time and will report the results in the nal paper. In the next setion, we give bakground information. Setion 3 summarizes our tehnique for load/store range analysis and Setion 4 outlines our algorithm to onstrut the interferene graph using our load/store range analysis tehnique. In Setion 5, we disuss the use of load/store range analysis with an existing register alloation sheme and present our experimental results. Related work is briey disussed in Setion 6. Bakground The live range of variable V is the set of all statements over whih V is live. The live range of a variable may ontain a number of disonneted regions where eah region is a name[6]. For variable V, the name of denition D is the largest onneted set of statements over whih V is live that ontains the live range of z A partition divides the live ranges into possibly overlapping segments of live ranges. 2

3 B2 START B1 = S1: X :=... Li1?.... := X Z ZZZ~ S2: X :=... B3 S3: X :=... Z Z ZZZ~ ZZZ~ Li2... = B4... := X Z ZZZ~ STOP B5 =... := X Figure 1: Li1, ontaining fstart, B1g, and Li2, ontaining fb2, B3, B4, B5g, are the two live ranges of X. denition D. The live range of denition D of variable V is the set of all statements where D reahes and a use U of V is reahable. The two equations below are used to ompute names. In the rst equation, live range Li is omputed for eah denition D. In the seond equation, names are omputed by taking the union of interseting Li. Li(D) = f statement S j D reahes S ^ Name(D) = S Name(D) \ Li(D 0 ) 6= Li(D 0 ) [ Li(D) use U reahable from S g For example, Figure 1 shows a program with the variable X dened in START, B2 and B3, and used in B1, B4 and B5. X has three denitions and hene, at most three names. The live ranges of the definitions of X are Li(S1) = fstart, B1g, Li(S2) = fb2, B4g and Li(S3) = fb3, B4, B5g. Sine Li(S1) does not interset with either Li(S2) or Li(S3), Name(S1) = Li(S1) = fstart,b1g; all this set Li1. On the other hand, Li(S2) and Li(S3) interset at blok B4, and Name(S2) is the same as Name(S3). Thus, Name(S2) = Name(S3) = Li(S2) [ Li(S3) = fb2, B3, B4, B5g; all this set Li2. Li1 and Li2 are shown in Figure 1. In the remainder of this paper, we use the term live range of a variable to mean the live range of a name. A program statement is omposed of two phases: the read phase, whih reads operands, and the write phase, whih writes the results. We denote the elements of a live range as follows. 3

4 \S r " indiates that the live range inludes only the read phase of statement S \S w " indiates that the live range inludes only the write phase of statement S \S rw " indiates that the live range inludes both the read and write phases of statement S Two live ranges interfere with eah other if they are live at the same phase of the same statement. The degree of live range L is the number of live ranges that interfere with L. The width of statement S is the number of live ranges that interfere at S. If the number of live ranges that interfere in the two phases of S is dierent, the width of S is the maximum of the widths of the two phases. The prot assoiated with a live range is the weighted sum of the number of denitions and uses of the variable, where the weights are the the exeution frequenies of the denitions and uses. Load/Store Range Analysis The aim of load/store range analysis is to loalize prots and register requirements of the aesses to variables to ahieve better spilling. Register requirements are the statements over whih a register is required and aesses are the denitions and uses of the variable. Eah denition of a variable produes a store range. A store range of a denition is the set of statements over whih the variable must be alloated to a register to avoid a store at the denition. A store range may ontain a number of load ranges, and there is at least one load range for every use in the store range. A load range of a use is the set of statements over whih the variable must be alloated to a register to avoid a load at the use. The main observation used to onstrut load ranges is that alloating a register over all statements between a use of a variable and the \most reent aess" of the variable is neessary and suient to avoid a load at the use. Load ranges and store ranges are minimal partitions of live ranges that an be independently and profitably alloated or spilled. Independent alloation means that the alloation (inluding the omputation of the heuristi funtion for the alloation) of a load range of a variable is independent of that of all other load ranges of that variable. Similarly, the alloation of a store range of a variable is independent of the alloations of all other store ranges of that variable. Protable alloation means that every load and store range has a positive savings in program exeution time if it is alloated. Minimum partitions are the smallest sets of statements that are protable and independent. The example in Figure 2 illustrates the usefulness of load ranges of a variable. To see this, onsider the variable X at statements S1 through S4 in the basi blok. There is a denition of X at statement S1, and uses of X at statements S2, S3, and S4. X is live between S1 and S4, and the live range of X is Li1:(S1 w,: : :,S4 r ). The prot of alloating Li1 is 4 beause it has 1 store and 3 loads when we assume that the basi blok is exeuted one. Store range analysis produes a store range St1:(S1 w,: : :,S4 r ) that has a prot of 4. Load range analysis produes the load ranges Lo1:(S1 w,: : :,S2 r ), Lo2:(S2 rw,: : :,S3 r ) and Lo3:(S3 rw,: : :,S4 r ). The prot of alloating Lo1 to a register is 1 beause a load is saved at S2. The prot of alloating Lo2 is 1 beause we assume that a load is used to aess X at S2 and a register is used to aess 4

5 Li1 St1 Lo1 S1: X := S2:... := X... S3:... := X 4 4 s s s s 1 Lo2 1 s Lo3 s... 1 S4:... := X... Basi Blok Live Range Store Range Load Ranges Figure 2: Load ranges Lo1, Lo2 and Lo3 are independent of one another. X at S3 and thus, we save a memory load at S3. Similarly the prot of Lo3 is 1. The ranges of X are also shown in Figure 2. A lled irle indiates that the range overs the read phase as well as the write phases of a statement, whereas an empty irle indiates that the range is live in only one phase. Suppose there are too many live variables in the region between statements S2 and S3 and variable X has to be spilled. If we spill the live range of X, Li1, there is no prot, but if we spill load ranges, we may be able to alloate the load ranges Lo1 and Lo3 to obtain a prot of 2. On the other hand, if there are enough registers available in the basi blok, alloating store range St1 is the same as alloating live range Li1 and yields a prot of 4. Live range Li1 is split into load ranges Lo1, Lo2 and Lo3, whih learly are protable partitions. These are minimal partitions beause it is not possible to nd smaller partitions that yield any prot. Lo1, Lo2 and Lo3 an be independently alloated beause the alloation as well as the omputation of the prot for any one of them does not depend on the alloation of the others. Thus, the prot of alloating a ombination of the load ranges is the sum of the prots of the ranges. For example, if Lo1 and Lo2 are alloated to a register, then the prot is 2 beause of the loads saved at S2 and S3. To illustrate the usefulness of store ranges, onsider the fragment of the program shown in Figure 3. Variable X is dened at statements S1 and S2, and is used at statement S3. The live range of X is Li1:(S1 w,: : :,S2 w,: : :,S3 r ). Suppose S1 and S2 are eah exeuted one and S3 is exeuted twie, then the prot of Li1 is 4. Store range analysis produes two store ranges: St1:(S1 w,: : :,S3 r ) and St2:(S2 w,: : :,S3 r ) eah with a prot of 2. If a register is not available in the region S1,: : :,S3, onsidering store ranges as andidates for spilling is beneial beause only St1 is spilled while St2 is alloated a register. 5

6 ? S0: if (...) S0: if (...) S1: X :=... Z ZZ~ else = S1: X :=... S2: X :=... S2: X :=... Z ZZ? endif Z~?? S3:... := X S3:... := X? Li1 @? 4 2 Program Fragment Control Flow Graph Live Range Store Ranges Figure 3: Store ranges St1 and St2 are independent of eah other. The Interferene Graph using Load/Store Ranges In this setion, we outline our algorithm Load/StoreInterferenes, given in Figure 4 to onstrut the load/store interferene graph. The rst step in Load/StoreInterferene omputes store ranges using iterative data ow algorithms for reahing denitions and reahable uses. The store range (St) of denition D is the set of all those statements where the denition D reahes and there is a reahable use U. St (def D) = f statement S j def D reahes S ^ use U reahable from S g The prot assoiated with a store range is the sum of the number of denitions and uses that have been weighted by the exeution frequeny of the denitions and uses. The seond step of Load/StoreInterferene renames eah variable by assigning a unique subsript to eah aess of the variable in the program. In the third step of Load/StoreInterferenes, load ranges of eah store range are omputed. We introdue additional terminology to dene a load range. An aess of a variable is a denition or a use. An aess-free subpath with respet to variable V and two statements S i and S j is a subpath from statement S i to the statement S j that ontains no aesses of the variable V. Ourrene V i of variable V arrives at statement S if there is at least one aess-free subpath with respet to V from V i to S. Use U of variable V is exposed at statement S if there is at least one aess-free subpath with respet to V from S to U. A denition of a variable is never exposed. A load range (Lo) of two aesses V i and V j of a store range is the set of statements between V i and V j. Lo (V i, V j ) = f statement S j 6

7 Algorithm Input : Output : Load/StoreInterferenes Control flow graph G Interferene graph IG for load/store ranges /* step 1 : ompute store ranges of definitions*/ Compute reahing definitions and reahable uses for G Compute store ranges using reahing definitions and reahable uses /* step 2 : rename aesses of variables */ for eah variable V in the program do Assign a unique subsript to eah aess of V /* step 3 : ompute load ranges of store ranges */ all ComputeLoadRanges /* step 4 : ompute nodes and edges of IG */ Weight nodes in IG with profits Add edges by omputing interferene among ranges Figure 4: Algorithm to ompute the load/store interferene graph. V i arrives at S ^ V j is exposed at S g The prot assoiated with Lo(V i, V j ) is the number of times that an aess-free subpath from V i to V j is exeuted. The load ranges of eah store range are omputed using the proedure skethed in Figure 5. Sine the omputation of load ranges requires arriving aesses and exposed uses information, proedure ComputeLoadRanges uses an iterative data ow analysis framework to ompute the arriving aesses in the A IN sets and the exposed uses in the E IN sets. The fourth step of Load/StoreInterferenes onstruts the interferene graph with the store ranges and the load ranges as its nodes. Also, in this step, weights representing the prots of the ranges are added to the nodes. To ompute the prots of the ranges, we estimate that eah aess is exeuted 10 d times where d is the loop-nesting depth at whih the aess ours. We statially estimate the prot of load range Lo(V i, V j ) as the quotient of the exeution frequeny of V j and the number of aesses that reah V j. When a load range is deleted from the interferene graph during register alloation, the prot (weight) assoiated with its store range is deremented aordingly. The fourth step of Load/StoreInterferenes also determines the edges of the interferene graph by omputing the interferenes among these load and store ranges. The load ranges of distint variables interfere if they ontain the same read or write phase of the same statement. The load ranges and store ranges of a variable do not interfere with one another. The degree of a load range is the number of other variables with whih it interferes. The degree of a store range is the ardinality of the union of the set of variables that interfere with its load ranges. During register alloation, the interferenes of a store range are deleted only when the orresponding interferenes of its load ranges are deleted from the interferene graph. For a partiular register alloation sheme, the omputational expense of using load/store ranges instead of live ranges is the additional time required to ompute the load/store ranges and the inrease in alloation time due to the inreased number of nodes handled by the alloator. Sine the order of omputing store ranges is the same as omputing live ranges, the only additional expense is the time to ompute the load 7

8 Proedure Input : Output : Delare : ComputeLoadRanges Store Range G with set of statements S and edge set E Load ranges Lo of store range G A IN, A OUT, E IN, E OUT, GEN, USE and KILL are arrays of sets of aesses suh that there is one suh set for eah statement s 2 S; /* step 1 : initialization of sets */ for s 2 S do KILL [s] := f v j v is an aess of a variable that ours in s g; GEN [s] := f v j v is an aess in s g; USE [s] := f v j v is a use in s g; A IN [s] := ; /* A IN is set of arriving aesses at a point just before s */ A OUT [s] := GEN [s]; /* A OUT is set of arriving aesses at a point just after s */ E IN [s] := USE [s]; /* E IN is set of exposed aesses at a point just before s */ E OUT [s] := ; /* E OUT is set of exposed aesses at a point just after s */ endfor /* step 2 : ompute exposed uses by iterating until a steady state */ E OUT [s] := S t is a suessor of s E IN [t]; E IN [s] := USE [s] [ (E OUT [s] - KILL [s]); /* step 3 : ompute arriving aesses by iterating until a steady state */ A IN [s] := S p is a predeessor of s A OUT [p]; A OUT [s] := GEN [s] [ (A IN [s] - KILL [s]); /* step 4 : ompute load ranges for all pairs of aesses in S */ Lo (V i, V j ) := f s j V i 2 A IN [s] ^ V j 2 E IN [s] g Figure 5: Proedure to ompute load ranges. ranges. Load ranges are omputed using an iterative data ow analysis algorithm where arriving aesses and exposed uses are the propagated values. If we assume that eah statement of the program denes one result and uses at most two operands, then the number of arriving aesses and exposed uses is at most three times the number of denitions in the program. Thus, omputing load/store ranges is proportional to omputing live ranges. The number of load/store ranges is dependent on the denition-use assoiations in the program and is polynomial in the size of the program. In our experiments, we found that the number of load/store ranges is between two and three times the number of live ranges. Register Alloation with Load/Store Ranges We implemented two register alloators that are based on Chaitin's graph oloring sheme[7] with the delayed spilling enhanement[3] and the Haifa spill heuristis[2]. One alloator uses live ranges as the nodes of its interferene graph and the other uses load/store ranges. We experimented with a few well known C and FORTRAN programs in order to ompare the two alloators. The C programs that we onsidered inlude linpak, whih is a linear algebra kernel, lloops, whih is a kernel ontaining the 14 Lawrene Livermore loops, nsieve, whih is the Sieve of Eratosthenes. We also examined the dhrystone, whetstone and dhampstone syntheti benhmarks, but do not report the results beause both alloators produed nearly idential alloations. The FORTRAN programs that we onsidered are the tomatv mesh generation 8

9 Program Proedure Total R Using Using Gain (%) Loads/ Live Lo./St. Stores Ranges Ranges nsieve main % % % % sieve % % % {9 {34.6% lloops main % % {684 {2.0% % init % % % % linpak main % % {3 {11.5% % matgen % % % % dgefa % % % % daxpy % % % {3 {4.0% ddot % % % % dsal % % % % Table 1. Alloations for C programs program and the matrix300 matrix multipliation program from the SPEC benhmarks suite. Here, we report some representative statistis. The live ranges and load/store ranges of the C programs are omputed from the denition/use information obtained from a modied version of the GNU C ompiler x, g[14][19]. The denition/use information of the FORTRAN programs is obtained by using f2 to translate the programs into C[11], and then ompiling the resulting C programs with the modied g ompiler. Tables 1 and 2 ompare the two alloators for the C and FORTRAN programs respetively. The rst and seond olumns ontain the names of the program and its proedure respetively. The third olumn lists the weighted number of loads and stores in the proedure and the fourth olumn gives R, the number of general purpose registers available for alloation. We experimented with 1, 2, 4 and 8 registers to get our results. The fth olumn ontains the weighted number of loads and stores obtained after alloating R registers to the live ranges of the proedure; the sixth olumn shows the orresponding number for the alloation of x 1987, 1989 Free Software Foundation, In, 675 Mass Avenue, Cambridge, MA

10 Program Proedure Total R Using Using Gain (%) Loads/ Live Lo./St. Stores Ranges Ranges tomatv main % % % % matrix300 main % % % % prnt % % {3.5% % sgemv % % % {1 {0.1% Table 2. Alloations for FORTRAN programs Program Proedure Store Load Single Loads/ Live Ranges Ranges Ranges Stores Ranges nsieve main sieve lloops main init linpak main matgen dgefa daxpy ddot dsal tomatv main matrix300 main prnt sgemv Table 3. Number of nodes in the interferene graphs load/store ranges. The last two olumns show the absolute dierene and the perentage dierene between the two alloations respetively. In ases where the resulting number of loads/stores is small, suh as nsieve, sieve with 8 registers, linpak, matgen with 8 registers, matrix300, main with 8 registers and matrix300,saxpy with 8 registers, the results are extreme. However, for other ases, the alloations with the load/store ranges usually results in a redution in the number of loads and stores in the program. To determine the growth in the size of the interferene graph using load/store ranges, we reorded the number of nodes produed by eah alloator. Table 3 ompares the number of nodes in the load/store interferene graphs of our test programs with the number of nodes in the live range interferene graph for the same programs. The third olumn in Table 3 lists the number of store ranges and the fourth lists the number of load ranges. The fth olumn gives the number of store ranges that ontained only one load range. We optimized the number of load/store ranges by eliminating the load ranges that were the only members of their store ranges from the interferene graph. The resulting number of load/store ranges is shown in the sixth olumn. The last olumn in Table 3 shows the number of live ranges of the proedure. Comparing the last two olumns of this table reveals that the number of load/store ranges is generally less than three times the 10

11 number of live ranges. Although there are a few programs where the ratio of the number of load/store ranges to the number of live ranges is higher, these are small programs with few live ranges. These results support our laim that, in pratie, the ost of alloating load/store ranges is muh less than the theoretial worst ase estimates. 2 Related Work The original graph oloring register alloator proposed by Chaitin et al.[6] uses a heuristi to rst alloate or spill live ranges and then to assign registers to those alloated variables. A later heuristi for deiding whih live ranges to spill[7] hooses the andidate with the lowest ost/degree ratio, where the ost is the ost of aessing the variable from memory and the degree is the number of live ranges that interfere with the node in the interferene graph. Later work in global register alloation onentrated on improving Chaitin's graph oloring heuristi[3] and on developing better heuristis for seleting the nodes to be spilled[2]. Briggs, et al.[3] observed that a onstrained node need not neessarily be spilled beause some of its neighbors might share olors and thus, leave a olor for it. They introdued the idea of delayed spilling, whih always produes alloations that are at least as good as those produed by Chaitin. Bernstein, et al.[2] developed the Haifa register alloator and rened Chaitin's spilling heuristi to produe a set of three omplementary heuristi funtions: ost/degree 2, ost/(areadegree), and ost/(areadegree 2 ). The area funtion of a variable approximates the ontribution of the variable to register pressure, and takes into aount the number of program statements in the live range of the variable, the loop-nesting depth of these statements, and the width of these statements. Their experiments showed that although none of these three heuristi funtions onsistently dominated one another, the \best-of-three" always outperformed Chaitin's heuristi for spilling. An important proposal that was made but not implemented or analyzed in the Haifa register alloator projet was that spilling be performed only in the \busy regions" instead of the entire program as in Chaitin's implementation. Callahan and Koblenz[5] proposed a sheme that omputes the spill osts of variables based on variable usage patterns between spills and reloads rather than the usage over the entire program. Although this sheme is intuitively appealing, it is muh more omplex than Chaitin's original sheme, and there are no theoretial or empirial omparisons between the alloations produed by this sheme and those produed by Chaitin. Chow and Hennessy[8] presented an alternate graph oloring sheme alled priority-based oloring. Nodes of the interferene graph are assigned priorities using a ost/size funtion that is similar to Chaitin's ost/degree heuristi. This tehnique does not expliitly address the spilling problem beause they believed that spilled nodes are those with lower priority and therefore, with lower prot in exeution time. Although the live range splitting an produe olorings where Chaitin fails, the greedy oloring approah may to split live ranges that ould have been assigned a single olor by Chaitin's oloring heuristi. Thus, it may introdue unneessary register-register transfer instrutions. Further, it is not lear whether the priority-based oloring produes any improvement in spilling over Chaitin's heuristi. Bernstein's team reports that their 11

12 modiation to Chaitin's spilling heuristi universally outperforms the priority-based oloring approah, but they do not give any spei numbers[2]. Cytron and Ferrante[9] presented an algorithm for live range splitting to improve the olorability of interferene graphs. They desribed an algorithm that guarantees a oloring using MAXLIVE olors, where MAXLIVE is the maximum width at any program statement. If the number of available registers, R, is less than MAXLIVE, the assignment pass is preeded by an alloation pass. The alloation pass uses weights on the nodes suh as Chow and Hennessy's priorities to alloate live range segments suh that the maximum number of live range segments alloated at any statement is R. However, the tehnique for determining suh an alloation is not desribed. Like the priority-based oloring, this algorithm an produe olorings where Chaitin fails, but it may also split live ranges where Chaitin's oloring heuristi would have worked. Referenes [1] A. V. Aho, R. Sethi and J. D. Ullman, Compilers, Priniples, Tehniques, and Tools, Addison{Wesley Publishing Company, [2] D. Bernstein, D. Q. Goldin, M. C. Golumbi, H. Krawzyk, Y. Mansour, I. Nahshon and R. Y. Pinter, \Spill ode minimization tehniques for optimizing ompilers", Proeedings of the ACM SIGPLAN '89 Conferene on Programming Language Design and Implementation, Sigplan Noties, vol. 24, no. 6, pp. 258{263, June, [3] P. Briggs, K. D. Cooper, K. Kennedy and L. Torzon, \Coloring heuristis for register alloation", Proeedings of the ACM SIGPLAN '89 Conferene on Programming Language Design and Implementation, Sigplan Noties, vol. 24, no. 6, pp , June, [4] P. Briggs, K. D. Cooper and L. Torzon, \Rematerialization", Proeedings of the ACM SIGPLAN '92 Conferene on Programming Language Design and Implementation, Sigplan Noties, vol. 27, no. 7, pp. 311{321, June, [5] D. Callahan and B. Koblenz, \Register alloation via hierarhial graph oloring", Proeedings of the ACM SIGPLAN '91 Conferene on Programming Language Design and Implementation, Sigplan Noties, vol. 26, no. 6, pp. 192{203, June, [6] G. J. Chaitin, M. A. Auslander, A. K. Chandra, J. Coke and P. W. Markstein, \Register alloation via oloring", Computer Languages, vol. 6, pp. 47{57, January, [7] G. J. Chaitin, \Register alloation and spilling via oloring", Proeedings of the ACM SIGPLAN '82 Symposium on Compiler Constrution, Sigplan Noties, vol. 17, no. 6, pp. 98{105, June, [8] F. Chow and J. Hennessy, \The priority-based oloring approah to register alloation", ACM Transations on Programming Languages and Systems, vol. 12, no. 4, pp. 501{536, Otober,

13 [9] R. Cytron and J. Ferrante, \What's in a name? The value of renaming for parallelism detetion and storage alloation", Proeedings of the 1987 International Conferene on Parallel Proessing, pp. 19{27, August, [10] R. Cytron, J. Ferrante, B. K. Rosen, M. N. Wegman and F. K. Zadek, \Eiently omputing stati single assignment form and the ontrol dependene graph", ACM Transations on Programming Languages and Systems, vol. 13, no. 4, pp. 451{490, Otober, [11] S. I. Feldman, D. M. Gay, M. W. Maimone and N. L. Shryer, A Fortran-to-C onverter, Computing Siene Tehnial Report No. 149, AT&T Bell Laboratories, Murray Hill NJ, November, [12] M. R. Garey and D. S. Johnson, Computers and Intratability: A Guide to the Theory of NP- Completeness, W.H. Freeman and Company, New York, [13] M. R. Garey and D. S. Johnson, \The omplexity of near{optimal graph oloring", Journal of the ACM, vol. 23, pp. 43{49, [14] M. J. Harrold and P. Kolte, \Combat: A ompiler based data ow testing system", Proeedings of the 10 th Pai Northwest Software Quality Conferene, Otober, [15] J. L. Hennessy and D. A. Patterson, Computer Arhiteture A Quantitative Approah, Morgan Kaufmann Publishers, In., San Mateo, California, [16] W. -C. Hsu, C. N. Fisher and J. R. Goodman, \On the minimization of loads/stores in loal register alloation", IEEE Transations on Software Engineering, vol. 15, no. 10, pp. 1252{1260, Otober, [17] J. R. Larus and P. N. Hilnger, \Register alloation in the SPUR Lisp ompiler", Proeedings of the ACM Symposium on Compiler Constrution, Sigplan Noties, vol. 21, no. 6, pp. 255{263, June, [18] T. A. Proebsting and C. N. Fisher, \Probabilisti register alloation", Proeedings of the ACM SIG- PLAN '92 Conferene on Programming Language Design and Implementation, Sigplan Noties, vol. 27, no. 7, pp. 300{310, June, [19] R. M. Stallman, \Using and porting GNU CC (version )," Free Software Foundation, In., Cambridge MA, February, [20] M. Yannakakis, \Node- and edge-deletion NP-omplete problems", Proeedings of the 10 th Annual ACM Symposium on Theory of Computing, pp. 253{264,