Tokyo Institute of Technology. Japan Advanced Institute of Science and Technology (JAIST) optimal packing with a certain guarantee.

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1 Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules Shigetoshi NAKATAKE y, Masahiro FURUYA z,, and Yoji KAJITANI y y Department of Electrical and Electronic Engineering Tokyo Institute of Technology z School of Information Science Japan Advanced Institute of Science and Technology (JAIST) Abstract A main task in designing IC/PCB is to pack rectilinear modules under various constraints and objectives. If modules are all rectangles without any positional constraint, recently proposed BSG and Sequence-pair based packing algorithms have been proved to work fast enough for practical use. Focusing BSG, to support an eective use, this paper develops techniques to handle rectilinear modules and modules with positional constraints. First a solution is proposed for pre-placed modules. It is to give a linear order to the oating modules following which they are embedded in packing. In the course, the pre-placed modules are considered as the constraints such that no oating modules are forbidden to be placed. The packing of modules including rectilinear ones is solved by applying the above techniques after rectilinear modules are sliced into a set of rectangles. Experimental results on industrial PCBdata showed that the proposed algorithm outputs high quality packings. 1 Introduction Away to cope with recent explosion of IC's scale and colexity in design specications is in a development of packing techniques followed by evolutions to take various constraints and optimizations into consideration. Recently,two new packing algorithms were proposed [1, 2]. It has been reported that they show enough performance for practical use if the problem is sily to pack given rectangles into as small area. Its biggest advantage to the conventional slicing structure is in universality: all the signicant placements could be generated, where signicant placement means a placement that can be optimum according to the size of modules. This fact is believed to lead a heuristic search toan This research is partly supported nancially by CAD21 at TIT and JAIST. optimal packing with a certain guarantee. Though these two ideas could be regarded mathematically equivalent, the dierence of the data structures makes each bear apparently dierent merits. This paper focuses the BSG based packing [1]. However, a sile rectangle packing is iractical unless it is evolved to accept such circumstantial requests that arise from modules which are in close relations by wires, space for wires, channel denitions, and rectilinear modules [, 4, 5,, 7] and pre-placed modules []. The last issue could be a merit in packing since it is a part of the solution and the cost of searching would be reduced []. It is true in those constructive algorithm design that places the modules one by one considering the situation. While, since our BSG based packing is to let all the modules be assigned without physical dimension and physical coaction follow, it is not on a course to introduce the pre-placed modules. This paper proposes an idea. A module is said oating if it is not pre-placed. Consider to pack only the oating modules in the order from the left-bottom of the chip. This is possible by the feature of the BSG. On the way, the pre-placed modules are considered the constraint that no oating module is allowed to be placed to intersect. This idea is easily ilemented in the coaction procedure. As we often encounter in PCB/IC design, some of modules are rectilinear. The packing of modules including such ones is needed. The above idea can be applied in the following way. A rectilinear module M is dissected into a set of rectangles. One fragment M r which is leftmost or most bottom in the set is chosen as the representative ofm. Start the packing from the bottom-left by the way as mentioned above. On the way, assoonasm r is xed its position (coordinates), stop the packing and determine the positions of the other fragments with reference of M r. Restart

2 the packing but with those placed fragments as the pre-placed modules. This paper reports three kinds of eirical results. First, using random inputs, we observed the relation between the number of pre-placed modules and chip area. It was revealed that to keep the quality, the coutation time is proportional to the number of pre-placed modules. Second, using an industrial PCB-data as the input, we demonstrated that the proposed method output highly coacted packings coetitive with results assuming that all the modules are oating. Third, the input is randomly generated rectilinear modules. The proposing algorithm showed an eciency for 1 module packing. 2 BSG and BSG-Based Coaction 1 The BSG (Bounded-Sliceline Grid) was introduced for packing of rectangular modules [1]. It consists of horizontal and vertical bounded segs, called the BSGsegs, which together dissect the plane regularly into rooms, called the BSG-rooms. In packing, modules are assigned into BSG-rooms, at most one in one room, and one-dimensional horizontal and vertical coactions follow. The BSG is innite in its denition but we restrict the region for practical use. In Fig. 1(A), a geometrical image of the BSG of size 2 is shown. Each BSG-room is bounded by a pair of half-shifted horizontal BSG-segs and that of half-shifted vertical BSG-segs. For every adjacent pair of vertical BSGsegs, the relation of right-of (or the inverse, left-of) is dened naturally. These horizontal relations are represented by a directed acyclic graph G v (V v ;E v ), called the BSG-constraint graph, where a grand source and grand sink are added to represent the left and right limits. The denition will be evident from exales shown in Fig. 1(B) (left). The vertical relation between horizontal BSG-segs is analogously represented by BSG-constraint graph G h (V h ;E h ) as shown in the gure (right). In drawing these constraint graphs over the BSG in a fashion as in the gure, each edge, say e, crosses a unique room, say r. Then, for silicity, e (dened on the constraint graph) and r (dened on the BSG) are referred to each other as \the room crossed by e" or \the edge that crosses r". BSG-based packing algorithm, called BSG-PACK, is described in four stages as follows. See an illustrative exale in Fig. 1. procedure BSG-PACK 1 Readers who are familiar with the BSG, this section can be skipped. 1. (Assignment) Modules are assigned to the BSGrooms, at most one module to one BSG-room. 2. (Edge weight) If a room r is assigned with module M whose width is w, give weight w to the edge of G v (V v ;E v ) that crosses the room. Edges incident to the grand source and sink are weighted with. Analogously, edges of G h (V h ;E h ) are weighted according to the height of modules.. (Longest path length) For each vertex v of G v (V v ;E v ), nd the length x(v) of the longest path from the grand source to v. Similarly, for each vertex u of G h (V h ;E h ), nd the longest path length y(u) from the grand source. 4. (Allocation) Place the vertical BSG-seg corresponding to v in G v (V;E) at horizontal position x = x(v). And place the horizontal BSG-seg corresponding to u at vertical position y = y(u). (The length of the BSG-segs are assumed exible. Therefore, the length of each vertical seg and that of each horizontal seg are automatically determined as long as they are not intersected.) Then each module is legally embedded. The following fact makes BSG-PACK unique. Fact 2.1 There exists an assignment that corresponds to a packing of the minimum area, if the size of the BSG is not smaller than n2n, where n is the number of modules. This ilies that an exactly optimum packing can be obtained in a nite time. Since exhaustive search is iractical by the coutation resource, a simulated annealing was proposed and tested in [1], showing a superior performance. Packing Including Pre-Placed Modules We enhance BSG-PACK to accept pre-placed modules. Pre-placed modules are called p-modules, and the other oating modules f-modules. If we were to assign f-modules and p-modules together to the BSG without discrimination, there would be contradictions between left-right-above-below relations in BSG and the coordinates specied. Accordingly, we take a strategy that (i) p-modules are not assigned to BSG, and that (ii) f-modules are placed so as not to overlap p-modules by modifying the calculation of the longest path in BSG-PACK. To embody the strategy, key procedures will be to check whether an f-module is overlapping with p- modules or not, and to avoid overlapping by shifting f-modules. We develop corresponding procedures TWIST BSG-PACK and SHIFT f-module. TWIST BSG-PACK is described as follows.

3 BSG-segs BSG-room a d r, b (A) Assignment (BSG 2) t h c r,2 r,1 r 1,1 r, r 1, r 2, s v s v 9 G v (Vv,Ev ) 11 t v 9 G h ( V h,e h ) s h (B) Edge weight 9 11 t v t h 9 (C) Longest path length b a c d (D) Allocation 4 4 s h Fig.1: An exale of BSG-based packing procedure TWIST BSG-PACK 1. Place all p-modules at the specied coordinates and assign all f-modules to BSG p2q. 2. Set the coordinates of all vertical and horizontal segs at.. Dene the twist order of rooms as: r ;=r ;1;r 1;=r 2;;r 1;1;r ;2=:::=r p1;q1: The twist order for BSG 424 is shown in Fig Calculate the size of each room and the coordinates of the f-module assigned to the room in order of the twist order as follows. For room a, let the x-coordinates of left and right segs of a be x l and x r, respectively. Similarly, let the y-coordinates of top and bottom segs of a be y t and y b, respectively. Fig.2: The twist order corresponding to BSG 424 (i) if a is ety, update the value of segs as x r max(x r ;x l ), y t max(y t ;y b ) (ii) if f-module is assigned to a, set the coordinates of the left-bottom corner of at (x l ;y b ). For each p-module m p, apply SHIFT f- MODULE(, m p ). Then let the coordinates of right-top of be (x; y), and update the value of segs as x r max(x r ;x), y t max(y t ;y). Next we describe SHIFT f-module in the following. procedure SHIFT f-module(, m p ) 1. If does not overlap m p, the procedure terminates. 2. Choose either of h-shift and v-shift of arbitrarily, which are to move horizontally or vertically, respectively. If the choice is h-shift (or v-shift), set the x-(or y-)coordinate of the leftbottom corner of at that of the right-top corner of m p.. If overlaps with the other p-module, let the module be m p, return 1. Otherwise the procedure terminates. Fig. shows how to place the f-module in order not to overlap p-modules in TWIST BSG-PACK. We assume that there is no overlap between p- modules. And any pair of f-modules and p-modules has no overlap because of SHIFT f-module. Furthermore, since each f-module is assigned to the individual room of BSG, there is either vertical and horizontal relation between any pair of f-modules. Accordingly, there is no overlap between f-modules. The length of the twist order is R where R is the number of rooms. SHIFT f-module consumes O(M p ) time and the number of times to call SHIFT f-module in TWIST BSG-PACK is O(M p 1 M f ), where M p and M f are the number of p-modules and f-modules. However, each p-module appears at least

4 m p v-shift m p h-shift h-shift v-sihft m p v-shift Fig.4: An exale of SHIFT f-rectilinear Fig.: avoiding overlapping with m p in TWIST BSG-PACK once at step 2 in SHIFT f-module. So, since R M 2 and M p ;M f M, the time colexity of TWIST BSG-PACK can be considered to be O(M 2 ). Notice that if there are not any p-modules, a packing obtained by TWIST BSG-PACK is obviously equivalent to the one by BSG-PACK. Because the order of edges that cross rooms in the twist order keeps the topological order in calculating longest paths of G v and G h in BSG-PACK. And the time colexity of TWIST BSG-PACK is O(R). 4 Packing Including Rectilinear Modules In practical designs of ICs and PCBs, it is often that several modules are combined into one module to be handled together when mutual locations between those modules are specied. It means the necessity to handle rectilinear modules. Sile ideas were proposed for 'L' and 'T' shaped modules in [1, 7]. The proposing idea is targeting general shaped modules. A rectilinear module m is decoosed into a set of non-intersecting rectangles. This decoosition is not unique, but we x one and denote it as S(m) which is called rectangle-set of m. Select a rectangle in S(m) such that neither its left side nor bottom one is in contact with the other rectangles in m. It is not unique, but we x one and call it a master-module in m, and the other rectangles in S(m) are called slave-modules. The coordinates of the slave-modules are determined according to those of the master-module. We enhance the TWIST BSG-PACK in order to handle rectilinear modules by the following strategy. (i) Dene S(m) for each module m with its mastermodule. (ii) Place all p-modules as specied. (iii) For all f-modules, assign their master-modules to the rooms. (iv) Place each master-module by the assign- ment on BSG avoiding overlaps with the modules which are already placed, and then calculate the coordinates of the slave-modules. The enhancement is realized by introducing a procedure called SHIFT f-rectilinear instead of SHIFT f-module. procedure SHIFT f-rectilinear(, m p ) 1. If does not overlap l p, the procedure terminates. Otherwise, repeat the following step until there is no overlap between and l p. 2. Find a pair of overlapping rectangles l f and l p in S( ) and S(m p ), respectively. Apply SHIFT f- MODULE(l f, l p )toavoid the overlap, and update the coordinates of the other rectangles in S( ) according to the coordinates of.. If m p overlap with the other p-module, let the module be m p, return 1. Otherwise the procedure terminates. In Fig. 4, it is shown how to place in order not to overlap in SHIFT f-rectilinear. Furthermore, eloying this procedure SHIFT f-rectilinear, we enhance TWIST BSG-PACK so that rectilinear modules can be handled. We named it with the same name TWIST BSG-PACK as that in Section, since it coletely includes the previous procedure. procedure TWIST BSG-PACK 1. Place all p-modules at the specied coordinates. 2. Set the coordinates all vertical and horizontal segs at.. Dene room sequence the twist order as described in Section. 4. Decoose each module into the rectangle-set with the master-module.

5 5. Assign master-modules to BSG p2q.. Calculate the size of each room and the coordinates of master-module assigned to the room in the twist order as follows. For room a, let the x-coordinates of left and right seg of a be x l and x r, respectively. Similarly, let the y-coordinates of bottom and top segs of a be y b and y t, respectively. (i) if a is ety, update the value of segs as x r max(x r ;x l ), y t max(y t ;y b ). (ii) if a master-module l is assigned to a, let the module containing l be m l, and set the coordinates of left-bottom of l at (x l ;y b ). For each p- modules m p, apply SHIFT f-rectilinear(m l, m p ). Then let the coordinates of right-top of l be (x; y), and update the value of segs as x r max(x r ;x), y t max(y t ;y). Regard m l as p- module. In this procedure, once f-modules are placed, they are considered as p-modules thereinafter. SHIFT f- RECTILINEAR places f-modules so as not to overlap p-modules. Accordingly, there is no overlap in the resultant packing. Naturally, introduction of rectilinear modules increases the coutational colexity. If the maximum number of rectangles in rectangle-sets is L, the time colexity ofshift f-rectilinear is O(L 2 1 M p ). Similarly to the discussion in Section, the time colexity of enhanced TWIST BSG-PACK can be considered to be O(M 2 L 2 ). 5 Experimental Results We ilemented TWIST BSG-PACK in the simulated annealing. Using an industrial PCB-data and randomly generated data, experiments show the eciency of our algorithms in the following. We briey describe about our simulated annealing. An initial solution is given arbitrarily. In order to generate a new solution from the current solution, our simulated annealing adopted the following operations as moves. 1. Interchange of contents of a pair of rooms degree rotation of an f-module. And we evaluate the minimum bounding box of all modules obtained by TWIST BSG-PACK, and adopt a standard annealing schedule for the cooling. 5.1 Packing Including Pre-Placed Modules First we are concerned with the relation between the numbers of p-modules and the quality of the chip area. We prepared inputs each of which consists of 2 rectangles including, 2, 5, 1, 2, 4,, or 1 p- modules. The size of each rectangle is generated automatically according to the size of the modules of the practical PCB. We chose rectangles as p-modules from the largest in area and specied the coordinates so that the area of the minimum bounding box of the p-modules is less than the sum of the area of all rectangles. This specication is because that experts of PCB designs say that the modules with larger area tend to be p-modules. We used BSG 222 and ilemented TWIST BSG- PACK in two ways. One is to choose randomly the direction for an f-module to be shifted in SHIFT f- MODULE, while the other is to choose the direction according to the shortness of the distance for the f- module to be shifted. The latter is referred to SHIFT f-module'. Fig. 5(A) shows the relation between the number of p-modules and the quality of the resultant chip when SHIFT f-module or SHIFT f-module' is used in TWIST BSG-PACK. Each point on the graph represents the average of three trials as altering the random seed in simulated annealing. It is interesting to observe that the resultant area is independent of the number of p-modules, although this may depend on the coordinates of p-modules specied. The quality attained by our methods is very satisfactory. We are also concerned with the relation between the number of p-modules and the coutation time. In Fig. 5(B), the experimental results are shown. When the number of the p-modules is less than half of the total number of modules, the CPU time increases proportional to the number of p-modules. This is explained by the fact that the number of times to call SHIFT f-module is O(M p 1 M f ) which reect the coutation of checking overlaps among the f-modules and the p-modules Second, we applied our method to an industrial PCB-data with 14 modules. Here we specied the coordinates of largest 7 modules in area. In Fig. (A), a resultant chip layout is shown. For coarison, the chip layout without p-modules in [1] is shown in Fig.. We observe that our chip is enough coacted in spite of constraint caused by the existence of p-modules. 5.2 Packing Including Rectilinear Modules Finally, our experiments are to demonstrate the performance of TWIST BSG-PACK when rectilinear modules are included. We prepared an input with 1 modules including 7 rectilinear modules. As for the domain, we used BSG 222. The resultant chip layout is shown in Fig. 7, where the area is 1.7 times as large as the sum of the area of all rectangles. The CPU time was about 2 hours.

6 ratio of area Shift F-Module Shift F-Module (A) number of p-modules no. of p-modules v.s. chip area / area sum of modules CPU time (sec) Shift F-Module Shift F-Module number of p-modules (B) no. of p-modules v.s. co. time Fig.5: Packing of 2 modules with p-modules It was iressive that fairly colicated modules were embedded so nicely, even caves by the rectilinear modules were stued. Conclusion In 2-dimensional packing, which is one of the most iortant basic technologies for automation of PCB designs, we enhance the so-far proposed BSG based packing algorithm in a very reasonable way to be able to handle pre-placed modules and rectilinear mod- Fig.7: Packing of 1 modules including 7 rectilinear modules ules. Eirical results demonstrate that TWIST BSG- PACK achieves high performance to the limit as a packing algorithm. However, for applications in VLSI design, dierent development is need to answer the problems arisen from the requirement of wires, closeness, design rules and so on. Acknowledgments The authors are grateful to Mr. Eiichi Kaneko and his group, Apollo Co., for invaluable suggestions and supply of data of industrial PCBs. They also appreciate Prof. Mineo Kaneko, JAIST, and Prof. Atsushi Takahashi, TIT, for helpful advice and sincere discussions. References [1] S.Nakatake, K.Fujiyoshi, H.Murata, and Y.Kajitani, \Module Placement on BSG-Structure and IC Layout Applications," in Proc. of ICCAD pp , 199. [2] H.Murata, K.Fujiyoshi, S.Nakatake, and Y.Kajitani, \Rectangle-Packing-Based Module Placement," in Proc. of ICCAD pp , [] L.Sha and R.Dutton, \An Analytical Algorithor Placement of Arbitrarily Sized Rectangular Blocks," in Proc. of 22th DAC, pp2-, 195. [4] W.Dai, M.Sato, ande.kuh, \A Dynamic and Ecient Representaiton of Building-Block Layout," in Proc. of 24th DAC, pp4-49, 197. [5] A.Alon and U.Ascher, \Model and Solution Strategy for Placement of Rectangular Blocks in the Euclidean Plane," in Proc. of IEEE Trans. on CAD, vol.7, no., pp.7-, 19. [] T.Lee, \A Bounded 2D Contour Searching Algorithm For Floorplan Design With Arbitrarily Shaped Rectilinear And Soft Modules," in Proc. of th DAC, pp525-5, 199. (A) Including 7 p-modules (B) Including no p-modules (area: 5,2) (area: 14,9) Fig.: PCB industrial data which consists of 14 modules [7] M.Kang and W.Dai, \General Floorplanning with L- shaped, T-shaped and Soft Blocks Based on Bounded Slicing Grid Structure," in Proc. of ASP-DAC, pp25-27, [] M.Chi, \An Automatic Rectilinear Partitioning Procedure for Standard Cells," in Proc. of 24th DAC, pp5-55, 197.