An Energy and Traffic Aware Mapping Method for 3-D NoC-Bus Hybrid Architecture

Transcription

1 A ergy ad Traffic Aware Mappig Method for 3-D NoC-Bus Hybrid Architecture Taotao Zhag, Nig Wu, Fag Zhou, ad ei Zhou Abstract 3-D itegrated circuits (ICs) icrease the device desity ad reduce the delay of itercoects of dies by stackig two or more dies vertically. To take advatage of less eergy cosumptio i the vertical directio ad to solve the defect of poor heat dissipatio, a mappig method for 3-D NoC-Bus hybrid architecture is proposed based o the task graph. To achieve the two optimal goals, optimal eergy cosumptio ad optimal balaced distributio of traffic, we first calculate the optimal combiatios of buses usig backtrackig algorithm ad the filter out the optimal order of the odes o the buses by geetic algorithm. xperimetal results show that the optimal eergy cosumptio ca reduce trasmissio eergy by 35.5% compared with the optimal balaced distributio of traffic, ad the latter s variace of traffic distributio amog stacks ad horizotal layers is oly 5% of the former. Idex Terms etwork-o-chip (NoC), 3-D NoC-Bus, task graph, itercoect eergy, balaced distributio of traffic I I. INTRODUCTION N 3-D itegrated circuits (ICs), by usig through silico vias (TSVs), multiple plaar device layers are stacked ad bod together, as show i Fig. 1. As the gap betwee each layer is oly tes of micrometers, the legth of TSV is much smaller tha that of the horizotal lik, which is oly oe percet of the latter. As the itercoect distace betwee vertical adjacet cores is very small, little resistace ad capacitace is caused i TSVs. So whe trasmittig the same amout of data, TSVs cosume much less eergy tha horizotal liks [1]. To make better use of the advatages of TSV i 3-D ICs, the vertical itercoect utilizes a wide, low-latecy multi-drop bus, which formig 3-D NoC (etwork-o-chip) -Bus hybrid architecture []. The cores i the same stack are cotrolled by a cetralized Arbiter, i which flit ca be accessed i oly oe hop. Mauscript received July 0, 014; revised August 05, 014. This work was supported by the Natioal Natural Sciece Foudatio of Chia uder Grat (No , No ), the Idustry-academic Joit Techological Iovatios Fud Project of Jiagsu uder Grat (No.BY ), the Fudig of Jiagsu Iovatio Program for Graduate ducatio uder Grat (No.KYX_073), ad the Fudametal Research Fuds for the Cetral Uiversities. Taotao Zhag, the College of lectrical ad Iformatio gieerig, Najig Uiversity of Aeroautics ad Astroautics (NUAA), Najig 10016, Chia ( taotzhag@163.com). Nig Wu, the College of lectrical ad Iformatio gieerig, NUAA, Najig 10016, Chia ( wuee@uaa.edu.c). Fag Zhou, the College of lectrical ad Iformatio gieerig, NUAA, Najig 10016, Chia ( zfuaa@uaa.edu.c). ei Zhou, the College of Iformatio gieerig, Yagzhou Uiversity, Yagzhou 5009, Chia ( tomcat800607@16.com). Fig D itegratio usig TSVs However, 3-D ICs greatly icreased device desity, which itroduces serious thermal issues. As high temperature ca cause the chip ustable ad reduce the chip s lifetime, thermal issue becomes a major challege for 3-D itegratio. I the literature, may methods have bee proposed, such as icorporatig thermal vias ito itegrated circuits to mitigate thermal issues by lowerig the thermal resistace of the chip [3], plaig thermal via locatios durig floorplaig stages [4], coolig each level i the 3-D stack by microfluidic itercoects [5], schedulig dyamic thermally-aware job for 3-D systems [6], [7], desigig a OS-level schedulig algorithm that performs thermal-aware task schedulig o a 3-D chip [8], etc. I this paper, through distributig traffic uiformly to make a eve heat distributio, a ew method for mappig the task graph to 3-D NoC-Bus hybrid architecture is proposed. I additio to solve thermal issues, this algorithm ca also reduce commuicatio eergy by restrictig tasks withi the same stack. II. PRINCIPS OF TH PROPOSD MTHOD Ulike the traditioal 3-D NoC architecture, 3-D NoC-Bus hybrid architecture uses bus commuicatio i the vertical directio, as show i Fig.. Fig.. 3-D NoC-Bus hybrid architecture

2 Sice the architecture oly eeds oe hop commuicatig o the bus, it greatly improves latecy performace of system i the 3-D NoC-Bus hybrid architecture. Because of the differece of trasmissio performace betwee TSV ad the horizotal lik, it takes two steps to map the task graph to the 3-D NoC-Bus hybrid architecture. First, map the odes of the task graph to the stacks (buses) which eed to break the tree structure of the task graph ito liks usig backtrackig algorithm. It starts with the root ode of the tree ad goes to the child ode of curret ode. If curret ode that is a cross poit has multiple odes, go small ode first. Util reach the ed of the lik, go back to the cross poit to fid aother lik. Traversig all the liks i the steps of the umber of layers of 3-D NoC-Bus hybrid architecture, which is also the umber of odes o the bus, ad the bus uits ca be foud. Combiig those uits to make combiatios of buses without a same ode ad screeig out the combiatios that meet the requiremets. Secod, map the odes o the buses to differet layers. Because of a permutatio ad combiatio of odes o the buses is a mappig result, there will be may results if there are may odes o a bus. We use geetic algorithm to geerate ew results ad filter the bad results geeratio to geeratio. Select the result meet the eeds best i the last geeratio as the last mappig result. A. Task Graph Aalysis III. TASK MAPPING I order to fully describe the mappig algorithm i this paper, we use Task Graphs for Free (TGFF) [9] to geerate a 0-ode task graph radomly, as show i Fig. 3. Fig ode task graph Task graph is a acyclic directed graph derived from a special foreseeable applicatio. I the graph, every ode represets a task to be assiged to the core. Nodes coect to each other if they have commuicatio requiremet with other odes. The weight o the edge deotes the commuicatio data volume betwee the correspodig odes. Accordig to the umber N of odes i the task graph ad the layers eed to be geerated, a 3-D NoC-Bus hybrid architecture ca be fialized via the followig iequatio ad equatio: ( 1) N N N / N is the miimum iteger bigger tha N/, which deotes the maximum odes i the task graph ca be allocated i a layer. If N <, other - N odes should be added to the 3-D NoC-Bus hybrid architecture. Whe the task graph i Fig. 3 is mapped to the D NoC-Bus hybrid architecture, layers of the architecture will be allocated 7 odes, ad 6 odes i the remaiig layer. I additio, it takes 7 additioal odes to fill the architecture. Sice the commuicatio betwee the odes are very differet, how to layout this odes will make great impact o system performace. Cosiderig trasmittig i TSVs ot oly ca reduce much eergy tha i horizotal liks [1] but also has a greater ifluece o the heat dissipatio [10], [11], [1], the promised algorithm maps the odes i the stack first ad the maps the odes i the horizotal layers. B. Mapped to the Stacks To assig the odes i the task graph to the stacks, backtrackig algorithm is utilized. The proposed method break up the tree structure ito several liks accordig to the paret-child relatioship odes. First, look for liks from the root ode ad go the path of small ode preferetially whe come across a bifurcate poit. Util reach the ed ode, the retur to the bifurcate poit ad fid other liks recursively. Doig i this way ca esure that the correlative odes are allocated i the same stack. As show i Fig. 3, to map the task graph i a D NoC-Bus architecture, 0 odes should be mapped to 7 stacks, oe of which cotais two TAB I INKS FOUND FROM TH TASK GRAPH ik odes ad each of the other cotais 3 odes. Doe i accordace with the above, the task graph ca be broke ito 3 liks, as show i Table I. Secod, after fidig out all the liks, traverse the odes o the liks usig as a uit. Put the uits that do t cotai the No. (1)

3 same ode together as a combiatio of stacks. If the umber of uits that do t cotai the same ode is smaller tha the umber of stacks we eed, fid other uits usig - 1 as a uit i the rest odes, which are ot i the uits, as show i Fig. 4. ) Optimal Balaced Distributio of Traffic To allocate the tasks averagely to the 7 stacks, which ca obviously form a uiform distributio of heat to solve the thermal issues, we use S v, the variace amog the commuicatio data volume of the stacks, as a yardstick to measure the degree of uiformity of traffic i each stack. Fig. 4. Method of fidig the uits i a lik A, B, C ad D represet the odes i a lik of the task graph. is the umber of layers (the umber of odes a stack icludes). As is calculated, bit trasmissio cost the horizotal lik 0.17 pj ad the TSV pj [1]. Bit trasmissio eergy for TSV is oly 7.5% of that of horizotal lik. So it ca reduce plety of commuicatio eergy if aggregates tasks withi the same stack. But the more tasks cluster i the same stack, the more power desity of this stack icrease, which will be likely to geerate a hot spot. This paper maps the odes of the task graph i two extreme ways, the optimal eergy cosumptio ad the optimal balaced distributio of traffic. The former oly cosiders aggregate as may tasks as we ca i the same stack to save maximum commuicatio eergy ad the latter just takes a average allocatio i the stacks to make a uiform distributio of heat. Accordig to the eeds, cosiderig them both is a good method to make a tradeoff betwee eergy cosumptio ad heat dissipatio. They ca be gotte at the same time due to they are ot a iverse relatioship. 1) Optimal ergy Cosumptio 6 stacks of 3 odes ca be foud from the liks i Table I, ad the rest two odes is allocated i the last stack. As the proposed method computed, there are 41 kids of combiatios. Whe oly cosiderig eergy cosumptio, aggregatig tasks i the same stack, usig F stacks as the degree of aggregatig tasks, result ca be reached whe F stacks is the maximum of the combiatios as show i Fig. 5. The * i Fig. 5 represets the ode additioal added. S v i 1 ( F ) deotes the average value of all the stacks. Via this equatio, the result of optimal balaced distributio of traffic ca be foud whe S v is the miimum of the combiatios, as show i Fig. 6. Fig. 6. Map of stacks of optimal balaced distributio of traffic C. Mapped to the Horizotal ayers xcept the two optimal combiatios of buses above, we ca also fid other combiatios that meet our requiremets ad uite the result mappig to the horizotal layers to fid the best mappig result amog them. Due to the trasmissio betwee odes o the bus just eed a sigle hop, it has little impact how to arrage the odes o the stack. So the odes o the bus ca be sorted casually ad what the proposed method eed to do is fidig out which arragemet of the odes o the buses is the best. Geetic algorithm is used to fid the best permutatio we eed. A model of chromosome is created i this algorithm, as show i Fig. 7. vi (3) F stacks F vi i1 () F vi represets the commuicatio data volume of each stack. Fig. 5. Map of stacks of optimal eergy cosumptio Fig. 7. The way of chromosomal heredity of the geetic algorithm of the proposed method

4 The legth of the chromosomal which has multilayer structure is equal to the umber of bus eed to be mapped. A bus represets a deoxyriboucleic acid (DNA) i the chromosome. very chromosome has oly oe ustable DNA (coected with dashed lies i Fig. 7) that is susceptible to mutatio. A mutatio or exchage of chromosomes is equivalet to chage the odes sort o the buses. To choose the best chromosomes we eed, a list of total commuicatio data volume belog to each ode is created. code each DNA i the chromosomes to sum the total commuicatio data volume of each layer. To achieve a balaced traffic of each layer, we use S, variace amog the commuicatio volume of the layers, to measure the degree of uiformity of traffic i each layer. (a) Optimal ergy Cosumptio S i1 ( i1 i F j j( i1) ( 1) F / i ) (4) represets the umber of layers of chromosomes. represets the average value of the layers. F j deotes the total commuicatio volume flowig through the ode j. j is recoded accordig to the structure of chromosomes. For example, F 10 of Chromosome A i Fig. 7 represets the total commuicatio volume of ode 16 of the task graph i Fig. 3, which is Mb. Ulike the very low probability of gee mutatio i the ature, here the mutatio should have high probability to keep the diversity each geeratio. The sort chromosomes i ascedig order by S ad keep the previous 50 chromosomes that meet the eeds ad reset all the ustable DNAs i the chose chromosomes to esure diversity each geeratio. Util the last geeratio, choose the first chromosome as the best mappig result of horizotal layers. I the experimet, the iitial populatio size is 100, the crossover rate is 0.8, the mutatio rate that is big here is 0.5, the maximum evolutio geeratio is 500 ad the legth of chromosome is 7. The mappig results of horizotal layers of optimal eergy cosumptio ad optimal balaced distributio of traffic, which respectively are {{3, 1, 6, 11, 13, 1, 0};{8, 4, 5, 14, 16, 15, *};{9,, 7, 19, 17, 18, 10}} ad {{1, 11, 13, 6, 0, 7, 9};{4, 14, 16, 18, 3, 1, *};{5, 19, 17, 15,, 10, 8}}, ca be reached with the parameters beig set above. IV. MAPPING RSUTS ANAYSIS I the experimet of this paper, we foud two optimal mappig results, optimal eergy cosumptio ad optimal balaced distributio of traffic, based o the task graph i Fig. 3. Uite the mappig results of stacks ad the mappig results of horizotal layers, the fial mappig results of 3-D NoC-Bus hybrid architecture ca be derived as show i Fig. 8. (b) Optimal Balaced Distributio of Traffic Fig. 8. Mappig results of the two optimal goals of 3-D NoC-Bus hybrid architecture Assumig D is the Mahatta distace betwee two odes i the 3-D NoC-Bus hybrid architecture. D D horizotal D vertical So the D horizotal of ode 11 ad ode 8 of the optimal balaced distributio of traffic i Fig. 8 is 3 ad the D vertical is. Usig the Mahatta distace, we ca calculate the eergy cosumptio durig commuicatio by the followig equatio. lik horizotal horizotal D horizotal vertical 1/ ChorizotalVdd D vertical horizotal is determied by the physical capacitace of horizotal lik C horizotal, supply voltage V dd ad activity factor α of the etwork commuicatio [1]. vertical ca be calculated i a similar maer like horizotal i (6). Accordig to the techology metioed i literature [1], bit trasmissio eergy ca be respectively calculated as 0.17 pj ad pj of horizotal lik ad vertical lik. With that, the total trasmissio eergy of optimal eergy cosumptio is.05 uj, just 64.5% of the trasmissio eergy of optimal balaced distributio of traffic, which is 3.19 uj. Although optimal eergy cosumptio ca save much eergy tha optimal balaced distributio of traffic, but the traffic distributio has large gap betwee stacks ad layers, which is ot coducive to system heat dissipatio. The differece of traffic distributio betwee optimal ways is (5) (6)

5 obvious, as show i Fig. 9. eergy savig solutio by usig the proposed method uder the circumstace that each stack s temperature is less tha the threshold temperature. Fig. 10. Map of optimal balaced distributio of traffic uder F stacks 1Mb Fig. 9. Traffic distributio of the two optimal goals of 3-D NoC-Bus hybrid architecture No matter amog stacks or layers, it is obvious that the traffic distributio is more uiform i optimal balaced distributio of traffic tha optimal eergy cosumptio. The sum of variaces of the stacks ad layers commuicatio data volume of the optimal balaced distributio of traffic is oly 5% of the optimal eergy cosumptio. The two optimal ways tested here are two extreme ways, oe of which oly cosiderig reducig trasmissio eergy, ad the other is just for the sake of heat dissipatio. Cosiderig both of them by uitig F stacks i () ad S v i (3), the uified equatios ca be represeted by (7). F stacks F mi S v Smax ( S v ) Max ( F stacks or (7) Mi ) F mi ad S max are set accordig to the results of bus combiatios. O the basis of bus combiatios i the step of mappig to stacks, we set F mi = 1 Mb ad the map of optimal balaced distributio of traffic ca be gotte as show i Fig. 10. Usig (6), the total trasmissio eergy i Fig. 10 is.665 uj, accoutig for 83.6% ad 130.% of optimal balaced distributio of traffic ad optimal eergy cosumptio. Ad the sum of variaces of the stacks ad layers commuicatio data volume is betwee the variaces of the two optimal goals, too. By settig some other costraits, the proposed method ca be used further. Such as, fid the relatioship betwee the stack s temperature ad commuicatio data volume. Defie a threshold temperature of stacks, ad we ca fid the most V. CONCUSIONS The proposed method is used to fid a good map to the 3-D NoC-Bus hybrid architecture based o the task graph. I the experimets, the optimal eergy cosumptio ca reduce trasmissio eergy by 35.5% compared with the optimal balaced distributio of traffic, ad the commuicatio data volume of the equalizatio is more uiform tha the optimal eergy, which is coducive to heat dissipatio. Ad the two optimal goals ca be cosidered both by a compromise optimizatio goal betwee them. RFRNCS [1] Cheg Y, Zhag, Ha Y, et al. Thermal-costraied task allocatio for itercoect eergy reductio i 3-d homogeeous mpsocs[j]. Very arge Scale Itegratio (VSI) Systems, I Trasactios o, 013, 1(): [] i, Feihui, et al. "Desig ad maagemet of 3D chip multiprocessors usig etwork-i-memory." ACM SIGARCH Computer Architecture News. Vol. 34. No.. I Computer Society, 006. [3] Gople, Bret, ad Sachi Sapatekar. "Thermal via placemet i 3D ICs."Proceedigs of the 005 iteratioal symposium o Physical desig. ACM, 005. [4] Wog, ric, ad Sug Kyu im. "3D floorplaig with thermal vias." Desig, Automatio ad Test i urope, 006. DAT'06. Proceedigs. Vol. 1. I, 006. [5] Bakir, Muhaad S., et al. "3D heterogeeous itegrated systems: iquid coolig, power delivery, ad implemetatio." Custom Itegrated Circuits Coferece, 008. CICC 008. I. I, 008. [6] Cosku, Ayse Kivilcim, et al. "Dyamic thermal maagemet i 3D multicore architectures." Desig, Automatio & Test i urope Coferece & xhibitio, 009. DAT'09.. I, 009. [7] Zhu, Chagyu, et al. "Three-dimesioal chip-multiprocessor ru-time thermal maagemet." Computer-Aided Desig of Itegrated Circuits ad Systems, I Trasactios o 7.8 (008): [8] Zhou, Xiuyi, et al. "Thermal-aware task schedulig for 3d multicore processors."parallel ad Distributed Systems, I Trasactios o 1.1 (010): [9] Dick, Robert P., David. Rhodes, ad Waye Wolf. "TGFF: task graphs for free." Proceedigs of the 6th iteratioal workshop o Hardware/software codesig. I Computer Society, [10] Zhou, Xiuyi, et al. "Thermal-aware task schedulig for 3d multicore processors."parallel ad Distributed Systems, I Trasactios o 1.1 (010): [11] Baerjee, Kaustav, et al. "3-D ICs: A ovel chip desig for improvig deep-submicrometer itercoect performace ad systems-o-chip itegratio."proceedigs of the I 89.5 (001): [1] Xie, Yua, et al. "Desig space exploratio for 3D architectures." ACM Joural o mergig Techologies i Computig Systems (JTC). (006):