Generate more. vectors
|
|
- Henry Sanders
- 6 years ago
- Views:
Transcription
1 Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment Ashish Giani Shuo Sheng and Michael S. Hsiao y Vishwani D. Agrawal Intel Corporation Dept. of ECE, Rutgers University Bell Labs Hillsboro, OR 9 Piscataway, NJ 88 Murray Hill, NJ 9 asgiani@ichips.intel.com hshuo, mhsiaoi@ece.rutgers.edu va@research.bell-labs.com Abstract This new method of built-in self-test (BIST) for sequential cores on a system-on-a-chip (SOC) generates test patterns using a real-time program that runs on an embedded processor. Alternatively, the same program can be run on an external low-cost tester. This program generates patterns using circuit-specic spectral information in the form of one or more Hadamard coecients. The coef- cients are extracted from high fault-coverage compacted pattern sets. When an embedded processor is available on SOC, the overhead is negligible. Also, sequential cores are tested in the functional mode, avoiding activation of nonfunctional timing paths. We present experimental results to show that for hard totestcircuits, with any given test time, spectral patterns provide signicantly higher fault coverage than weighted-random patterns. I Introduction Improvements in VLSI technology in terms of gate density and increased clock speeds have made VLSI testing an integral part of chip design. Technology advances are resulting in higher operating speeds, and test equipment will fall short on keeping pace with this growing speed of circuits, thus preventing \at speed" test and measurement. Consequently, built-in-self-test (BIST) has emerged as a promising solution to the test problem. In addition, the recent trend of core-based system-on-a-chip (SOC) design hampers testability ofembedded cores due to limited accessibility. This makes BIST the most suitable methods for testing embedded cores in the SOC environment. The main components of a BIST system are a test pattern generator that applies a sequence of patterns to the circuit under test (CUT), a response compacter that compacts the responses into a signature, and a signature comparator that compares the signature to a faultfree reference value. Due to their low hardware costs, BIST based on random patterns is very attractive. Linear feedback shift registers (LFSRs) are commonly used as Formerly with Dept. of ECE, Rutgers University, Piscataway, NJ 88 y Supported in part by an NSF Career Award, under contract CCR-93. pseudo-random test pattern generators in BIST schemes. They have a simple structure and can also be used as output response analyzers, thereby serving a dual purpose []. However, this technique generally results in large test sets []. Besides, the quality of the LFSR-generated test set depends on the CUT [3]. This is because some signals in the circuit may not be set to specic logic values using pseudo-random vectors, making faults on those signals hard to detect. Weighted random patterns have been found to yield better fault coverage in circuits that contain such random-pattern-resistant faults [{8]. In these approaches, the probability of obtaining a or a at a particular input is biased towards detecting random pattern resistant faults. Weighting the pseudo-random patterns [, 9] is done using counter-based schemes [, ] or performing bit-xing (pattern mapping) []. The disadvantages are additional area and delay overheads. One way toovercome these drawbacks is to design the LFSR by selecting good seed and feedback polynomial [3{]. However, test sequences with acceptable test length and fault coverage are obtained at the expense of area overhead required to store seeds. Also, the complexityofcomputation of the seeds [] rapidly increases with the number of primary inputs. Ecient hardware pattern generators [,8] often round-o optimal weights, hence producing patterns that are sub-optimal for certain circuits. In sequential circuits, faults may need a biased internal state in addition to biased input values, making it more dicult to obtain a good set of weights. Deterministic BIST techniques such as stored pattern testing involve the application of specic test vectors, each providing an increase in fault coverage. However, a high cost is associated with the storing of the large number of patterns. Walsh and Rademacher-Walsh function analyses have been proposed in the past [8, 9] only for response compaction. Their present application in vector generation is novel and has signicant advantages not perceived before. An embedded controller or processor on an SOC makes it possible for the processing unit to generate patterns to test the rest of the chip [{]. This alleviates the need for additional hardware such as LFSRs to test the other embedded cores/peripherals. For testing embedded processors by some proposed methods [, ] random oper- 93-/ $. c IEEE 3 Proc. 9th IEEE VLSI Test Symp., Apr.-May
2 ations and operands are generated to test ALUs within DSP cores. Random test patterns can also be generated by an embedded processor [, 3]. Deterministic BIST for accumulator-based processors to avoid instructionimposed constraints has also been proposed []. In this paper, we propose a new spectrum-based BIST technique for SOC's with an embedded processor. This spectrum-based testing method generates vectors by using the information provided by each core designer. We analyze the given information of an embedded core to obtain a spectral characteristic for the input test patterns [,]. To do this, we view the core as a digital system that is described by input-output signals. A signal in a digital (or analog) circuit is a function of time. Any such function can be represented and reproduced in the time-domain, using its frequency-domain spectrum. A random signal (which is noise-like) contains a very wide spectrum. By properly restricting the spectrum, we can generate signals that are more useful than random signals. However, the determination of the spectrum should be based upon the \usefulness" criterion. In the present work we are concerned with the capability of the input signals of a digital circuit in detecting faults. In studying a signal, what we care most is the predictability of the signal. If the signal is predictable, we can use a portion of it (the past and the current) to represent and reconstruct it in entirety. For digital circuits, Hadamard functions can be used to represent the spectral information. We will determine Hadamard coecients for input patterns that have a high fault coverage in a given sequential circuit. Using just a few coecients, a pattern set can be generated, which preserves the characteristics relevant to fault detection, while randomly changing others. Self-test of embedded cores, then, becomes a problem of constructing a set of waveforms, which when applied at the primary inputs of the core, can excite and propagate targeted faults in the core. In order to capture the spectral characteristics of a given signal, a noise-free representation for that signal is desired (wider spectra lead to more unpredictable/random signals). Thus, any embedded noise should be ltered. Static test set compaction [, 8] reduces the size of the test set by removing any unnecessary vectors while retaining the useful ones. In other words, static compaction lters unwanted noise from the derived test sequence, leaving a cleaner signal (narrower spectrum) to analyze. Applying this idea to generating vectors for BIST, the derived spectral information not only helps to identify embedded spectral information, but also oers a new way of testing sequential circuits by predicting intelligent vectors based on the vectors we have so far. Vectors generated from a selected spectrum have better fault detection characteristics. The remainder of the paper is organized as follows. Section II gives an overview and motivation for the new spectral BIST. Section III discusses the details of spectral characteristic extraction. Section IV explains the application of such information to BIST. Section V reports the experimental results, and Section VI concludes the paper. II Overview and Motivation Spectral decomposition is the most commonly used technique in signal processing. A signal can be projected onto a set of independent waveforms that have dierent frequencies. This set of waveforms, each represented as a vector, forms a basis matrix. The projection operation (a post-multiply to the basis matrix) reveals the quantity each basis vector contributes to the original signal. This quantity is called decomposition coecient. Subsequently, enhancing the important frequencies and suppressing the unimportant ones (\noise"), we expect that we can have a new and higher-quality signal that will help test generation. In choosing the projection matrix, Hadamard transform is a well-known non-sinusoidal orthogonal transform used in signal processing [9]. A Hadamard matrix consist of only 's and -'s, which makes it a good choice for the signals in VLSI testing ( = logic, - = logic ). Each basis in the Hadamard matrix is a distinct sequence that characterizes the switching frequency between s and -s. We will use Hadamard transform for our analysis. Hadamard matrices are square matrices containing only s and -s, and can be generated using the following recurrence relation: H(k) = H(k ; ) H(k ; ) H(k ; ) ;H(k ; ) k = ::: n where H() = and n = log N. For example, with k = and k =,above equation yields 3 H() = H() = ; ; ; ; ; ; ; From this denition of the Hadamard matrix, we can observe that H(n) H(n) T = ni n, where I n is the n n identity matrix. Given only 's and -'s in the matrices, multiplication can essentially be computed using additions and subtractions. Moreover, the inverse transform of a Hadamard matrix is the same as the forward transform, making reconstruction straight-forward. Each row/column in a Hadamard matrix is a basis vector, carrying a distinct frequency component. Taking H() for illustration, the four basis vectors are [ ], [ ], [ ], and [ ]. Any bit sequence of length can be represented as a linear combination of these basis vectors. For instance, the vector [ ] can be written
3 Vector set (initially random) Gate-level fault sim. and vector compaction Replace with compact vectors User encoded program to generate BIST vectors using Hadamard coeff. Append vectors Extract Hadamard coeff. from compacted vectors Hadamard coefficients Performed by core provider Fault coverage or max. iterations? Yes Extraction completed No Generate more vectors Performed by embedded CPU on SOC Figure : Extraction and application of Hadanard coe. as ;[ ]+[ ; ;]+[ ; ;]+ [ ; ; ]. Therefore, we can project the test sequence to the Hadamard basis components, lter out certain components and do an inverse transform to get the de-noised sequence. Figure presents the overall framework for extracting the spectral characteristics by the core provider. Then, the coecients are used to generate BIST vectors in the SOC. The coecient extraction is done iteratively. Initially (iteration ), the test set simply consists of random vectors. A call to static compaction lters any unnecessary vectors without lowering the fault coverage. Using the Hadamard transform on the compacted vectors, we analyze and identify the predominant Hadamard components at each primary input. We use this information to generate additional test vectors based on the identi- ed spectrum. We may also generate vectors by spanning the likely vector space using only the basis components. This helps to drive the circuit into hard-to-reach states and gives us more information about the characteristics of the CUT. This process is repeated until a preset number of iterations is reached. During this process, the spectral characteristics for all primary inputs of the circuit are collected and stored. The gathered coecients accompany the core, and are used to generate test sequences during BIST. III Spectral Characteristics Extraction BIST techniques based on LFSRs use weighted random vectors to enhance fault coverage. The drawbacks of these techniques are often insucient fault coverage, long test sequences and extra hardware. The goal of the present spectrum-based BIST technique is to extract information embedded in the CUT in the form of Hadamard coef- cients to create suitable vectors during BIST and overcome the above drawbacks. Because of the way Hadamard coecients are obtained, the patterns have high fault coverage. Besides, they resemble \functional" patterns and allow the technique to be applied to sequential circuits. In the procedure of Figure, the core provider may use the following algorithm: Algorithm : Let a i be the input bit sequence for primary input i. /* coecient extraction */ for (each primary input i in test set) coecient vector c i = H a i for (each value in the coecient matrix [c ::: c n ]) if (absolute value of coecient < cuto) Set the coecient to. else Set the coecient to or -, based on its abs value. /* generation of vectors based on coecients */ for (each primary input i) extension vector e i = modified c i H if (weight > ) Extend the vector set with valuetopii. else if (weight < ) Extend the vector set with value - to PI i. else if (weight ==) Randomly extend the vector set with either or - To illustrate Algorithm, let us consider a subsequence of eight -input vectors. We rst replace each '' with with a -: PI PI PI PI 3 PI PI PI PI 3 - replace - - with ;! Next, we perform spectral analysis. Consider the bit stream for primary input PI. Multiplying H(3) with the bit stream for PI,we obtain its coecient vector: ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; = ; ; ; If the cuto for coecients is set to, then the coecient vector c i is modied by replacing every coecient whose absolute value is less than with. Thus, the new c becomes [] T. Multiplying the new coecient [c ] T with H(3) yields: [] H(3)=[ ; ; ; ; ] We willextend the test set for PI with (, -,, -,, -,, -). Here, we have ltered out the higher order
4 Hadamard components that contribute to randomness in the input bit stream, since bit # has been changed from to-. Now, let us consider a dierent primary input PI 3. Multiplying H with PI 3 yields coecients shown below: ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 3 ; ; ; ; 3 = ; ; ; If the cuto for coecients is again, then the coecient vectorischanged to [ ;;;]. Multiplying the new coecient with H(3) yields the following extension vector: [ ; ; ; ] H(3) = [; ; ; ; ] Extending the compacted vector set for PI 3, we obtain scaled vector (-,, -,,, -, - ). This is the same as the input sequence, which means that there was no random noise that needed ltering. Similarly, we obtain extended vector sets for PI and PI as (,,,,,,, ) and (, -, -, -,, -, -, -). Thus, we append the following newly generated vectors to the test set: The coecients may also be computed with or without overlapping bit streams. Let us consider H(3) without overlapping. Bits - of a PI are rst multiplied with H(3) to get Hadamard coecients. Then, bits 8- are considered, followed by bits -3, and so on. When considering overlapping of bits during coecient extraction, bits - of a PI are rst multiplied by H(3) to get Hadamard coecients. Then, bits -8 are considered, followed by bits -9, and so on. Overlapping will identify cases where the inherent temporal correlation is more pronounced [,]. We repeat this process a maximum of times, and average the coecients obtained for the iterations. IV Use of Spectral Information for BIST We now use the Hadamard coecients obtained to generate vectors for BIST in a System-on-a-chip (SOC) environment. We make the assumption that a SOC containsacentral processing unit (CPU). In such a system, the CPU can be used to generate test vectors for other cores/peripherals in the system. Thus, we willnot have 3 to depend on specic hardware such as LFSRs to generate patterns for testing other devices on the chip, but can generate vectors using spectral testing. These vectors are generated based on the spectral information extracted by the core provider. Here, we use the technique described in the previous section to generate the spectral coecients, since this technique extracts the dominant strain in the input bit stream rapidly. Generation of vectors by spanning the spectral coef- cients would lead to the test set having only twice as manyvectors as the size of the original test set used to derive the Hadamard coecients. In order to generate more vectors, we can duplicate some vectors this is shown in Algorithm. H() is used in Algorithm and the values of the coecients range between + and -. Algorithm : Assign a cuto value of. Generate a set of vectors from coecients. Randomly duplicate p vectors during generation of vectors Assign a cuto value of 8. Generate a set of vectors from coecients. Randomly duplicate p vectors during generation of vectors Assign a cuto value of. Generate a set of vectors from coecients. Randomly duplicate p vectors during generation of vectors In Algorithm, we rst generate vectors from the coecients using a cut-o value of for the Hadamard coecients. While generating vectors, we duplicate an arbitrary number (p) ofvectors a few cycles. We repeat this procedure increasing the cut-o value of the Hadamard coecients to 8 and, respectively. Increasing the cuto value is equivalent to ne-tuning the lter, leading to more rened information about the CUT. The overall application of BIST vectors to each embedded core is illustrated in Figure. The CPU takes Hadamard coecients provided by the core designer (computed using Hadamard transform) and generates corresponding BIST patterns from the coecients. The embedded CPU repeats this process for every embedded core/peripheral in the SOC. V Experimental Results All experiments were conducted on an Ultra SPARC with MB of RAM for some ISCAS 89 [3] and ITC 99 [3] benchmark circuits, all treated as nonscanned embedded cores in an SOC design. We compare our results obtained from spectral characteristics with the weighted random approach for BIST. In both cases,, BIST vectors were generated. The results for weighted random patterns are shown in column 3 of Table. In this case, ideal weights are used. However, since it is dicult to obtain the exact
5 Table : Coverage of, weighted-random and spectral patterns for BIST. Faults detected (highest coverage shown in boldface) Circuit Total Weighted-random patterns Spectral patterns Faults Ideal weights Rounded-o weights H() H() s s s 9 9 s3 8 s s s s88 8 s s b b b b b Total SOC Core/Peripheral (tested by BIST vectors generated by the CPU) CPU (use Hadamard coefficients to generate vectors for BIST) Core/Peripheral (tested by BIST vectors generated by the CPU) Figure : Use of Hadamard coecients for BIST. weights in hardware without incurring substantial overhead, we round o the obtained weights to the nearest quarter (.,. or.). The results for this technique are shown in column of Table. The results for the spectral BIST technique are shown in columns and of Table. For each circuit wehaveselected the matrix either for the overlapping input streams or for non-overlapping streams, depending on whichever provides higher fault coverage. We assume that such a selection can be easily made by the core provider. The Hadamard coeents are obtained from only iterations of compaction and coecent extraction (Figure ). Column gives results for the H() matrix, and column for the H() matrix. As shown in the table, in all cases, the results of our technique either surpass or equal the results obtained for the ideal weighted random technique. For some hardto-test circuits such as s38 and b, our technique is able to detect signicantly more faults than the weighted random BIST approach. For example, our technique detected faults for b while the ideal and roundedo weighted random patterns detected only 3 and 3 faults, respectively. For a given circuit, the size of the Hadamard matrix used to extract the input spectrum will inuence the nal fault coverage. This is because dierent circuits exhibit dierent spectral characteristics. For instance, in circuit s, H() (length of 3) produced the best result, while for all other circuits, H() (length of ) performed equal or better. The eect of overlapping input streams when computing the spectral coecients plays a role. Overlapping will benet fault detection when the embedded temporal correlation of input streams is large [, ]. VI Conclusion We have presented a novel spectral technique for BIST in the SOC environment. The core provider rst computes/analyzes the spectral characteristics for the core using the Hadamard transform. Vector sequences, then, can be represented as a linear combination (indicated by the Hadamard coecients) of the basis vectors (columns of the Hadamard matrix). These Hadamard coecients are then used by the embedded processor of the SOC to generate new BIST vectors for the cores/peripherals. Experiments conducted using this technique showed that
6 higher fault coverages can be obtained when compared to the LFSR-based weighted random pattern generation techniques, without incurring the overhead of additional test hardware. Future work should include a study of the optimal Hadamard matrix for given circuits. References [] B. Koenemann and J. Mucha and G. Zwieho, \Built- In Test for Complex Digital Integrated Circuits," IEEE J. Solid-State Circuits, vol. SC-, no. 3, June 98, pp [] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital System Testing and Testable Design, New York, NY: Computer Science Press, 99. [3] V. D. Agrawal, \When to use random testing," IEEE Trans. on Computers, vol C-, No., Nov. 98, pp. -. [] M. F. Alshaibi and C. R. Kime, \Fixed-biased pseudorandom built in self test for random pattern resistant circuits," Proc. Int. Test Conf., pp , 99. [] F. Muradali, T. Nishada, and T. Shimizu, \Structure and technique for pseudo random-based testing of sequential circuits," Journal of Electronic Testing: Theory and Applications, vol., Feb. 99, pp. -. [] M. Bershteyn, \Calculation of multiple sets of weights for weighted random testing," Proc. Int. Test Conf., pp. 3-, 993. [] H. J. Wunderlich, \Multiple distributions for biased random test patterns," Proc. Int. Test Conf., pp.3-, 988. [8] H. J. Wunderlich, \Self-test using unequiprobable random patterns," Proc. Fault-Tolerant Computing Symp., pp. 8-3, 988. [9] F. Muradali, V. K. Agarwal and B. Nadeau-Dostie, \A new procedure for weighted random built-in self-test," IEEE Int. Test Conf., pp. -9, 99. [] D. Kagaris and S. Tragoudas, \Generating deterministic unordered test patterns with counter," IEEE VLSI Test Symp., pp. 3-39, 99. [] S. B. Akers and W. Jansz, \Test set embedding in a builtin self-test environment," IEEE Int. Test Conf., pp. - 3, 989. [] M. Chatterjee and D. K. Pradhan, \A novel pattern generator for near-perfect fault coverage," IEEE VLSI Test Symp., pp. -, 99. [3] B. Koenemann, \LFSR-coded test patterns for scan designs," IEEE European Test Conf., pp. 3-, 99. [] S. Hellebrand, S. Tarnick, J. Rajski and B. Courtois, \Generation of vector patterns through reseeding of multiple polynomial linear feedback shift registers," IEEE Int. Test Conf., pp. -9, 99. [] S. Venkataraman, J. Rajski, S. Hellebrand and S. Tarnick, \An ecient BIST scheme based on reseeding of multiple polynomial linear feedback shift registers," IEEE Int. Conf. Computer-Aided Design, pp. -, 993. [] M. Lempel, S. K. Gupta and M. A. Breuer, \Test embedding with discrete logarithms," IEEE VLSI Test Symp., pp. -8, 99. [] C. Fagot, O. Gascuel, P. Girard and C. Landrault, \On calculating ecient LFSR seeds for built-in self-test," Proc. European Test Workshop, pp. -, 999. [8] A. K. Susskind, \Testing by Verifying Walsh Coecients," IEEE Trans. Computers, vol. C-3, no., Feb., 983, pp [9] T-C. Hsiao and S. C. Seth, \The use of Rademacher- Walsh spectrum in random compact testing," IEEE Trans. on Computers, Vol. C-33, October 98, pp [] K. Radecka, J. Rajski, and J. Tyszser, \Arithmetic builtin-self-test for DSP cores," IEEE Trans. CAD, vol., no., Nov. 99, pp [] J. Rajski and J. Tyszer, Arithmetic Built-In Self-Test for Embedded Systems, Prentice Hall, 998. [] S. Hellebrand and H.-J. Wunderlich, \Mixed-mode BIST using embedded processors," Proc. Intl. Test Conf., pp. 9-, 99. [3] R. Dorsch and H.-J. Wunderlich, \Accumulator based deterministic BIST," Proc. Intl. Test Conf., pp. -, 998. [] L. Chen and S. Dey, \DEFUSE: A deterministic functional self-test methodology for processors," Proc. VLSI Test Symp., pp. -,. [] S. Sheng, A. Jain, M. S. Hsiao, and V. D. Agrawal, \Correlation analysis of compacted test vectors and the use of correlated vectors for test generation," IEEE Intl. Test Synthesis Workshop, March,. [] A. Giani, S. Sheng, M. S. Hsiao, and V. D. Agrawal, \Correlation-based test generation for sequential circuits," Proc. IEEE North Atlantic Test Workshop,, pp [] I. Pomeranz and S. M. Reddy, \Vector restoration based static compaction of test sequences for synchronous sequential circuits," Proc. Intl. Conf. Computer Design, pp. 3-3, 99. [8] R. Guo, I. Pomeranz, and S. M. Reddy, \Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration," Proc. Design, Aut., and Test in Europe, 998, pp [9] A. V. Oppenheim, R. W. Schafer, J. R. Buck, Discrete- Time Signal Processing. Englewood Clis, New Jersey: Prentice Hall, Inc., 999. [3] F. Brglez, D. Bryan, and K. Kozminski, \Combinational proles of sequential benchmark circuits," Int. Symp. on Circuits and Systems, 989, pp [3] S. Davidson and Panelists, \ITC '99 benchmark circuits - preliminary results," Proc. Int. Test Conf., 999, pp.. also at 8
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST Madhavi Karkala Nur A. Touba Hans-Joachim Wunderlich Computer Engineering Research Center Computer Architecture Lab Dept. of Electrical
More informationBit-Fixing in Pseudorandom Sequences for Scan BIST
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 4, APRIL 2001 545 Bit-Fixing in Pseudorandom Sequences for Scan BIST Nur A. Touba, Member, IEEE, and Edward J.
More informationWITH integrated circuits, especially system-on-chip
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006 1227 Improving Linear Test Data Compression Kedarnath J. Balakrishnan, Member, IEEE, and Nur A. Touba, Senior
More informationImproving Encoding Efficiency for Linear Decompressors Using Scan Inversion
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering
More informationALTERING A PSEUDO-RANDOM BIT SEQUENCE FOR SCAN-BASED BIST
ALTERING A PSEUDO-RANDOM BIT SEQUENCE FOR SCAN-BASED BIST Nur A. Touba* and Edward J. McCluskey Center for Reliable Computing Departments of Electrical Engineering and Computer Science Stanford University
More informationDeterministic BIST ABSTRACT. II. DBIST Schemes Based On Reseeding of PRPG (LFSR) I. INTRODUCTION
Deterministic BIST Amiri Amir Mohammad Ecole Polytechnique, Montreal, December 2004 ABSTRACT This paper studies some of the various techniques of DBIST. Normal BIST structures use a PRPG (LFSR) to randomly
More informationAn Efficient Test Relaxation Technique for Synchronous Sequential Circuits
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits Aiman El-Maleh and Khaled Al-Utaibi King Fahd University of Petroleum and Minerals Dhahran 326, Saudi Arabia emails:{aimane, alutaibi}@ccse.kfupm.edu.sa
More informationSrikanth Venkataraman* Janusz Rajski* Sybille Hellebrand** Steen Tarnick*** **University of Siegen, Siegen, Germany
An Ecient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers Srikanth Venkataraman* Janusz Rajski* Sybille Hellebrand** Steen Tarnick*** *MACS Laboratory, McGill University,
More informationStatic Compaction Techniques to Control Scan Vector Power Dissipation
Static Compaction Techniques to Control Scan Vector Power Dissipation Ranganathan Sankaralingam, Rama Rao Oruganti, and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer
More informationEfficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition
Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition Jinkyu Lee and Nur A. Touba Computer Engineering Research Center University of Teas, Austin, TX 7872 {jlee2, touba}@ece.uteas.edu
More informationLow-Power Weighted Pseudo-Random BIST Using Special Scan Cells
Low-Power Weighted Pseudo-Random BIST Using Special Scan Cells Shalini Ghosh 1, Eric MacDonald 2, Sugato Basu 3, and Nur A Touba 1 1 Dept of Electrical & Computer Engg University of Texas at Austin Austin,
More informationDelay Test with Embedded Test Pattern Generator *
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 29, 545-556 (2013) Delay Test with Embedded Test Pattern Generator * Department of Computer Science National Chung Hsing University Taichung, 402 Taiwan A
More informationX(1) X. X(k) DFF PI1 FF PI2 PI3 PI1 FF PI2 PI3
Partial Scan Design Methods Based on Internally Balanced Structure Tomoya TAKASAKI Tomoo INOUE Hideo FUJIWARA Graduate School of Information Science, Nara Institute of Science and Technology 8916-5 Takayama-cho,
More informationOn Using Machine Learning for Logic BIST
On Using Machine Learning for Logic BIST Christophe FAGOT Patrick GIRARD Christian LANDRAULT Laboratoire d Informatique de Robotique et de Microélectronique de Montpellier, UMR 5506 UNIVERSITE MONTPELLIER
More informationN-Model Tests for VLSI Circuits
40th Southeastern Symposium on System Theory University of New Orleans New Orleans, LA, USA, March 16-18, 2008 MC3.6 N-Model Tests for VLSI Circuits Nitin Yogi and Vishwani D. Agrawal Auburn University,
More informationScan-Based BIST Diagnosis Using an Embedded Processor
Scan-Based BIST Diagnosis Using an Embedded Processor Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas
More informationEfficient Algorithm for Test Vector Decompression Using an Embedded Processor
Efficient Algorithm for Test Vector Decompression Using an Embedded Processor Kamran Saleem and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University
More informationReconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center University of Texas at Austin {kjbala,touba}@ece.utexas.edu
More informationTEST DATA COMPRESSION BASED ON GOLOMB CODING AND TWO-VALUE GOLOMB CODING
TEST DATA COMPRESSION BASED ON GOLOMB CODING AND TWO-VALUE GOLOMB CODING Priyanka Kalode 1 and Mrs. Richa Khandelwal 2 1 Department of Electronics Engineering, Ramdeobaba college of Engg and Mgt, Nagpur
More informationTEST cost in the integrated circuit (IC) industry has
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 8, AUGUST 2014 1219 Utilizing ATE Vector Repeat with Linear Decompressor for Test Vector Compression Joon-Sung
More informationNon-Intrusive BIST for Systems-on-a-Chip
Non-Intrusive BIST for Systems-on-a-Chip Silvia CHIUSANO*, PAOLO PRINETTO*, HANS-JOACHIM WUNDERLICH + (*) Politecnico di Torino Dipartimento di Automatica e Informatica Corso duca degli Abruzzi 24 - I-10129,
More informationTest Application Time and Volume Compression through Seed Overlapping
Test Application Time and Volume Compression through Seed verlapping ABSTRACT We propose in this paper an approach based on the Scan Chain Concealment technique to further reduce test time and volume.
More informationA Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods
International Journal of Scientific & Engineering Research, Volume 4, Issue 4, April-2013 664 A Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods Debasmita Hazra Abstract- This
More informationReducing Control Bit Overhead for X-Masking/X-Canceling Hybrid Architecture via Pattern Partitioning
Reducing Control Bit Overhead for X-Masking/X-Canceling Hybrid Architecture via Pattern Partitioning Jin-Hyun Kang Semiconductor Systems Department Sungkyunkwan University Suwon, Korea, 16419 kangjin13@skku.edu
More informationType T1: force false. Type T2: force true. Type T3: complement. Type T4: load
Testability Insertion in Behavioral Descriptions Frank F. Hsu Elizabeth M. Rudnick Janak H. Patel Center for Reliable & High-Performance Computing University of Illinois, Urbana, IL Abstract A new synthesis-for-testability
More informationTESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS
TESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS Navaneetha Velammal M. 1, Nirmal Kumar P. 2 and Getzie Prija A. 1 1 Department of Electronics and Communications
More informationFault Tolerant Parallel Filters Based on ECC Codes
Advances in Computational Sciences and Technology ISSN 0973-6107 Volume 11, Number 7 (2018) pp. 597-605 Research India Publications http://www.ripublication.com Fault Tolerant Parallel Filters Based on
More informationAdaptive Techniques for Improving Delay Fault Diagnosis
Adaptive Techniques for Improving Delay Fault Diagnosis Jayabrata Ghosh-Dastidar and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas,
More informationSYNTHESIS OF MAPPING LOGIC FOR GENERATI TRANSFORMED PSEUDO-RANDOM PATTERNS FOR
SYNTHESIS OF MAPPING LOGIC FOR GENERATI TRANSFORMED PSEUDO-RANDOM PATTERNS FOR Nur A. Touba and Edward J. McCluskey Center for Reliable Computing Departments of Electrical Engineering and Computer Science
More informationAt-Speed Scan Test with Low Switching Activity
21 28th IEEE VLSI Test Symposium At-Speed Scan Test with Low Switching Activity Elham K. Moghaddam Department of ECE, University of Iowa, Iowa City, IA 52242 ekhayatm@engineering.uiowa.edu Janusz Rajski
More informationreasonable to store in a software implementation, it is likely to be a signicant burden in a low-cost hardware implementation. We describe in this pap
Storage-Ecient Finite Field Basis Conversion Burton S. Kaliski Jr. 1 and Yiqun Lisa Yin 2 RSA Laboratories 1 20 Crosby Drive, Bedford, MA 01730. burt@rsa.com 2 2955 Campus Drive, San Mateo, CA 94402. yiqun@rsa.com
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 10 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Content Manufacturing Defects Wafer defects Chip defects Board defects system defects
More informationFunctional Test Generation for Delay Faults in Combinational Circuits
Functional Test Generation for Delay Faults in Combinational Circuits Irith Pomeranz and Sudhakar M. Reddy + Electrical and Computer Engineering Department University of Iowa Iowa City, IA 52242 Abstract
More informationLow Power Testing of VLSI Circuits Using Test Vector Reordering
International Journal of Electrical Energy, Vol. 2, No. 4, December 2014 Low Power Testing of VLSI Circuits Using Test Vector Reordering A. M. Sudha Department of Electrical and Electronics Engineering,
More information[ Circuit Under Test 1
Applying Two-Pattern Tests Using Scan-Mapping Nur A. Touba and Edward J. McCluskey Center for Reliable Computing Stanford University, Stanford, CA. 94305 Abstract This paper proposes a new technique, called
More informationAn efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients
Title An efficient multiplierless approximation of the fast Fourier transm using sum-of-powers-of-two (SOPOT) coefficients Author(s) Chan, SC; Yiu, PM Citation Ieee Signal Processing Letters, 2002, v.
More informationA New Optimal State Assignment Technique for Partial Scan Designs
A New Optimal State Assignment Technique for Partial Scan Designs Sungju Park, Saeyang Yang and Sangwook Cho The state assignment for a finite state machine greatly affects the delay, area, and testabilities
More informationAN EFFICIENT DESIGN OF VLSI ARCHITECTURE FOR FAULT DETECTION USING ORTHOGONAL LATIN SQUARES (OLS) CODES
AN EFFICIENT DESIGN OF VLSI ARCHITECTURE FOR FAULT DETECTION USING ORTHOGONAL LATIN SQUARES (OLS) CODES S. SRINIVAS KUMAR *, R.BASAVARAJU ** * PG Scholar, Electronics and Communication Engineering, CRIT
More information6 DESIGN FOR TESTABILITY I: FROM FULL SCAN TO PARTIAL SCAN
94 Advances in Microelectronics 6 DESIGN FOR TESTABILITY I: FROM FULL SCAN TO PARTIAL SCAN Chia Yee Ooi 6.1 CONTEXT It is important to check whether the manufactured circuit has physical defects or not.
More informationA Reconfigured Twisted Ring Counter Using Tristate Coding For Test Data Compression
A Reconfigured Twisted Ring Counter Using Tristate Coding For Test Data Compression 1 R.Kanagavalli, 2 Dr.O.Saraniya 1 PG Scholar, 2 Assistant Professor Department of Electronics and Communication Engineering,
More informationBuilt-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs Shyue-Kung Lu and Shih-Chang Huang Department of Electronic Engineering Fu Jen Catholic University Hsinchuang, Taipei, Taiwan 242, R.O.C.
More informationAn Integrated ECC and BISR Scheme for Error Correction in Memory
An Integrated ECC and BISR Scheme for Error Correction in Memory Shabana P B 1, Anu C Kunjachan 2, Swetha Krishnan 3 1 PG Student [VLSI], Dept. of ECE, Viswajyothy College Of Engineering & Technology,
More informationInternational Journal of Digital Application & Contemporary research Website: (Volume 1, Issue 7, February 2013)
Programmable FSM based MBIST Architecture Sonal Sharma sonal.sharma30@gmail.com Vishal Moyal vishalmoyal@gmail.com Abstract - SOCs comprise of wide range of memory modules so it is not possible to test
More informationScalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN)
Scalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN) Abstract With increasing design complexity in modern SOC design, many memory
More informationThe performance of xed block size fractal coding schemes for this model were investigated by calculating the distortion for each member of an ensemble
Fractal Coding Performance for First Order Gauss-Markov Models B E Wohlberg and G de Jager Digital Image Processing Laboratory, Electrical Engineering Department, University of Cape Town, Private Bag,
More informationA Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution Irith Pomeranz 1 and Sudhakar M. Reddy 2 School of Electrical & Computer Eng. Electrical &
More informationA Technique for High Ratio LZW Compression
A Technique for High Ratio LZW Compression Michael J. Knieser Francis G. Wolff Chris A. Papachristou Daniel J. Weyer David R. McIntyre Indiana University Purdue University Indianapolis Case Western Reserve
More informationISSN (Online), Volume 1, Special Issue 2(ICITET 15), March 2015 International Journal of Innovative Trends and Emerging Technologies
VLSI IMPLEMENTATION OF HIGH PERFORMANCE DISTRIBUTED ARITHMETIC (DA) BASED ADAPTIVE FILTER WITH FAST CONVERGENCE FACTOR G. PARTHIBAN 1, P.SATHIYA 2 PG Student, VLSI Design, Department of ECE, Surya Group
More informationTest Set Compaction Algorithms for Combinational Circuits
Proceedings of the International Conference on Computer-Aided Design, November 1998 Set Compaction Algorithms for Combinational Circuits Ilker Hamzaoglu and Janak H. Patel Center for Reliable & High-Performance
More informationSoft-Core Embedded Processor-Based Built-In Self- Test of FPGAs: A Case Study
Soft-Core Embedded Processor-Based Built-In Self- Test of FPGAs: A Case Study Bradley F. Dutton, Graduate Student Member, IEEE, and Charles E. Stroud, Fellow, IEEE Dept. of Electrical and Computer Engineering
More informationTest Point Insertion Based on Path Tracing
Test Point Insertion Based on Path Tracing Nur A. Touba and Edward J. McCluskey Center for Reliable Computing Stanford University, Stanford, CA 94305 Abstract This paper presents an innovative method for
More informationSoftware-Based Test Integration in a SoC Design Flow
Software-Based Test Integration in a SoC Design Flow Alexandre M. Amory, Leandro A. Oliveira, Fernando G. Moraes Faculdade de Informática - Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)
More informationVLSI System Testing. Fault Simulation
ECE 538 VLSI System Testing Krish Chakrabarty Fault Simulation ECE 538 Krish Chakrabarty Fault Simulation Problem and motivation Fault simulation algorithms Serial Parallel Deductive Concurrent Random
More informationOn Broad-Side Delay Test
Abstract On Broad-Side Delay Test A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational
More informationSoftware-Based Self-Testing Methodology for Processor Cores
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 3, MARCH 2001 369 Software-Based Self-Testing Methodology for Processor Cores Li Chen, Student Member, IEEE,
More informationModified Welch Power Spectral Density Computation with Fast Fourier Transform
Modified Welch Power Spectral Density Computation with Fast Fourier Transform Sreelekha S 1, Sabi S 2 1 Department of Electronics and Communication, Sree Budha College of Engineering, Kerala, India 2 Professor,
More informationAn Efficient Method for Multiple Fault Diagnosis
An Efficient Method for Multiple Fault Diagnosis Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL Abstract: In this paper, failing circuits are analyzed and
More informationHDL IMPLEMENTATION OF SRAM BASED ERROR CORRECTION AND DETECTION USING ORTHOGONAL LATIN SQUARE CODES
HDL IMPLEMENTATION OF SRAM BASED ERROR CORRECTION AND DETECTION USING ORTHOGONAL LATIN SQUARE CODES (1) Nallaparaju Sneha, PG Scholar in VLSI Design, (2) Dr. K. Babulu, Professor, ECE Department, (1)(2)
More informationPower Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder
Power Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder Syeda Mohtashima Siddiqui M.Tech (VLSI & Embedded Systems) Department of ECE G Pulla Reddy Engineering College (Autonomous)
More informationOnline Testing of Word-oriented RAMs by an Accumulator-based Compaction Scheme in Symmetric Transparent Built-In Self Test (BIST)
Online Testing of Word-oriented RAMs by an Accumulator-based Compaction Scheme in Symmetric Transparent Built-In Self Test (BIST) Sharvani Yedulapuram #1, Chakradhar Adupa *2 # Electronics and Communication
More informationA Hybrid BIST Architecture and its Optimization for SoC Testing
A Hybrid BIST Architecture and its Optimization for SoC Testing Gert Jervan, Zebo Peng Linköping University, Sweden {gerje, zebpe}@ida.liu.se Raimund Ubar, Helena Kruus Tallinn Technical University, Estonia
More informationOn Test Generation by Input Cube Avoidance
On Test Generation by Input Cube Avoidance Irith Pomeranz 1 and Sudhakar M. Reddy 2 School of Electrical & Computer Eng. Electrical & Computer Eng. Dept. Purdue University University of Iowa W. Lafayette,
More informationOn Efficient Error Diagnosis of Digital Circuits
On Efficient Error Diagnosis of Digital Circuits Nandini Sridhar Michael S. Hsiao Intel Corporation Bradley Dept. of ECE, Virginia Tech Dupont, WA 98327Blacksburg, VA 246 nandini.sridhar@intel.com mhsiao@vt.edu
More informationMotion Estimation. Original. enhancement layers. Motion Compensation. Baselayer. Scan-Specific Entropy Coding. Prediction Error.
ON VIDEO SNR SCALABILITY Lisimachos P. Kondi, Faisal Ishtiaq and Aggelos K. Katsaggelos Northwestern University Dept. of Electrical and Computer Engineering 2145 Sheridan Road Evanston, IL 60208 E-Mail:
More informationEECS 579: Built-in Self-Test 3. Regular Circuits
EECS 579: Built-in Self-Test 3 Outline Implementing BIST by regularization Adder ALU RAM Commercial BIST approaches LOCSD STUMPS CSTP Case Study Bosch AE11 microcontroller John P. Hayes University of Michigan
More informationEvaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks Charles Stroud, Ping Chen, Srinivasa Konala, Dept. of Electrical Engineering University of Kentucky and Miron Abramovici
More informationA Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis Chunsheng Liu and Krishnendu Chakrabarty Department of Electrical & Computer
More informationInternational Journal of Foundations of Computer Science c World Scientic Publishing Company DFT TECHNIQUES FOR SIZE ESTIMATION OF DATABASE JOIN OPERA
International Journal of Foundations of Computer Science c World Scientic Publishing Company DFT TECHNIQUES FOR SIZE ESTIMATION OF DATABASE JOIN OPERATIONS KAM_IL SARAC, OMER E GEC_IO GLU, AMR EL ABBADI
More informationDevelopment of Generic Search Method Based on Transformation Invariance
Development of Generic Search Method Based on Transformation Invariance Fuminori Adachi, Takashi Washio, Hiroshi Motoda and *Hidemitsu Hanafusa I.S.I.R., Osaka University, {adachi, washio, motoda}@ar.sanken.osaka-u.ac.jp
More informationDriving Toward Higher I DDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG
Driving Toward Higher I DDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG Hisashi Kondo Kwang-Ting Cheng y Kawasaki Steel Corp., LSI Division Electrical and Computer Engineering
More information7 DESIGN FOR TESTABILITY II: FROM HIGH LEVEL PERSPECTIVE
122 Advances in Microelectronics 7 DESIGN FOR TESTABILITY II: FROM HIGH LEVEL PERSPETIVE hia Yee Ooi Norlina Paraman 7.1 ONTEXT The advantage of a top-down design flow, specifying design a high abstraction
More informationUpper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring Vishwani D. Agrawal Auburn Univerity, Dept. of ECE Soumitra Bose and Vijay Gangaram Intel Corporation, Design Technology Auburn,
More informationRowena Cole and Luigi Barone. Department of Computer Science, The University of Western Australia, Western Australia, 6907
The Game of Clustering Rowena Cole and Luigi Barone Department of Computer Science, The University of Western Australia, Western Australia, 697 frowena, luigig@cs.uwa.edu.au Abstract Clustering is a technique
More informationTestability Analysis and Improvement from VHDL Behavioral Specifications
Testability Analysis and Improvement from VHDL Behavioral Specifications Xinli Gu, Krzysztof Kuchcinski, Zebo Peng Dept. of Computer and Information Science Linköping University S-581 83 Linköping, Sweden
More information1 Introduction Data format converters (DFCs) are used to permute the data from one format to another in signal processing and image processing applica
A New Register Allocation Scheme for Low Power Data Format Converters Kala Srivatsan, Chaitali Chakrabarti Lori E. Lucke Department of Electrical Engineering Minnetronix, Inc. Arizona State University
More informationLow-Power FIR Digital Filters Using Residue Arithmetic
Low-Power FIR Digital Filters Using Residue Arithmetic William L. Freking and Keshab K. Parhi Department of Electrical and Computer Engineering University of Minnesota 200 Union St. S.E. Minneapolis, MN
More informationSSoCC'01 4/3/01. Specific BIST Architectures. Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University
Specific BIST Architectures Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University General Concepts Test-per-scan architectures Multiple scan chains Test-per-clock architectures BIST conclusions
More informationGate Level Fault Diagnosis in Scan-Based BIST
Gate Level Fault Diagnosis in Scan-Based BIST Ismet Bayraktaroglu Computer Science & Engineering Department University of California, San Diego La Jolla, CA 92093 ibayrakt@csucsdedu Alex Orailoglu Computer
More informationAn enhanced barrel shifter based BIST scheme for word organized RAMs (EBBSR).
An enhanced barrel shifter based BIST scheme for word organized RAMs (EBBSR). M.leela vinoth krishnan Depatment of Electronics and Communication, CEG-Anna university, Chennai, INDIA. Krishnan7_ece@yahoo.co.in.
More informationPacked Integer Wavelet Transform Constructed by Lifting Scheme
1496 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 10, NO. 8, DECEMBER 2000 Packed Integer Wavelet Transform Constructed by Lting Scheme Chengjiang Lin, Bo Zhang, and Yuan F. Zheng
More informationREDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits *
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits * Chen Wang, Irith Pomeranz and Sudhakar M. Reddy Electrical and Computer Engineering Department
More informationPROOFS Fault Simulation Algorithm
PROOFS Fault Simulation Algorithm Pratap S.Prasad Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL prasaps@auburn.edu Term Paper for ELEC 7250 (Spring 2005) Abstract This paper
More informationFPGA Implementation of ALU Based Address Generation for Memory
International Journal of Emerging Engineering Research and Technology Volume 2, Issue 8, November 2014, PP 76-83 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) FPGA Implementation of ALU Based Address
More informationPPS : A Pipeline Path-based Scheduler. 46, Avenue Felix Viallet, Grenoble Cedex, France.
: A Pipeline Path-based Scheduler Maher Rahmouni Ahmed A. Jerraya Laboratoire TIMA/lNPG,, Avenue Felix Viallet, 80 Grenoble Cedex, France Email:rahmouni@verdon.imag.fr Abstract This paper presents a scheduling
More informationHigh-level Variable Selection for Partial-Scan Implementation
High-level Variable Selection for Partial-Scan Implementation FrankF.Hsu JanakH.Patel Center for Reliable & High-Performance Computing University of Illinois, Urbana, IL Abstract In this paper, we propose
More informationEMBEDDED DETERMINISTIC TEST FOR LOW COST MANUFACTURING TEST
EMBEDDED DETERMINISTIC TEST FOR LOW COST MANUFACTURING TEST Janusz Rajski, Jerzy Tyszer *, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski
More informationA Proposed RAISIN for BISR for RAM s with 2D Redundancy
A Proposed RAISIN for BISR for RAM s with 2D Redundancy Vadlamani Sai Shivoni MTech Student Department of ECE Malla Reddy College of Engineering and Technology Anitha Patibandla, MTech (PhD) Associate
More informationError Detecting and Correcting Code Using Orthogonal Latin Square Using Verilog HDL
Error Detecting and Correcting Code Using Orthogonal Latin Square Using Verilog HDL Ch.Srujana M.Tech [EDT] srujanaxc@gmail.com SR Engineering College, Warangal. M.Sampath Reddy Assoc. Professor, Department
More informationALGORITHM FOR POWER MINIMIZATION IN SCAN SEQUENTIAL CIRCUITS
ALGORITHM FOR POWER MINIMIZATION IN SCAN SEQUENTIAL CIRCUITS 1 Harpreet Singh, 2 Dr. Sukhwinder Singh 1 M.E. (VLSI DESIGN), PEC University of Technology, Chandigarh. 2 Professor, PEC University of Technology,
More informationReducing Power Dissipation During Test Using Scan Chain Disable
Reducing Power Dissipation During Test Using Scan Chain Disable Ranganathan Sankaralingam, Bahram Pouya2, and Nur A. Touba Computer Engineering Research Center Dept. of Electrical and Computer Engineering
More informationAN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS
International Journal of Engineering Inventions ISSN: 2278-7461, www.ijeijournal.com Volume 1, Issue 8 (October2012) PP: 76-80 AN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS B.Prathap Reddy
More informationAt-Speed On-Chip Diagnosis of Board-Level Interconnect Faults
At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults Artur Jutman Tallinn University of Technology artur@pld.ttu.ee Abstract This article describes a novel approach to fault diagnosis suitable
More informationEfficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering
Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering Aiman El-Maleh, Saqib Khurshid King Fahd University of Petroleum and Minerals Dhahran, Saudi Arabia
More informationDesign and Implementation of Signed, Rounded and Truncated Multipliers using Modified Booth Algorithm for Dsp Systems.
Design and Implementation of Signed, Rounded and Truncated Multipliers using Modified Booth Algorithm for Dsp Systems. K. Ram Prakash 1, A.V.Sanju 2 1 Professor, 2 PG scholar, Department of Electronics
More informationOverview ECE 753: FAULT-TOLERANT COMPUTING 1/23/2014. Recap. Introduction. Introduction (contd.) Introduction (contd.)
ECE 753: FAULT-TOLERANT COMPUTING Kewal K.Saluja Department of Electrical and Computer Engineering Test Generation and Fault Simulation Lectures Set 3 Overview Introduction Basics of testing Complexity
More informationATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm
ATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm P.K.Chakrabarty 1, S.N.Patnaik 2 1Professor, Department of CSE., IT,BHU, India 2Asst.Professor, ECE Department, DRIEMS, Cuttack,
More informationThe 17th International Conference on Safety, Reliability and Security (SAFECOMP 98) LNCS, Heidelberg, 1998
The 17th International Conference on Safety, Reliability and Security (SAFECOMP 98) LNCS, Heidelberg, 1998 Verifying Integrity of Decision Diagrams Rolf Drechsler Institute of Computer Science Albert-Ludwigs-University
More information8ns. 8ns. 16ns. 10ns COUT S3 COUT S3 A3 B3 A2 B2 A1 B1 B0 2 B0 CIN CIN COUT S3 A3 B3 A2 B2 A1 B1 A0 B0 CIN S0 S1 S2 S3 COUT CIN 2 A0 B0 A2 _ A1 B1
Delay Abstraction in Combinational Logic Circuits Noriya Kobayashi Sharad Malik C&C Research Laboratories Department of Electrical Engineering NEC Corp. Princeton University Miyamae-ku, Kawasaki Japan
More informationDocument Image Restoration Using Binary Morphological Filters. Jisheng Liang, Robert M. Haralick. Seattle, Washington Ihsin T.
Document Image Restoration Using Binary Morphological Filters Jisheng Liang, Robert M. Haralick University of Washington, Department of Electrical Engineering Seattle, Washington 98195 Ihsin T. Phillips
More informationFaults. Abstract. 1. Introduction. * Nur A. Touba is now with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX
s Abstract While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo-random testing of bridging faults and describes a means for achieving high fault coverage
More information