Electronic Design Automation: Synthesis, Verification, and Test

Transcription

1 Electronic Design Automation: Synthesis, Verification, and Test Edited by Laung-Terng Wang Yao-Wen Chang Kwang-Ting (Tim) Cheng AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO К SAN FRANCISCO SINGAPORE SYDNEY TOKYO MORGAN ELSEVIER Morgan Kaufmann Publishers is an imprint of Elsevier KAUFMANN

2 Contents Preface In the Classroom Acknowledgments Contributors About the Editors xxi xxv xxvii xxix xxxiii CHAPTER 1 Introduction 1 Charles E. Stroud, Lang-Terng (L.-T.) Wang, and Yao-Wen Chang 1.1 Overview of electronic design automation Historical perspective VLSI design flow and typical EDA flow Typical EDA implementation examples Problems and challenges Logic design automation Modeling Design verification Logic synthesis Test automation Fault models Design for testability Fault simulation and test generation Manufacturing test Physical design automation Floorplanning Placement Routing Synthesis of clock and power/ground networks Concluding remarks Exercises 33 Acknowledgments 35 References 35 V

3 CHAPTER 2 Fundamentals of CMOS design 39 Xinghao Chen and Nur A. Touba 2.1 Introduction Integrated circuit technology MOS transistor Transistor equivalency Wire and interconnect Noise margin CMOS logic CMOS inverter and analysis Design of CMOS logic gates and circuit blocks Design of latches and flip-flops Optimization techniques for high performance Integrated circuit design techniques Transmission-gate/pass-transistor logic Differential CMOS logic Dynamic pre-charge logic Domino logic No-race logic Single-phase logic CMOS physical design Layout design rules Stick diagram Layout design Low-power circuit design techniques Clock-gating Power-gating Substrate biasing Dynamic voltage and frequency scaling Low-power cache memory design Concluding remarks Exercises 92 Acknowledgments 95 References 95 CHAPTER 3 Design for testability 97 Laung-Terng (L.-T.) Wang 3.1 Introduction Testability analysis 100

4 Contents \ vii SCOAP testability analysis Combinational controllability and observability calculation Sequential controllability and observability calculation Probability-based testability analysis Simulation-based testability analysis Scan design Scan architectures Muxed-D scan design Clocked-scan design Ill LSSD scan design At-speed testing Logic built-in self-test Test pattern generation Exhaustive testing Pseudo-random testing Pseudo-exhaustive testing Output response analysis Ones count testing Transition count testing Signature analysis Logic BIST architectures Self-testing with MISR and parallel SRSG (STUMPS) Built-in logic block observer (BILBO) Concurrent built-in logic block observer (CBILBO) Industry practices Test Compression Circuits for test stimulus compression Linear-decompression-based schemes Broadcast-scan-based schemes Circuits for test response compaction Combinational compaction Sequential compaction Industry practices Concluding remarks Exercises 162 Acknowledgments 165 References 165

5 viii Contents CHAPTER 4 Fundamentals of algorithms 173 Chung-Yang (Ric) Huang, Cbao-Yue Lai, and Kwang-Ting (Tim) Cheng 4.1 Introduction Computational complexity Asymptotic notations O-notation O-notation and -notation Complexity classes Decision problems versus optimization problems The complexity classes P versus NP The complexity class NP-complete The complexity class NP-hard Graph algorithms Terminology Data structures for representations of graphs Breadth-first search and depth-first search Breadth-first search Depth-first search Topological sort Strongly connected component Shortest and longest path algorithms Initialization and relaxation Shortest path algorithms on directed acyclic graphs Dijkstra's algorithm The Bellman-Ford algorithm The longest-path problem Minimum spanning tree Maximum flow and minimum cut Flow networks and the maximum-flow problem Augmenting paths and residual networks The Ford-Fulkerson method and the Edmonds-Karp algorithm Cuts and the max-flow min-cut theorem Multiple sources and sinks and maximum bipartite matching 207

6 Contents I ix 4.4 Heuristic algorithms Greedy algorithm Greedy-choice property Optimal substructure Dynamic programming Overlapping subproblems Optimal substructure Memoization Branch-and-bound 215 4ЛЛ Simulated annealing Genetic algorithms Mathematical programming Categories of mathematical programming problems Linear programming (LP) problem Integer linear programming (ILP) problem Linear programming relaxation and branch-and-bound procedure Cutting plane algorithm Convex optimization problem Interior-point method Concluding remarks Exercises 230 Acknowledgments 232 References 232 CHAPTER 5 Electronic system-level design and high-level synthesis 235 Jianwen Zhu and Nikil Dutt 5.1 Introduction ESL design methodology Function-based ESL methodology Architecture-based ESL methodology Function architecture codesign methodology High-level synthesis within an ESL design methodology Fundamentals of High-level synthesis TinyC as an example for behavioral descriptions Intermediate representation in TinylR RTL representation in TinyRTL 253

7 x I Contents Structured hardware description in FSMD Quality metrics High-level synthesis algorithm overview Scheduling Dependency test Unconstrained scheduling Resource-constrained scheduling Register binding Liveness analysis Register binding by coloring Functional unit binding Concluding remarks Exercises 293 Acknowledgments 294 References 294 CHAPTER 6 Logic synthesis in a nutshell 299 Jie-Hong (Roland) Jiang and Srinivas Devadas 6.1 Introduction Data Structures for Boolean representation and reasoning Quantifier-free and quantified Boolean formulas Boolean function manipulation Boolean function representation Truth table SOP POS BDD AIG Boolean network Boolean representation conversion CNF vs. DNF Boolean formula vs. circuit BDD vs. Boolean network Isomorphism between sets and characteristic functions Boolean reasoning engines Combinational logic minimization Two-level logic minimization 332

8 Contents I xi PLA implementation vs. SOP minimization Terminology З.2 SOP minimization The Quine-McCluskey method Other methods Multilevel logic minimization З.З.1 Logic transformations Division and common divisors Algebraic division Common divisors Boolean division Combinational complete flexibility Advanced subjects Technology mapping Technology libraries Graph covering Choice of atomic pattern set Tree covering approximation Optimal tree covering Improvement by inverter-pair insertion Extension to non-tree patterns Advanced subjects Timing analysis Topological timing analysis Functional timing analysis Delay models and modes of operation True floating mode delay Advanced subjects Timing optimization Technology-independent timing optimization Timing-driven technology mapping Delay optimization using tree covering Area minimization under delay constraints Advanced subjects Concluding remarks Exercises 393 Acknowledgments 400 References 400

9 CHAPTER 7 Test synthesis 405 Laung-Temg (L.-T.) Wang, Xiaoqing Wen, and Shianling Wu 7.1 Introduction Scan design Scan design rules Tristate buses Bidirectional I/O ports Gated clocks Derived clocks Combinational feedback loops Asynchronous set/reset signals Scan design flow Scan design rule checking and repair Scan synthesis Scan extraction Scan verification Logic built-in self-test (BIST) design BIST design rules Unknown source blocking Re-timing BIST design example BIST rule checking and violation repair Logic BIST system design RTL BIST synthesis Design verification and fault coverage enhancement RTL Design for testability RTL scan design rule checking and repair RTL scan synthesis RTL scan extraction and scan verification Concluding remarks Exercises 443 Acknowledgments 446 References 446

10 Contents I xiii CHAPTER 8 Logic and circuit simulation 449 Jiun-Lang Huang, Cheng-Kok Koh, and Stephen F. Cauley 8.1 Introduction Logic Simulation Hardware-accelerated logic simulation Circuit Simulation Logic simulation models Logic Symbols and Operations "1" and "0" The unknown value и The high-impedance state Z Basic logic operations Timing models Transport delay Inertial delay Functional element delay model Wire delay Logic simulation techniques Compiled-code simulation Preprocessing Code generation Applications Event-driven simulation Zero-delay event-driven simulation Nominal-delay event-driven simulation Hardware-accelerated logic simulation Types of hardware acceleration Reconfigurable computing units Interconnection architectures Direct interconnection Indirect interconnect Time-multiplexed interconnect Timing issues Circuit simulation models Ideal voltage and current sources Resistors, capacitors, and inductors Kirchhoff's voltage and current laws Modified nodal analysis 477

11 8.6 Numerical methods for transient analysis Approximation methods and numerical integration Initial value problems Simulation of VLSI interconnects Wire resistance Wire capacitance Wire inductance Lumped and distributed models Simulation procedure for interconnects Simulation of nonlinear devices The diode The field-effect transistor Simulation procedure for nonlinear devices Concluding remarks Exercises 506 Acknowledgments 509 References 510 CHAPTER 9 Functional verification 513 Hung-Pin (Charles) Wen, Li-C. Wang, and Kwang-Ting (Tim) Cheng 9.1 Introduction Verification hierarchy Designer4evel verification Unit4evel verification Core-level verification Chip-level verification System-/board-level verification Measuring verification quality Random testing Coverage-driven verification Structural coverage metrics Line coverage (a.k.a. statement coverage) Toggle coverage Branch/path coverage Expression coverage Trigger coverage (a.k.a. event coverage) Finite state machine (FSM) coverage More on structural coverage Functional coverage metrics 531

12 Contents l xv 9.4 Simulation-based approach Testbench and simulation environment development Methods of observation points Assertion-based verification Assertion coverage and classification Use of assertions Writing assertions Formal approaches Equivalence checking Checking based on functional equivalence Checking based on structural search Model checking (property checking) Model checking with temporal logic Theorem proving Advanced research 56l 9.7 Concluding remarks Exercises 564 Acknowledgments 570 References 570 CHAPTER 10 Floorplanning 575 Tung-Chieh Chen and Yao-Wen Chang 10.1 Introduction Floorplanning basics Problem statement Floorplanning model Slicing floorplans Non-slicing floorplans Floorplanning cost Simulated annealing approach Simulated annealing basics Normalized Polish expression for slicing floorplans Solution space Neighborhood structure Cost function Annealing schedule B*-tree for compacted floorplans From a floorplan to its B*-tree 594

13 xvi I Contents From a B*-tree to its floorplan Solution space Neighborhood structure Cost function Annealing schedule Sequence pair for general floorplans From a floorplan to its sequence pair From a sequence pair to its floorplan Solution space Neighborhood structure Cost function Annealing schedule Floorplan representation comparison Analytical approach Modern floorplanning considerations Soft modules Fixed-outline constraint Floorplanning for large-scale circuits Other considerations and topics Concluding remarks Exercises 625 Acknowledgments 631 References 631 CHAPTER 11 Placement 635 Chris Chu 11.1 Introduction Problem formulations Placement for different design styles Standard-cell placement Gate array/fpga placement Macro block placement Mixed-size placement Placement objectives Total wirelength Routability Performance Power Heat distribution A common placement formulation 641

14 Contents I xvii 11.3 Global placement: partitioning-based approach Basics for partitioning Problem formulation The Fiduccia-Mattheyses algorithm A multilevel scheme Placement by partitioning The basic idea Terminal propagation technique Practical implementations The Capo algorithm The Fengshui algorithm Global placement: simulated annealing approach The placement algorithm in TimberWolf Stage Stage Annealing schedule The Dragon placement algorithm Global placement: analytical approach An exact formulation Quadratic techniques Quadratic wirelength Force interpretation of quadratic wirelength Net models for multi-pin nets Linearization methods Handling nonoverlapping constraints Nonquadratic techniques Log-sum-exponential wirelength function Density constraint smoothing by bell-shaped function Density constraint smoothing by inverse laplace transformation Algorithms for nonlinear programs Extension to multilevel First choice Best choice Legalization Detailed placement The Domino algorithm The FastDP algorithm 677

15 11.8 Concluding Remarks Exercises 680 Acknowledgments 682 References 682 CHAPTER 12 Global and detailed routing 687 Huang-Yu Chen and Yao-Wen Chang 12.1 Introduction Problem definition Routing model Routing constraints General-purpose routing Maze routing Coding scheme Search algorithm Search space Line-search routing A*-search routing Global routing Sequential global routing Concurrent global routing Steiner trees Detailed Routing Channel routing Full-chip routing Modern routing considerations Routing for signal integrity Crosstalk modeling Crosstalk-aware routing Routing for manufacturability OPC-aware routing CMP-aware routing Routing for reliability Antenna-avoidance routing Redundant-via aware routing Concluding remarks Exercises 740 Acknowledgments 745 References 745

16 Contents P xix CHAPTER 13 Synthesis of clock and power/ground networks 751 Cheng-Kok Koh, Jitesh Jain, and Stephen F. Cauley 13.1 Introduction Design considerations Timing constraints Skew and Jitter IR drop and Ldi/dt noise Power dissipation 76l Electromigration Clock Network design Typical clock topologies З.2 Clock network modeling and analysis Clock tree synthesis Clock skew scheduling ЗЗ.2 Clock tree routing Zero-skew routing Bounded-skew routing Useful-skew routing Clock tree optimization Buffer insertion in clock routing Clock gating Wire sizing for clock nets Cross-link insertion Power/ground network design Typical power/ground topologies Power/ground network analysis Power/ground network synthesis Topology optimization Power pad assignment Wire width optimization Decoupling capacitance Concluding remarks Exercises 843 Acknowledgments 846 References 846

17 CHAPTER 14 Fault Simulation and Test Generation 851 James C.-M. Li and Michael S. Hsiao 14.1 Introduction Fault Collapsing Equivalence fault collapsing Dominance fault collapsing Fault Simulation Serial fault simulation Parallel fault simulation Parallel fault simulation Parallel pattern fault simulation Concurrent fault simulation Differential fault simulation Comparison of fault simulation techniques Test Generation Random test generation Exhaustive testing Theoretical Background: Boolean difference Untestable Faults Designing a stuck-at ATPG for combinational circuits A naive ATPG algorithm A basic ATPG algorithm D algorithm PODEM FAN Advanced Test Generation Sequential ATPG: Time frame expansion Delay fault ATPG Bridging fault ATPG Concluding Remarks Exercises 910 Acknowledgments 913 References 913 Index 919