Chapter 9. Design for Testability

Transcription

1 Chapter 9 Design for Testability

2 Testability CUT = Circuit Under Test A design property that allows: cost-effective development of tests to be applied to the CUT determining the status of the CUT (normal or defective) and the location of the defect Testability components: controllability observability predictability page 2 of 42 Copyright Miron Abramovici, 1997 November 1997

3 Rationale for DFT reduce lifetime cost of ownership of a product increase quality reduce time-to-market page 3 of 42 Copyright Miron Abramovici, 1997 November 1997

4 Why Isn t DFT Universally Used? Short-sighted view of management (schedule and costs) Life-cycle costs ignored Overhead and performance degradation myths Costs are easier to quantify than benefits Lack of knowledge by design engineers Testing is someone else s problem Poor organizational interfaces: design test Incompatibility: design CAD tools test tools Test requirements and test strategy: lacking or poorly defined page 4 of 42 Copyright Miron Abramovici, 1997 November 1997

5 Testability Part of the design requirements Logic introduced to satisfy requirements is not overhead DFT helps both design and test page 5 of 42 Copyright Miron Abramovici, 1997 November 1997

6 DFT Techniques: Evaluation Criteria Hardware costs area power dissipation routing pins packaging Fault/defect coverage SSFs shorts, opens delay faults Test application time Performance degradation CAD tools support page 6 of 42 Copyright Miron Abramovici, 1997 November 1997

7 DFT Techniques: Evaluation Criteria... Life-cycle usefulness development (design costs, time-to-market) manufacture (IC test, board test, system test) debug (lab test) field support and maintenance Computational costs (test development time) ATE costs (Sematech prediction: ~$20M by year 2010) page 7 of 42 Copyright Miron Abramovici, 1997 November 1997

8 Test Synthesis Automated implementation of DFT techniques When coupled with logic (design) synthesis, several objectives are concurrently optimized: area performance power testability HDL model Logic Synthesis Test Synthesis Gate-level model Different DFT techniques may be applied to different subcircuits (embedded RAM, random logic, embedded µp, IC on board,...) page 8 of 42 Copyright Miron Abramovici, 1997 November 1997

9 Ad-Hoc DFT (9.2) Provide test points and control points Provide easy initialization Partition the logic Provide bus access Bypass clock generation, one-shots,... for testing Avoid/bypass asynchronous logic Break feedback loops Disable intentional redundancies for testing Provide access to embedded blocks... page 9 of 42 Copyright Miron Abramovici, 1997 November 1997

10 System-Level Test Using System Bus nonbus I/O MP or ATE µp UNIT 1 UNIT N system bus ROM RAM I/O controller I/O BUS MP = Maintenance Processor page 10 of 42 Copyright Miron Abramovici, 1997 November 1997

11 A Look at Several Ad-Hoc DFT Techniques Change circuit behavior in Test Mode Partitioning using multiplexers pipeline structures large blocks Observing several test points with only one spare pin Providing pull-up (or pull-down) loads for busses Loadable flip-flops page 11 of 42 Copyright Miron Abramovici, 1997 November 1997

12 Test Mode Add one (or more) pin(s) to define the mode of operation of the circuit Use test mode(s) to modify structures detrimental to testing Clock generator 0 1 D C FF Q D C FF R Q Test_clock 0 N/T feedback loop Test_reset 0 1 N/T 1 N/T page 12 of 42 Copyright Miron Abramovici, 1997 November 1997

13 Test Mode: Cost-Benefit Analysis - Pins: 1 - Area: negligible - Delays: negligible (unless feedback loop has critical timing) - Routing: negligible (several test signals) - Bypassed areas must be tested in normal mode + Essential to allow ATPG to process the circuit + Higher fault coverage + Also needed with structured DFT techniques page 13 of 42 Copyright Miron Abramovici, 1997 November 1997

14 Partitioning a Pipeline Structure via Multiplexers Before: After: A B C S 1 S 2 Mode 0 0 Normal 1 1 test B 0 1 test A 1 0 test C M A U B C X M U X S 1 S 2 page 14 of 42 Copyright Miron Abramovici, 1997 November 1997

15 Testing the Partitioned Circuit Testing B: M U X A B C M U X Testing A: M U X A B C M U X Testing C: M U X A B C M U X page 15 of 42 Copyright Miron Abramovici, 1997 November 1997

16 Pipeline MUX Partitioning: Cost-Benefit Analysis - Pins: 2 - Area and delays: one MUX for every internal signal - Routing: extra fanout for all PIs and for outputs of B + C: more controllable (PIs A B PIs A) + A: more observable (B C POs B POs) + B: totally controllable and observable (PIs A B C POs PIs B POs + Better fault coverage + Faster ATPG + Faster fault simulation page 16 of 42 Copyright Miron Abramovici, 1997 November 1997

17 Cost-Benefit Analysis... + Better fault location: first test B by itself then test A observing it through the already tested B then test C controlling it through the already tested B page 17 of 42 Copyright Miron Abramovici, 1997 November 1997

18 Partitioning a Large Block via Multiplexers B T 1 T 2 B A m / D /p / s C / n A D A 1 S M U 0 X C C 1 / q E C 2 C 1 S M U X 1 C 0 E C 2 F G Problems: controlling D, E observing D, E F 0 1 MUX S F A A G 1 0 S MUX G C C page 18 of 42 Copyright Miron Abramovici, 1997 November 1997

19 Testing the Partitioned Circuit T 1 T 2 B T 1 T B A D A 1 S M U 0 X C A D A 1 S M U 0 X C C 1 S M U X 1 C 0 E C 2 C 1 S M U X 1 C 0 E C 2 F 0 1 MUX S G 1 0 S MUX F 0 1 MUX S G 1 0 S MUX F G F G Testing C 1 Testing C 2 page 19 of 42 Copyright Miron Abramovici, 1997 November 1997

20 Partitioning with MUXes: Cost-Benefit Analysis - Pins: 2 - Area and delay: MUXes for all POs and subsets of PIs - Routing: additional fanout for subsets of PIs (A and C ) - Some connections C 1 C 2 not tested in test mode + Better controllability and observability for D and E + Reduced test application time + Reduced fault simulation time + Reduced test generation time + Better fault location page 20 of 42 Copyright Miron Abramovici, 1997 November 1997

21 Test Application Time Assumptions: exhaustive testing m=n p=q p m # patterns without partitioning: 2 2m+s # patterns with partitioning: 2 2 m+s+p Reduction= 2 s-p-1 Example: m=n=s=8; p=q= A m / C 1 F B D /p / s / q E C 2 G C / n page 21 of 42 Copyright Miron Abramovici, 1997 November 1997

22 Fault Simulation and ATPG Time Assumptions: G = # of gates in the original circuit fault simulation time ~O(G 2 ) C 1 and C 2 have ~G/2 gates ATPG time ~O(G 3 ) For the partitioned circuit fault simulation time: 2 O(G/2) 2 = 0.5 O(G 2 ) ATPG time: 2 O(G/2) 3 = 0.25 O(G 3 ) page 22 of 42 Copyright Miron Abramovici, 1997 November 1997

23 Observing Several Test Points with One Pin Problem: We d like to observe N internal signals, but we have only one spare pin. Solution: Combine the internal signals via an XOR (parity) tree. TP 1 TP 2 TP 3... TPN Potential trouble: A fault that affects an even number of test points concurrently may not be detected (error masking). Potential solution: Pick independent test points. Add: TP 1 TP 2 TP 3 TP N pin page 23 of 42 Copyright Miron Abramovici, 1997 November 1997

24 XORing Test Points: Cost-Benefit Analysis - Pins: 1 - Area: XOR tree - Routing: additional fanout for N signals + Minimal impact on performance + Direct observability for N signals + Better fault coverage + More efficient fault simulation + More efficient ATPG + Better diagnostics page 24 of 42 Copyright Miron Abramovici, 1997 November 1997

25 Providing Pull-Up Loads for Busses Without the pull-up: No driver is enabled the bus is floating floating = unknown value Bus=u/0 fault on Enable (or in the logic feeding it) is undetectable or potentially detected With the pull-up: Z 1 Test for Enable s-a-1: Set all Enable lines to 0 Set all Data lines to 0 Bus=1/0 0 0 Enable 0 s-a-1 0 Data 0 0 Pull-up Bus (u/0) 1/0 + page 25 of 42 Copyright Miron Abramovici, 1997 November 1997

26 Providing Pull-Ups: Cost-Benefit Analysis - Cost: pull-up load + Several untestable faults become testable + Better fault coverage + More efficient fault simulation + More efficient ATPG + Better diagnostics + Also required with structured DFT page 26 of 42 Copyright Miron Abramovici, 1997 November 1997

27 Main Problem: Sequential Circuits Buried registers are difficult to control and observe Many DFT techniques try to improve the controllability and observability of flip-flops (FFs) PI C R PO Q D Clock page 27 of 42 Copyright Miron Abramovici, 1997 November 1997

28 Loadable Flip-Flops Load=0: normal operation Load=1: A subset of FFs (R L ) are loaded from PI values PI C PO Solves only the controllability problem only for FFs in R L R Q D Q R L D M U X Clock Load page 28 of 42 Copyright Miron Abramovici, 1997 November 1997

29 Loadable Flip-Flops: Cost-Benefit Analysis - Pins: 1 - Area: MUX for every input to R L - Delays: MUX (negligible if FFs in R L are not on critical timing paths) - Routing: PIs MUX + Controllability for R L + Better fault coverage (marginal) + Shorter test sequences (marginal) + Allows at-speed testing page 29 of 42 Copyright Miron Abramovici, 1997 November 1997

30 Ad-Hoc DFT: General Remarks + Relatively low overhead and performance impact + Modest improvements in testability + Do not constrain the design + Some technique may be also required with structured DFT - Partial solutions - ATPG feasible only for small/medium circuits - Fault simulation for functional tests: not always feasible - Long test development time - Low fault coverage - No CAD support (or very little) page 30 of 42 Copyright Miron Abramovici, 1997 November 1997

31 Full-Scan Design Transform all flip-flops into scan flip-flops and connect them in a shift register (scan chain) Scan flip-flop System Data M Scan Data U D Q X C Scan_select Clock (Many other styles of scan flip-flop exist.) M U X Scan_select D C Clock Q M U X Scan_select C Clock Scan chain D Q All FFs controllable and observable (via serial access) Note: Scan_select N/T page 31 of 42 Copyright Miron Abramovici, 1997 November 1997

32 Testing a Full-Scan Circuit 1. Flush-test scan chain 2. Scan-in vector (Scan_select = 1) PI PO 3. Apply vector at PIs C 4. Observe results at POs 5. Apply Clock to capture results in register (Scan_select = 0) 6. Scan-out results and scan-in new vector (Scan_select = 1) 7. Go to 3 R S Q D S OUT (Double-sampling technique: observe POs both before and after clocking.) Scan_select S IN Clock page 32 of 42 Copyright Miron Abramovici, 1997 November 1997

33 Full-Scan Design: Cost-Benefit Analysis - Pins: 3 (S IN, S OUT, Scan_enable,...) - Area: (MUXes) 2-10% - Increased power dissipation - Performance degradation: (MUXes) 1-5% - Routing: scan chain connections, Scan_enable - Logic must be synchronous (or synchronous in test mode) - Long test application time (#cycles #vectors #FFs) + Sequential circuits become combinational in test mode + Significantly faster ATPG + High fault coverage (close to 100% for SSFs) page 33 of 42 Copyright Miron Abramovici, 1997 November 1997

34 Cost-Benefit Analysis... + Significantly faster fault simulation + Allows more accurate and more efficient diagnosis (for single or multiple stuck faults, bridging faults, delay faults) + Highly-structured technique + May be applied hierarchically: chips boards system field + Fully automated process + Well-supported by CAD vendors + Very useful for debugging, diagnosis and field service + Reduced time-to-market + Provides good basis for BIST page 34 of 42 Copyright Miron Abramovici, 1997 November 1997

35 BOARD 1 System-Level Scan CHIP BOARD 2 CHIP CHIP CHIP CHIP CHIP BOARD N CHIP CHIP CHIP System maintenance processor Select N Select 2 Select 1 S in S out N _ / T CLK page 35 of 42 Copyright Miron Abramovici, 1997 November 1997

36 Reducing Test Application Time Use k parallel scan chains S IN1 S OUT1 S INk S OUTk Compared to single chain: Cost: additional 2(k-1) pins (S IN, S OUT for each chain) Benefit: test ~k times faster page 36 of 42 Copyright Miron Abramovici, 1997 November 1997

37 Scan Testing Using Multiple Test Sessions Together Mode Single session S in R 1 R 3 one circuit - 12 PIs / 8 / 4 input registers are first in chain and output registers are last use only 12 cycles per vector test time = 1200 cycles S out R 2 C 1 (100 patterns) / 4 R 4 C 2 (20 patterns) / 8 page 37 of 42 Copyright Miron Abramovici, 1997 November 1997

38 Scan Testing Using Multiple Test Sessions... Separate Mode R 1 R 3 Two sessions S in 1. test C 1 - do not use the full chain / 8 / 4 test time = 800 cycles R 2 C 1 (100 patterns) / 4 R 4 C 2 (20 patterns) / 8 S out page 38 of 42 Copyright Miron Abramovici, 1997 November 1997

39 Separate Mode - Session 2 2. test C 2 - with reconfigured chain connect R 4 to S out inhibit clocking of R 2 S in R 1 / 8 R 3 / 4 Input stream: 4-bit vector, xxxx,... C 1 (100 patterns) C 2 (20 patterns) session time 20 8 = 160 cycles S out R 2 / 4 R 4 / 8 total test time = =960 (<1200) page 39 of 42 Copyright Miron Abramovici, 1997 November 1997

40 Scan Testing Using Multiple Test Sessions Overlap Mode R 1 R 3 Two sessions S in 1. one circuit - 12 PIs - for the first 20 vectors session time = 240 cycles R 2 / 8 C 1 (100 patterns) / 4 R 4 / 4 C 2 (20 patterns) / 8 C 2 already tested S out page 40 of 42 Copyright Miron Abramovici, 1997 November 1997

41 Overlap Mode - Session 2 2. test C 1 - as in separate mode session time 80 8 = 640 cycles total test time = =880 (<960) S in R 1 R 2 Note: S out sometimes separate mode leads to shorter tests optimal strategy depends on structure of scan chain, # of test patterns per block, and # of PIs and POs per block / 8 C 1 (100 patterns) / 4 R 4 R 3 / 4 C 2 (20 patterns) / 8 page 41 of 42 Copyright Miron Abramovici, 1997 November 1997