Multi-Channel Controller

Size: px

Start display at page:

Download "Multi-Channel Controller"

Gervase Owens
5 years ago
Views:

1 What you will learn What is the? How to interface to a T1 framer What is a super channel? How to initialize SIRAM How the MCC Receives Data How the MCC Transmits Data How the MCC Processes Interrupts 6-1

2 What is the MCC, Multi-Channel Communications Controller? Definition The MCC handles up to 128 serial, full-duplex data channels in four subgroups. One or more subgroups can be multiplexed through one of the MCCs corresponding time-slot assigner TDM channels. Block Diagram SIRAM Channels CH00 CH01 Buffer Descriptors TDMa TDMb TDMc M C C F x MCCx CH32 CH33 CH64 CH65 TDMd CH96 CH97 Features 1. The MCC routes data from/to up to 128 channels to up to 4 TDM busses. 2. Data flow is controlled by SIRAM and a register which allocates groups of channels, MCCx. 3. Each channel has an array of both transmit and receive buffer descriptors. 4. The data can be either HDLC or transparent. 5. Each MCC has a 16-byte FIFO which holds both data and channel number. 6. Each channel has a 2-byte FIFO; superchannels accumulate FIFO size. 6-2

3 How to Interface to a T1 Framer Introduction The diagram below shows how to interface the MPC8260 to a T1 framer, PM4388. Connection Diagram PA6/L1RSYNC1A PA7/L1TSYNC1A PA8/L1RXD[0]1A PA9/L1TXD[0]1A PC30/CLK2 PC31/CLK1 IFP1 EFP1 ID1 ED1 ECLK1 ICLK1 MPC8260 CSx* A[21-31] D[0-7] GPL2* GPL3* MPC931FA CS* A[10-0] D[7-0] RDB* WRB* XCLK PM4388 Features 1. This diagram shows how to connect an MPC8260 to a PM4388 T1 Framer. This device is an octal framer, but the connections are for just one. 2. The connections are basically in two parts: 1) the serial interface between the devices and 2) the management interface for initializing and getting status from the PM Beside transmit and receive connections, the transmit and receive clocks and syncs are provided by the PM4388. The clocks are generated from an external clock driver, MPC931, which gets an input from a MHz clock generator. 4. The management interface is connected to the memory controller using one of the UPMs. 6-3

4 What are the Basic MCC Structures? Definition The basic MCC structures reside in both dual port RAM and in external memory as shown below. Memory Maps Internal Memory DPRAM1 CEP, CSP, SCTT DPRAM2 MCC1 Parameter RAM MCC2 Parameter RAM External Memory Area for Receive & Transmit Buffer Descriptors DPRAM3 Registers SI RAM Interrupt Queues Internal Memory External Memory 1. The DPRAM1 area is used for Channel Specific Parameters, Channel Extra Parameters, and the Super Channel Transmit Table. 2. DPRAM2 is parameter ram for all the devices including MCC1 and MCC2. The programming model for MCC parameter RAM is on p DPRAM3 is not used. 4. SIRAM routes data to the specified channels. 1. Buffer descriptors for all channels are in an external memory area. 2. The interrupt queues. 6-4

5 How to Locate the Buffer Descriptors Introduction The diagram below shows how the Rx and Tx array spaces are located by pointers in MCC parameter RAM. MCC1 Memory Map Internal Memory DPRAM1 CEP RBASE External Memory Area for Receive & Transmit Buffer Descriptors 0x8700 DPRAM2 MCCBASE XTRABASE MCC1 Parameter RAM DPRAM3 Registers Interrupt Queues Description 1. In this slide, we ve highlighted the MCC1 parameter RAM area. It is located at 0x8700 in the internal memory map. 2. The first parameter in this area is MCCBASE, a pointer to the memory area (512 Kbyte) where the buffer descriptors are to be located. 3. A particular BD array is located by either RBASE or TBASE in the Channel Extra Parameters area. This value is an offset from MCCBASE. The base address of the BD ring is MCCBASE+8*xBASE where x is R or T. 4. The Channel Extra Parameters area is located in DPRAM1 at the location pointed to by XTRABASE, another parameter in MCCx parameter RAM. Any particular channel s extra parameter RAM can be located by calculating XTRABASE+8*CH_NUM. 6-5

6 Channel Extra Parameters Programming Model Channel Extra Parameters P TBASE TBPTR 4 6 RBASE RBPTR Description 1. TBASE and RBASE are offset pointers to the transmit and receive buffer descriptors for the channel.. 2. TBPTR and RBPTR are offset pointers to the currently active transmit and receive buffer descriptor. 6-6

7 How to Locate the Channel Specific Parameters Introduction The diagram below shows how the channel specific parameters are located. MCC1 Memory Map Internal Memory Ch. 0 Specific Params Ch. 1 Specific Params DPRAM1 External Memory Area for Receive & Transmit Buffer Descriptors 0x8700 DPRAM2 MCC1 Parameter RAM DPRAM3 Registers Interrupt Queues Description 1. Here we show where the channel specific parameters are located. They start at the first location in dual-port RAM. 2. Any particular CSP can be located by calculating DPR starting address + 64*channel number. 6-7

8 HDLC Channel Specific Parameters Programming Model (1 of 2) Channel-Specific HDLC Parameters P Offset Name Size Description Init Value 0 TSTATE Word Tx internal state 0xHH ZISTATE Word Zero-insertion machine State 0x ZIDATA0 Word Zero-ins high word data buffer 0xFFFFFFFF 0xC ZIDATA1 Word Zero-ins low word data buffer 0xFFFFFFFF 0x10 TBDflags Hword TxBD flags 0x12 TBDCNT Hword Tx internal byte count 0x14 TBDPTR Word Tx internal data pointer 0x18 INTMSK Hword Channel s interrupt mask flag 0x1A CHAMR Hword Channel mode register 0x1C TCRC Word Temp transmit CRC 0x20 RSTATE Word Rx internal state 0xHH x24 ZDSTATE Word Zero deletion machine state 0x00FFFFE0* 0x28 ZDDATA0 Word Zero del high word data buffer 0xFFFFFFFF 0x2C ZDDATA1 Word Zero del high word data buffer 0xFFFFFFFF 0x30 RBDflags Hword RxBD flags 0x32 RBDCNT Hword Rx internal byte count 0x34 RBDPTR Word Rx internal data pointer * For an inverted channel, 0x30FFFFE0 Description 1. Here we show the channel-specific parameters for HDLC. The ones which need to be initialized by the user are bolded. 2. Most parameters either don t need to be initialized or need to be initialized with a pre-determined value. The two exceptions are: 1) INTMSK, the mask register for this channel s interrupts, and 2) CHAMR, the channel mode register. 6-8

9 HDLC Channel Specific Parameters Programming Model (2 of 2) Channel-Specific HDLC Parameters (cont d) Offset Name Size Description Init Value 0x38 MFLR Hword Maximum frame length register 0x3A MAX_cnt Hword Maximum length counter 0x3C RCRC Word Temp receive CRC TSTATE, RSTATE - Internal Transmitter, Receiver State P. 27-9, GBL BO TC DTB BDB INTMSK - Interrupt Mask P NI ID MR RX BS RX - UN TX - B D L F F Y B CHAMR - Channel Mode Register P MO PO ID 1 0 TS RQN NOF DE L LM CR 0 C Description 1. MFLR is another parameter in the CSP area that needs to be initialized to the max frame length. 2. As we ve seen before, TSTATE and RSTATE are actually one word size, but we need only concern ourselves with initializing the upper byte. 3. CHAMR, among other things, allows us to select between HDLC and transparent. Also the POL bit (for POLling) allows the user to turn off polling of the transmit bits during those times the user knows no transmit will be taking place. This eliminates using bus bandwidth to check for a buffer ready even though its known there won t be any. 6-9

10 How to Allocate the Channels Introduction Although 256 channels are possible, they must be allocated by MCC and TDM. Allocation by MCC SI1RAM Channels MCC1 This allocation of channels is fixed. SI2RAM Channels MCC2 Allocation by TDM TDM1a TDM1b TDM1c TDM1d MCCF1 Channel Config Register MCC1 This allocation of channels is programmable MCC2 is routed to the TDM2s via MCCF2 Channel Allocation 1. Channels are allocated in two ways: 1) by MCC number (fixed allocation) and 2) by TDM (programmable allocation). 2. Channels belong to SI1RAM and MCC1. Channels belong to SI2RAM and MCC2. 3. The 128 channels allocated to an MCC can be further allocated to the TDMs using the Channel Configuration Reg, MCCx where x=1 or

11 How to Allocate by TDM Introduction The example below shows how to allocate channels by TDM. Example Allocate the channels so that: TDM Channels 00 1a b 1c 1d 2a 2b 2c 2d Not used Not used Not used MCCF1 MCCF2 Channel Numbers Gr 1 Gr 2 Gr 3 Gr pimm->mccf1 = 0x90; pimm->mccf2 = 1; Example Description 1. In this example, it is desired to allocate the channels to the TDMs as shown in the table. The first 4 entries in the table are for the TDM1s and MCC1, and the second 4, for TDM2s and MCC2. 2. The values shown for MCCF1 and 2 will allocate the channels as shown in the table. 6-11

12 Exercise - Allocate by TDM Introduction Exercise In the exercise below, determine how MCCF1 and MCCF2 should be programmed. Allocate the channels so that: TDM 00 1a 01 1b 10 1c 11 1d 00 2a 01 2b 10 2c 11 2d Channels pimm->mccf1 = ; pimm->mccf2 = ; MCCF1 MCCF2 Channel Numbers Gr 1 Gr 2 Gr 3 Gr

13 What is a Super Channel? Definition A super channel is multiple DS0s, but not a full T1 frame. Example Frame T1 Frame 1 24 Typically, one DS0 or time slot, is routed to one channel In some cases, a subscriber requires several DS0s. This is referred to as a superchannel. Application For receive, an HDLC channel need not be a super channel and, in fact, making it a normal channel is more efficient. For receive, only transparent should be a super channel. Features 1. Normally each time slot in a T1 frame is allocated to a channel. 2. If a subscriber needs more than one time slot, s/he can get a super channel consisting of two or more timeslots. 6-13

14 How to Program SI_RAM for T1, No Superchannels Introduction The example below shows how to program SI_RAM for T1, no superchannels. Programming Model SI_RAM Entry P LO SU BY LS 1 MCSEL CNT OP P T T Example Program SI1RAM to receive a T1 frame. Route DS0s 1-24 to channels Features 1. Each entry is designated for an MCC because bit 0 is No loop mode because bit 1 = 0 in each entry. 3. No super channels because bit 2 = 0 in each entry. 4. The 24 channels for a T1 frame are in bits 3-10 of each entry. 5. Each entry specifies that one byte is to be received by each channel. 6-14

15 How to Program SI_RAM for T1, Superchannels, Receive (1 of 2) Introduction Example The example below shows how to program SI_RAM for T1 superchannels for receive. Program SI1RAM to receive a T1 frame with the following routing: Time Slots Channel Numbers SI1RAM TS SI LO SU BY LS MCSEL CNT OP P T T Example 1. In this example, a T1 frame is to be routed as shown. It has two super channels, 2 and 5. Time slots 11 to 24 are to be routed to channels 7 to In SI1RAM, all entries must have 1 in bit 0 to select MCC. Bit 1 must be 0 for no loopback. 3. Entry 0 in SI1RAM is TS 1 of the frame which is to be routed to channel 1 which is not a superchannel. Therefore, in entry 0, SUP=0; MCSEL is the channel number, 1; and CNT+BYT is Entry 1 in SI1RAM is TS 2 of the frame which is to be routed to channel 2 which is a superchannel. Therefore, in entry 1, SUP=1; MCSEL is the channel number, 2; and CNT+BYT is 0001 to indicate the first entry of the superchannel. 5. Entry 2 in SI1RAM is the same as entry 1 except that the channel is Entries 3 and 4 are for TSs 4 and 5 which are also routed to channel 5. These entries are the same as entry 2 except that CNT+BYT=1110 because these are superchannel entries after the first entry. 6-15

16 How to Program SI_RAM for T1, Superchannels, Receive (2 of 2) Time Slots Channel Numbers SI1RAM (cont d) TS SI LO SU BY LS MCSEL CNT OP P T T x x Example 1. Subsequent entries are initialized in the same manner. Notice that SI1RAM entries 6 and 7 for TSs 7 and 8 are routed to channel 2 which is a super channel that has had an earlier entry. Therefore, in each case, CNT+BYT= The 24th TS is in entry 23. It is a regular channel entry with the LST=

17 How to Program SI_RAM for T1, Superchannels, Transmit (1 of 3) Introduction Problem The example below shows how to program SI_RAM for T1 superchannels for transmit. Program SI1RAM to transmit a T1 frame with the following routing: Time Slots Channel Numbers Procedure for Programming 1. For super channels, MCSEL must be different in every entry. 2. If the SIRAM entry is for a regular channel, then SUP=0, MCSEL=channel number, and CNT+BYT can be 1 bit to 2 bytes. 3. If the SIRAM entry is for a super channel, then SUP=1, MCSEL=an index into the SCT, and SCTE=channel number. If this is the first entry for the super channel, then CNT+BYT=0001; else CNT+BYT=1110. Description 1. Now we want to initialize SIRAM for transmitting a T1 frame with the same routing as the previous example. 2. The programming procedure for transmit is shown. It is somewhat different because of the use of a Super Channel Table which contains the channel number while MCSEL contins an index into the SCT. 6-17

18 How to Program SI_RAM for T1, Superchannels, Transmit (2 of 3) TS SI SI1RAM xa xC xE Superchannel Table Time Slots Channel Numbers Features 1. As before, each entry has a one in bit 0 for MCC, and zero in bit 1 to indicate no loopback. 2. The first entry is for a regular channel and is the same as we saw for receive. 3. The second entry is for superchannel 2 so SUP=1. MCSEL is an index into the superchannel table, so it is set to the SIRAM entry number, in this case, one. Since this is the first entry for super channel 2, CNT+BYT=0001. The corresponding entry in the superchannel (2*2) is initialized for channel The third entry is for superchannel 5. Therefore SUP=1, the SIRAM entry number 2, CNT+BYT=0001 because it s the first entry, and the super channel entry is set to The next two entries are also for super channel 5. They are the same as entry 2 except that CNT+BYT=

19 How to Program SI_RAM for T1, Superchannels, Transmit (3 of 3) TS 9 SI 8 SI1RAM xA Superchannel Table xC xE x x2a x2c x2E 2 0x

20 How to Locate the Superchannel Tables Introduction The diagram below shows how the superchannel tables are located in dual-port RAM. MCC1 Memory Map Internal Memory DPRAM1 Superchannel Tables External Memory Area for Receive & Transmit Buffer Descriptors 0x8700 DPRAM2 MCCBASE SCTPBASE MCC1 Parameter RAM DPRAM3 Registers Interrupt Queues Description 1. The superchannel tables are pointed to by an offset pointer in MCCx parameter, thus locating the super channel tables in DPRAM

21 Exercise - Programming SI_RAM for T1 (1 of 4) Introduction Example The example below shows how to program SI_RAM for T1 superchannels for receive. Program SI_RAM to receive a T1 frame on with the following routing: SI1RAM, Receive TS SI LO SU BY LS MCSEL CNT OP P T T

22 Exercise - Programming SI_RAM for T1 (2 of 4) SI1RAM, Receive TS 6 SI

23 Exercise - Programming SI_RAM for T1 (3 of 4) SI1RAM, Transmit LO SU BY LS MCSEL CNT OP P T T TS 1 SI 0 SI1RAM Superchannel Table xA 7 6 0xC 8 7 0xE 9 8 0x

24 Exercise - Programming SI_RAM for T1 (4 of 4) SI1RAM, Transmit TS 10 SI 9 SI1RAM x12 Superchannel Table x x x x28 0x2A 0x2C x2E 0x30 0x

25 What is an Interrupt Circular Queue? Definition Interrupt Circular Queue Diagram Features The interrupt circular queue is a structure in memory in which interrupt information is stored when a channel interrupt occurs. xintbasey CPU Pointer xintptry V W 0 0 Interrupt Flags Channel Number 0 0 Interrupt Flags Channel Number 0 0 Interrupt Flags Channel Number 1 0 Interrupt Flags Channel Number 1 0 Interrupt Flags Channel Number 1 0 Interrupt Flags Channel Number 1 0 Interrupt Flags Channel Number 0 0 Interrupt Flags Channel Number 0 0 Interrupt Flags Channel Number 0 0 Interrupt Flags Channel Number 0 1 Interrupt Flags Channel Number Word When a channel interrupt occurs, PowerQUICC2 writes the interrupt information to the location pointed to by xintptry. Entries with the valid bit set need to be processed by the CPU. The end of the queue is marked with the W = 1. Additional Description 1. The interrupt queues are located by the pointers TINTBASE, RINTBASE0, RINTBASE1, RINTBASE2, and RINTBASE3 in parameter RAM. 2. When the CPU processes a channel interrupt, it must clear the V bit as part of the interrupt service routine. 6-25

26 How to Locate the Interrupt Queues Introduction The diagram below shows how the interrupt queues are located. MCC1 Memory Map Internal Memory DPRAM1 External Memory Area for Receive & Transmit Buffer Descriptors 0x8700 DPRAM2 MCC1 Parameter RAM TINTBASE TINTPTR RINTBASE0 RINTPTR0 DPRAM3 Registers Interrupt Queues Description 1. Here we show where the interrupt queues are located. There are five interrupt queues: one for transmit and four for receive. 2. Each queue has a base pointer and an active pointer, for example RINTBASE1 and RINTPTR1. Four receive interrupt queues allow the user to sort interrupts. For example, if an MCC implements 4 T1/E1 lines, one interrupt queue can be used for each TDM. 3. All channels use the single transmit interrupt queue. Each channel specifies in the channel parameters which receive queue is to be used for its interrupts. 6-26

27 Interrupt Programming Model Interrupt Queue Entry p TX NI ID MR RX BS RX V W - UN - B D L F F Y B - Channel Number - MCCEx - MCC Event Register p QO RIN QO RIN QO RIN QO RIN TQ TI GU GO - - V0 T0 V1 T1 V2 T2 V3 T3 OV NT N V MCCMx - MCC Mask Register p QO RIN QO RIN QO RIN QO RIN TQ TI GU GO - - V0 T0 V1 T1 V2 T2 V3 T3 OV NT N V Description 1. The interrupt queue entry is structured as shown. 2. The event and mask registers have 2 bits for the global events (GUN,GOV), overflow bits for each interrupt queue (QOVx and TQOV), and interrupt bits for each interrupt queue (RINTx and TINT) where x = 1,2,3 and

28 How the MCC Processes Interrupts (1 of 2) Introduction The diagram below show the flow of interrupt processing on the PowerQUICC 2 MCC. MCC Interrupt Processing Flow Start Interrupt Occurs GOV or GUN? N Interrupt masked? Y End Y Set bit in MCCEn End N xintptry[v]=0? Y N Enter interrupt info into queue; set V; increment xintptry Set MCCEn.xQOVy End A Additional Comments 1. If a global interrupt occurs, GOV or GUN will set directly. 2. If a channel interrupt occurs, it may be masked by INTMSK. 3. Assuming there is room in the queue, an entry will be made for the channel interrupt. 6-28

29 How the MCC Processes Interrupts (2 of 2) A MCC Interrupt Processing Flow RxF event? N Y Decrement GRFCNT GRFCNT=0? N End Y Load GRFCNT with GRFTHR Set MCCEn[xINTy] End Description 1. Each time an interrupt occurs, GRFCNT is decremented. When it is 0, the event bit is set in the MCCx event register. 6-29

30 Exercise - Initializing an MCC for Interrupts (1 of 2) Introduction In the exercise below, initialize MCC2 for the specified interrupts. Exercise Problem: Initialize MCC2 to respond to the following interrupts: global overrun and underrun, interrupt queue overrun for transmit and receive queue 0, and transmit interrupt and receive queue 0 interrupt. The transmit queue is to be twenty entries long at 0xA and the receive 0 queue, forty entries long at 0xA pq = (qptr *) 0xA ; /* init xmit intrpt q*/ for (j=0; j<20; j++) *pq++ = 0; *--pq = 1<<30; pimm->mcc2. = 0xA ; /*init xmit intrpt q base pntr */ pimm->mcc2. = pimm->mcc2. ; /*init xmit intrpt q actv pntr */ pq = (qptr *) 0xA ; /* init recv intrpt q*/ for (j=0; j<40; j++) *pq++ = 0; *--pq = 1<<30; pimm->mcc2. = 0xA ; /*init recv intrpt q base pntr */ 6-30

31 Exercise - Initializing an MCC for Interrupts (2 of 2) pimm->mcc2. = pimm->mcc2. ; /*init recv intrpt q actv pntr */ pimm->mcc2. = 5; /*init frame threshld*/ pimm->mcc2.gfrcnt = pimm->mcc2.gfrthr; /* init frame count */ pimm-> = 0xC00F; /*enbl glob,qov,xints*/ 6-31

32 How the MCC Transmits Data Introduction The diagram below show the flow of transmitting data. MCC Transmit Flow TSTATE=0xHH LST=1 End xmit Three-state xmit pins Xmit Ready Xmit Global Underrun Occurs Before entering this state: Initialization should be complete TxBDs are ready CHAMR[POL] = 1 Frame Sync Data is transmitted according to SI_RAM and MCCFx GUN Stop Host Reinitialization Transmits abort sequence Sets MCCEn.GUN Transmits idles 6-32

33 How the MCC Receives Data Introduction The diagram below show the flow of receiving data. MCC Receive Flow RSTATE=0xHH Recv Ready Before entering this state: Initialization should be complete RxBDs are ready Frame Sync LST=1 End recv Recv Global Overrun Occurs Data is received according to SI_RAM and MCCFx GOV Stop Host Reinitialization Updates RSTATE to prevent further reception Sets MCCEn.GOV 6-33

Freescale Semiconductor, I

Freescale Semiconductor, I nc. MPC8260ESS7UMAD/D 12/2002 Rev. 0.1 Enhanced SS7 Microcode Specification Addendum to MPC8260 RevB ROM Microcode Additions nc. nc. About This Document This document describes additional functionality