Understanding Strip (Finite) and Slot (Infinite) Ground based EM simulations in ADS

Transcription

1 Understanding Strip (Finite) and Slot (Infinite) Ground based EM simulations in ADS ADS offer three ways in which designers can model the return path (ground) for their structures to perform EM simulations. This short tutorial note explains about each of them so that designers can choose the appropriate method while simulating their structures using ADS Momentum EM solver. Option1: Using Cover Plate for Ground This is usually the default option where we can notice cover plate at the bottom of the substrate stack up. Limitation with this option is that it can only be defined either at the Top or Bottom side of the stackup definition and not on intermediate layers. This option works best with typical Microstrip or Stripline configuration as used in traditional RF/Microwave circuit designs. Whenever Cover is defined in the stackup, this is picked as default return path (GND) for all + Signal Pins placed in the layout. In other words it is like defining PEC (Perfect Electrical Conductor) and beyond this no other substrate layers can exist. Also, it is not possible to create any defect in the ground plane while using this option. Incase defected ground is needed then one has to look for other 2 options (Strip and Slot) discussed in this tutorial note. Impact of Cover definition in layout: Cover definition in the stackup doesn t change how layout is drawn in any manner, designers just need to draw their desired signal traces/shapes on their STRIP layers and connect + Pin at the desired places on the STRIP layer as per their layer mapping in stackup definition. In above snapshot we can notice that cond layer is used as main STRIP layer in which we would like to design our circuit. During EM simulation, negative pin will automatically be place right beneath + Pin for return current modeling on this Perfect Conductor Cover plate..

2 Option2: Using Slot Plane for Ground Another simple option to define return path (ground) is to use Slot Plane definition in the substrate stackup. Slot planes can be defined on any of the layers (top, bottom or intermediate) in the stackup editor and pretty simple to use. While defining Slot plane, one need to select a drawing layer from the layer list available in the substrate editor window and same has to be mapped on the interface of dielectrics as shown below: Impact of Slot Plane definition in layout: One thing to remember while using Slot Plane is that it is negative layer and it has to be drawn accordingly in layout. If we want full solid plane on SLOT layer as a ground plane then nothing has to be drawn on Layout on Slot layer (pc1 in our example above) but if we need defected ground or VIA clearance etc then we need to draw desired shape in the layout Example1: Line on cond layer and solid ground on pc1 slot layer Here, we can see we haven t drawn anything on pc1 layer in layout because we want solid ground plane (remember, it is negative layer..)

3 Example2: Interconnecting VIA for cond and cond2 metal layers Here we can see that we have drawn object on pc1 i.e. slot layer where we don t want ground plane to exist. Apart from this circular area we shall have ground plane..remember that SLOT is a negative layer for layout drawing purposes. Also remember while using SLOT layer in our stackup definition we only need to place Pins on Signal lines i.e. cond and cond2 and respective ve Pins are automatically placed at nearest SLOT layer right beneath + Pins.

4 Port Editor Window: Looking at the port editor window we can observe that ve Pin for each termination is defined as Gnd which refers either to the Cover Plate or SLOT available in the stackup editor and designers don t need to worry about the ve pins. While working with Allegro or Xpedition etc kind of Layout softwares, kindly don t confuse this Gnd used in Port editor window to the GND layers which you may have in your Allegro or Xpedition etc kind of layout designs. These are two different things and shouldn t be mixed up. Simulating Slots in Ground Planes Slots in ground planes are treated in a special manner by Momentum. An electromagnetic theorem called the equivalence principle is applied. Instead of attempting to simulate the flow of electric current in the wide extent of the ground plane, only the electric field in the slot is considered. This electric field is modeled as an equivalent magnetic current that flows in the slot. Momentum does not model finite ground plane metallization thickness. Ground planes and their losses are part of the substrate definition. Option3: Using Strip Plane for Ground Third and final way to define ground plane is to use finite ground plane approach in ADS layout. To define the finite ground approach, the layers which are supposed to be used as Ground should be defined as regular STRIP conductor mapping and the interface should be defined as STRIP plane (which is the default option in substrate editor) We can define the properties of this layer like any other conductor by defining the Conductor material/conductivity, Thickness etc as shown below.

5 Impact of Strip Plane definition in layout: While using Strip plane method of defining finite ground pattern is pretty straightforward in terms of layout and we just need to draw the ground plane as we desire. Additional workload on designers while using Finite ground approach is to make sure: a. There should be a ve Pin placed on desired ground layer nearest possible to the +ve Pin b. Designers need to define proper + and Pin pairing for each termination necessary Example1: Line on cond layer and finite ground on pc1 layer We can notice a simple transmission line drawn on cond layer and the finite ground shape being drawn on pc1 layer in the snapshot below While placing Pins for simulation, we need to make sure that there is a Pin present on desired ground layer for every Pin on Signal layer. In present case we shall have 2 Signal Pins placed on cond layers which shall be used as +ve Pins and 2 corresponding Pins on pc1 layer which shall be used as ve Pins to make +/- pairs. Note: It is not mandatory to have ground plane to be always defined on a separate layer. It is possible to have regular signal lines and ground plane to be on the same metal layer like is the case while using CPW (Coplanar Waveguide) based structures.

6 Port Editor Window: Default Port Editor window will appear as shown above with all 4 ports shown as 50 Ohm terminations but that is not the case for us. Also, need to remember that there is nothing called Gnd where return current would be referred to. We are using Finite ground approach and we need to define where we want return current to travel and how the fields will be excited in our structure. Depending on the order in which Pins are placed, we can drag and drop Pins placed on ground layer to the ve terminals of the Ports in Port Editor window as shown below In our case P1 and P3 are + and terminals for Port1 and P2 and P4 are + and terminals for Port2 resulting in 2-port network simulation.

7 Example2: Line on cond and cond2 layers with interconnecting VIA and ground plane on pc1 layer Here is another example of lines on cond and cond2 layers interconnected by a VIA drawn on hole layer as per the stackup definition Snapshot with cond and cond2 layer switched off. Zoomed-In view of the VIA transition where the clearance was created in pc1 layer to avoid VIA getting shorted with ground plane on pc1 layer

8 Simulation and Results Comparison between STRIP and SLOT ground approach In order to compare results obtained by Finite Ground (Strip) or Slot ground approach, we shall run simulation on examples shown previously and results are summarized below. Care is taken to make sure simulation; mesh settings etc are kept common for respective cases Example1: Long Transmission Line We can notice here that responses are pretty comparable with very minor differences which may be due to the different formulations used for finite ground and Slot mode simulation approach but TDR showing impedance predicted is nearly the same so either mode of simulation should serve the purpose. Benefit of using SLOT mode for complex designs where lot of conductor is present on ground layers is that it saves significant amount of simulation time and memory requirements with minimal loss of accuracy and not to forget time spent on + & - Pin pairing for each Terminations.

9 Example2: Lines with Interconnecting VIA Again we can notice that responses agree pretty well for 2 nd case as well END OF DOCUMENT-----