Modeling of Connector to PCB Interfaces. CST User Group Meeting, September 14, 2007 Thomas Gneiting, AdMOS GmbH

Transcription

1 Modeling of Connector to PCB Interfaces CST User Group Meeting, September 14, 2007 Thomas Gneiting, AdMOS GmbH

2 Table of Content Introduction Parametric CST model of connector to PCB interfaces Application in design analysis Integration into overall signal integrity simulations of complete systems. Hardware to model correlation Summary

3 Introduction: Data Communication Systems Daughter card with e.g. Processor, IO, etc. Male Connector Female Connector System (e.g. Router, Switch) with back plane

4 Interface between Connectors and PCBs High speed connector Connector geometry is fixed, interface geometry is selected by PCB designer. It depends on layer stackup and layout. Ground pads and vias Printed Circuit Board (PCB) Signal pads, vias and traces Ground planes (insulator is not shown here)

5 Effects on Signal Integrity Characteristic impedance of a typical signal path in a backplane system High Speed Connector Backplane 2. Connector 110 Ideal tolerance of 100Ω ±10% of path impedance impededance Ohm Pressfit vias of high speed connectors often exceed these limitations!

6 Parametric CST Model (1) Via: Via diameter Pad diameter Antipad diameter Backdrilling Via shape Layer stack up: Up to 40 metal layers Different materials Lines: Width Spacing Layout Pairs per channel

7 Parametric CST Model (2) Waveguide ports on the connector side are implemented as coaxial lines Example of backdrilling, where the via is removed to reduce the stub. Waveguide ports on the PCB side are placed directly on striplines at the border of the calculation space.

8 Design Analysis (1) a b c d e f Aggressor pair Victim pair Vin tr=1ns tr=0.5ns tr=0.2ns tr=0.1ns tr=0.05ns A typical measure for the performance of a via array is the multi pair crosstalk: Worst case scenario. All signal pairs around a victim pair are switching. The multi pair crosstalk is the sum of the maximum values of each crosstalk contribution. Signals with different rise times

9 Design Analysis (2) NEXT 1ab NEXT 2ab NEXT 3ab XTnear_1ab XTnear_1cd NEXT 1cd XTnear_2ab XTnear NEXT (sum) XTnear_3ab XTnear_3cd NEXT 3cd The outcome helps PCB and system designers to find optimized PCB layouts for the routing of the transmission lines to the connectors NEXT 1ef NEXT 2ef NEXT 3ef XTnear_1ef XTnear_2ef XTnear_3ef trise_ns NEXT N_1ab N_1cd N_1ef N_2ab N_2ef N_3ab N_3cd N_3ef

10 Integration into Circuit Simulation (1) PCB Striplines Signal path Backplane High Speed Connector to Board Transition High Speed Connector System Host Board Transmitter/Receiver Transmitter out + 8B10B 6.25 Gbit/s out - Daughtercard Daughtercard Signal via with Vias (here for differential signal lines)

11 g h g h Integration into Circuit Simulation (2) VAR Design_Settings Trace_length=500 Trace_width=0.15*factor_width Trace_spacing=0.4 Trace_thickness=0.035 Pre_break_height=0.24 er=fr4_er tan_d=fr4_tan_d cbi_backplane=cbp_pf_fr4_top Differential traces: ADS PCB multiline models cbi_daughter=cdt_pf_fr4_top Connector plus board contact (Micro Vias or not): Integration of Touchstone Spar files coming from CST Microwave Studio g Port P1 Num=1 h Daughter card Port P3 Num=3 h g spar_lb_daughter X2 er_dt2=er B_dt2=2*Pre_break_height T_dt2=Trace_thickness tand_dt2=tan_d W_dt2=Trace_width S_dt2=Trace_spacing len_dt2=50 g-h e-f c-d a-b a-b c-d e-f spar_stecker_alle Stecker1 g-h g Port P2 Num=2 h Daughter card Port P4 Num=4 h g spar_lb_daughter X3 er_dt2=er B_dt2=2*Pre_break_height T_dt2=Trace_thickness tand_dt2=tan_d W_dt2=Trace_width S_dt2=Trace_spacing len_dt2=50 CST models are integrated as: Touchstone files SPICE netlists g-h e-f c-d a-b a-b c-d e-f spar_stecker_alle Stecker2 g-h Models are hierarchical and fully parameterized to allow simulation of different configurations (trace lengths, board material) or statistical analyses. Backplane spar_lb_backplane Backplane er_bp2=er T_bp2=Trace_thickness B_bp2=2*Pre_break_height tand_bp2=tan_d len_bp2=trace_length W_bp2=Trace_width S_bp2=Trace_spacing

12 Integration into Circuit Simulation (3) Eye pattern analysis of a complete transmission path including drivers and receivers. Datarate: 5Gbit/s 8B10NRZ code. out + Transmitter 8B10B 6.25 Gbit/s out - Ue1 Ue2 1 2 DUT 7 8 Ua1 Ua2 model_transmitter_6p25_gbit Ue3 X2 out + Ue4 Transmitter 8B10B 6.25 Gbit/s out Ua3 Ua4 model_transmitter_6p25_gbit Ue5 X3 out + Ue6 Transmitter 8B10B 6.25 Gbit/s out - model_transmitter_6p25_gbit model_dut X4 X1 sim_index=3 TRANSIENT Ua5 Ua6 Var Eqn

13 Hardware to Model Correlation Hardware to model correlation on test PCBs. Measurements are performed in the time domain. For the simulation, CST based Touchstone files of the connector and vias are used.

14 Summary It was demonstrated that vias and press fit holes in PCBs can cause a significant disturbance of the signal quality in high speed data links. Modeling these elements is a very important step to perform both, design analysis and overall system simulation. We showed an approach using fully parametric CST simulation models to enable this analysis in the pre-layout phase of a design project. Finally, the diagrams in the hardware to model correlation demonstrated the accuracy of the simulation approach versus the measured data.