Ramasamy Krishnan Boeing Electronics High Technology Center Seattle, Washington

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1 Conventional Binary Number System (BNS) versus Residue Number System (RNS) Digital Signal processing Architecture Suitable for Complex Digital Filtering Ramasamy Krishnan Boeing Electronics High Technology Center Seattle, Washington Abstract In general, the number of active devices used to build a circuit, decides the power consumption and the area of the circuit in the VLSI technology. Hence, algorithms are developed to compute the number of active devices for residue number system (RNS) and binary number system (BNS) signal processing architectures. The pre-charged CMOS technology is used in order to build the filter architecture. The ROM lookup table and 2s complement multiplier are used as computational cells in the RNS and BNS respectively. A direct implementation transversal systolic filter architecture is considered in RNS and BNS algorithms. 1. Introduction In the last two decades, considerable efforts have been made to develop computationally high speed algorithms to process digital signals. Mainly these algorithms are based on the Residue Number System (RNS) arithmetic computed over finite fields and rings and the conventional Binary Number System(BNS) arithmetic. If the BNS based algorithms are employed in implementing the hardware to process the digital signals, a comparatively large amount of time will be spent in the multiplication operation, and large register lengths will be required. One of the problems in implementing the digital filter algorithms using the conventional BNS is the possible accumulation of round-off and truncation error during computation because of finite word length constraint.[5]. In RNS, the binary operations of addition or subtraction have no inter-digit carries or borrows, and multiplication does not generate partial products. In fact, in some hardware realizations multiplication and addition have identical speed and cost, and, in certain cases, multiplication by constant can he a 'free' operation. The primary advantage of the RNS is that the bir.z:y operations of addition, subtraction and multiplication can he performed on the respective residue digits in the L-independent parallel channels. The over head is the coding and decoding. Hence, the RNS is of particular interest in digital signal processing. In the early ~O'S, the RNS was extensively investigated and demonstrated for the use of general purpose high speed computer applications. The early investigators such as savaboda and valach[3] were interested in using the RNS for the design and construction of general purpose computer which resulted in the EPOS general purpose computer. Residue technique did not achieve wide spread usage at that time because the ferrite core memories were too expensive and bulky. In addition, the RNS has difficulties in implementing operations of division, scaling, sign detection and magnitude comparison. Further more, there were not efficient algorithms for coding and decoding at that time. Although many shortcomings still exists in applying the RNS to general purpose computer design, the techniques were well suited to the implementation of digital signal processing algorithms. In the RNS, once the coefficients and input data are quantized, there is no computational error due to round-off or truncation. However, when implementing the IIR filter using RNS algorithms, scaling is necessary to keep the data with in the limited dynamic range. It is reported in [2], that the RNS based recursive filter will provide better signal to noise ratio than the conventional filters due to the quantization error. A tremendous amount of research has been published in this field[6] In this paper, we are computing the architectural requirements in terms of power for the RNS and BNS based filters, In order to do this computation, a transversal filter architecture to process a continuous stream of incoming complex data at a rate of MHz. Recently, it has been shown that complex multiplication over Complex Quadratic Rings can be reduced to 2 base field multiplications, with the proviso that the field modulus is of the form 4K+1. This work was directed towards the study of RNS architectures in which parallel independent operations on several small quadratic rings are used to produce a result over a ring isomorphic to the direct sum of smaller rings. The resulting number 23ACSSC MAPLE PRESS 873

2 system has been termed the quadratic Residue Number System (QRNS). The results, however, also apply to operations computed over a single ring. These results have been extended to the Modified Quadratic Residue Number System (MQRNS) with ring operations for moduli of any form[4]. 2. Systolic Implementation of Direct Transversal Filter Architecture in QRNS The transversal filter can be described by the inputoutput relationship: N- 1 y(n)= Z h(k). x(n-k) for,1... N-1. (1) where (x(n-k)) are the input samples, (y(n)) are the output samples, h(k) are the filter coefficients and N is the order of the filter. The direct computation of (1) can be considered in the QRNS as follows: YI (n) = YI mi (n) 0 YI mz d YI ml (n) The direct implementation the systolic architecture in the QRNS is shown in fig-i. The main computational element here is the look-up table modules. In the following section we have developed algorithms to compute power for look-up table module. xlrl The element pairs of the input samples and the filter coefficients can be computed as follows: Let h(k)= a(k) + ip(k) be the impulse response and x(n-k)= y (n-k)+ is(n-k) be the complex sequence of the FIR filter where i=d-i is a complex operator. Let the operator j for the QRNS can be computed using jzt = -1 mod mt and IS [ 1.2,._... 1 and mt is of the form 4Kt+l Mk)t = I awt + jtp(k)t lmt x(n-k)t= I y (n-k)t+ jt6(n-k)t Imt (2) h*(k)t =I a(k)t - jtp(k), Imt x*(n-k)t = I y (n-k)t-jt6(n-k)t lmt The quadratic residue pairs for the output of the FIR filter can be computed as: N-1 Q(n)t =I Z h(k)t. x(n-k)tlmt (4) N-1 Q*(n)t =I Z h*(k)t. x*(n-k)tlmt (5) The real and imaginary parts of the FIR filter output can be computed as: (3) Figure 1. Syrtolrc Architecture for Complex FIR Filter in the QRNS 4.Power Computation in look-up table Computational Modules The memory cells to store '0 and '1' in CMOS are shown in fig-2. It uses a precharge principle. The output bit lines are precharged low or '0 during QI. e 4 0 s U 81 YR(n)t = I 2-l. (Q(n)t + Q*(n)t)lmt (6) YI(n)t = jt-l(q(n)t-q*(n),)l,t (7) For the mapping the CRT can he used on the real and imaginary part as follows: YR (n) = YR mi (n) d YR "2 YR ml (n) (8) To Store Logical 0 To store logical 1 Figurel. Memory cells 874

3 During, the selected word line goes low (all others remain 1, implying that a precharge decoder to select word lines can be used). If a p-channel transistor is placed at the intersection of the bit-line and the selected word line, a 1 will be transmitted to the bit line; otherwise, 0 will be transmitted (see fig-3). 0.WORD is the logical output from the decode (Supporting) circuits. Loak~upTSle artay figure 3. CMOS Look-up Table Module for an 8~bit modulus In CMOS ROM, there are two components that establish the amount of power dissipated. They are: 1. Static power (P,) - due to leakage current 2. Dynamic dissipation (pd)- due to: i. switching transients current ii. Charging, discharging of load capacitance Therefore the total power dissipation =Pt = Ps + Pd (9) Among the two, the second one is predominant factor, but if the number of look-up tables increases which is always the case in the RNS architecture, we cannot completely neglect the first one. Therefore, the static power can be computed as: n Ps= Z Lecage current x VDD (10) I where n is the number of devices and the dynamic power is: Pd = CL VDD~ F (11) where F = Frequency of operation CL = Load Capacitance Eqn.(9) can be used to compute the total power dissipation in a ROM look-up table module. Once the technology and the type of drive is fixed, we can obtain the value of CL as shown in [7]. Since the static power is proportional to number of active devices, it can be computed for the look-up table, for any given prime modulo mi, i E {1,2... L). Note: The following computation ts performed predominantly for the storage array for a prime moduli. For the decoder or the supporting circuit the number of active devices based on the gate counts. Let ni = number of bits used to represent any prime modulus mi, then ni = r logz mi 1 (12) where r.1 represents the ceiling function for the integer truncation. That is ni should be the next integer value of log2 mi. Let Li = 2"' - mi and N; = number of the memory locations in modulo mi look- up table. If Li = 0, then Ni' = 22ni and if Li # 0 then Li- 1 N; = 22ni. z {.(ZK +I)) (13) K=O The proposed memory cell can be used in a ROM array with precharged n-devices to store the 'Os' and so we need only p-devices in combination of the above n-devices to store 'Is'. That means, we need not have separate location to store a word with all 'Os'. Based on this, the number of memory locations needed to store the rest of the words in the look-up table can be computed as follows: Let NiA/S and NiM be the number of memory locations needed to implement the modulo mi addersubtractor and multiplier respectively. Then for adder-subtractor NiA/S = N(. mi (14) and for multiplication NiM = Ni' - [ Zni + - (2Ki + 3)l (15) where Ki = Li - 1 and ki =0, when Li - 1 < I. The number of devices required for adderlsubtractor look-up table is: N. ai - N.AIS, ni I and for the multiplier N,~ = N ~M. ni (16) The static power in the look-up table is NG or Nmi P,M= Z Lecage current x VDD (17) 1 PdM = CL VDD2 F (18) The dynamic power in the look-up table is: The decoder circuit will be implemented using logic gates. Large number of gates with many inputs ( for example if it exceeds 3 or 4) would be difficult to implement in any technology. Therefore the first level of decoder circuits may be implemented either using 2 or 4 input logic gates and the remaining 875

4 levels may he implemented using two input gates (see fig-3). In this approach, to compute the access time of the memory, the critical path of the signal should be traced and the effective capacitance can he computed using the procedure Lct us consider first the horizontal decoder circuits and the same will be repeated for the vertical decoder circuits. If ni is greater than 2 hits, then the total number of gates Ng = N1 + N2 + NI (19) where NI = no. of gates in the first level N2 = no. of 2 input gates in the rest of the levels N' = no. of gates to address the table locations. Therefore the total number of gates for the both decoder circuits will be 2Ng. The total number of devices in the decoders is ND = nng + 2(N2 + N') (20) where n is the total number of inputs to the first level of the decoder. Therefore the static power in the decoder circuit ND P;D = Z Leakage current X VDD i=l The dynamic power consumed by the decoder circuit can be computed by computing the load capacitance CL using the method proposed in [7,81. The dynamic power: PdD CL. VDD2. F The total power consumed by the computational look-up table module p = PsM + PdM + 2( PsD f PdD) (21) In the next section the implementation of BNS architecture has been presented. 4. Systolic Implementation of Direct Transversal Filter Architecture in BNS A one bit multiplier and adder cellfor the high speed binary multiplier circuit is shown in fig-4 [l]. The cell uses 23 transistor and the cell draws no DC current. - S > ~, The number of cells required for a n-bit multplier will be n2. Number of devices required for a binary 16 bit multplier can be easily computed. Using this binary multiplier, the implementation of transversal filter using systolic architecture in the BNS is shown in fig-5. The static power consumption can he computed using (IO). The dynamic power can be computed using the procedure given in section 3. Figure 5. Syrtolir. Architecture for Complex FIR filter in ENS 5.Conclusion Implementation of transversal filter in quadratic residue number system and binary number system has been presented. A step by step pruceudre has been developed to compute the number of devices in both architecture for precharged CMOS technology. Algorithms have developed to compute the static and dynamic power in the case of the RNS and BNS architectures. Figure4. One bit multiplierandadder cell 876

5 REFERENCES [I]. J.lwamura, S.Taguchi, K. Suganuma, M.Kimura, H.Tango K.lchinose and T. Sato," A High speed and low power CMOSISOS multiplier-accumulator". Micro electronics Journal, Vol. 14. No , pp G.A Jullien." Residue Number Scaling and other Operations Using ROM Arrays", IEEE trans. on Computers. Vol. c.27. No.4, April 1978, pp A.Savoboda and M.Valach," Decimal Arithmetic Unit," Stroje Na Zpracovani, Vol. 8, Nakl. CSAU, Praha A.V.Oppenheim and C.I.Weinstein." Effects of finite register length in digital filtering and fast fourie,r transform." IEEE Proc. Vol.60, pp , Aug M.A.Soderstrand. W.K.Jenkins, G.A.Jullien and F.1.Taylor," Residue Number System Arithmetic: Modern Applications in Digital Signal Processing", IEEE press, 1YX6, New York. (71 C.Mead and L.Conway," Introduction to VLSl Systems", Addison Wesley [El A.Mukherjee." Introduction to nmos & CMOS VLSl System Design", Prentice-Hall R.Krishnan, G.A.lullien and W.C.Miller," Complex Digital Signal Processing Usong Quadratic Residue Number Systems," IEEE Trans. Acoust.. Speech, Signal Processing, Vol. ASP-34, No.1, Feb x77

Low-Power FIR Digital Filters Using Residue Arithmetic

Low-Power FIR Digital Filters Using Residue Arithmetic William L. Freking and Keshab K. Parhi Department of Electrical and Computer Engineering University of Minnesota 200 Union St. S.E. Minneapolis, MN