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1 Digital Design for Embedded Data Converters Valentino Liberali Universita degli Studi di Pavia Dipartimento di Elettronica Via Ferrata 1, 271 Pavia, Italy Phone: Fax: EUROPRACTICE Training Course on Design of State-of-the-Art Embeddable Data Converters for Mixed-Signal ASICs Barcelona (Spain) January 18{22, 1999

2 Contents: Basic Concepts Digital Filters Decimation and Interpolation Number Representation Elementary Arithmetics VLSI-Ecient Digital Processing 1

3 Basic Concepts DIGITAL SIGNAL PROCESSING := to sample a a continuous process and to extract a set of numbers which represent the process being sampled. Shannon's sampling theorem: If a continuous signal x(t) has a band-limited Fourier transform X(f) (i.e. jx(f)j = for 8jfj 62 [f ;f B]), then x(t) can be uniquely reconstructed without error from equally time-spaced samples x(kt), provided that the sampling frequency F s = 1 T is larger than the Nyquist frequency of the signal 2B. Properties of Fourier transform discrete in frequency $ periodic in time discrete in time (sampled) $ periodic in frequency BASIC CONCEPTS 2

4 A sampled signal x(kt) is completely represented in frequency by X(f) with h f 2 ; 1 i T (or f 2 h, 1 2T ; 1 i 2T ). We cannot distinguish X(f nf s ) from X(f)! aliasing X(f) -B S(f) B f -F s X(f) * S(f) F s f -F s F Fs 2 s 2 -B B F s Sampling without aliasing f BASIC CONCEPTS 3

5 X(f) -B B f S(f) -F s X(f) * S(f) F s f -F s 1 Fs 2 -B B F s - F 2 s Sampling with aliasing 1 f BASIC CONCEPTS 4

6 Digital Filters Filters are used for band limiting signals (antialiasing), for band splitting in multiplexing/demultiplexing, for pulse forming in digital modulators, for decimation and interpolation in A/D and D/A converters, for equalization, ::: Filters may be: linear non-linear adaptive Linear lters are linear time-invariant (LTI) systems! they are completely described by their impulse response h(t). For sampled-data systems (including digital systems), ltering may be described in the Z-domain: H(z) = Zfh(k)g = 1 X k=,1 h(k)z,k DIGITAL FILTERS 5

7 Linear lters may have: nite impulse response (FIR) innite impulse response (IIR) FIR lters The system function is The output is H(z) = N,1 X y(m) = N,1 X k= k= h(k)z,k h(k)x(m, k) By applying an impulse (k) to the input, the output goes to zero after N samples. An FIR lter is also called a moving average (MA) lter. DIGITAL FILTERS 6

8 Signal ow graphs of an FIR lter x(k) z -1 z -1 z -1 z -1 h() h(1) h(2) h(n-2) h(n-1) y(k) Direct form I x(k) h() h(1) h(2) h(n-2) h(n-1) y(k) z -1 z -1 z -1 z -1 Direct form II Linear phase FIR lters In DSP and communications, phase must be proportional to the frequency (linear phase): '(f) = 6 H(f) / f DIGITAL FILTERS 7

9 Linear phase corresponds to a pure delay in time domain. A linear phase FIR lter has symmetrical impulse response (either even-symmetrical or oddsymmetrical): h(k) = h(n, 1, k) h(k) =,h(n, 1, k) even-symmetric odd-symmetric Impulse responses of linear phase FIR lter h(k) N-1 2 Even symmetry N-1 k h(k) N-1 2 Odd symmetry N-1 DIGITAL FILTERS 8 k

10 Signal ow graph of an even-symmetrical linear phase FIR lter x(k) z -1 z -1 z -1 z -1 z -1 z -1 h() h(1) h(2) h N-1 ( ) 2 y(k) Direct form I This solution saves about one half of the multiplications. DIGITAL FILTERS 9

11 IIR lters The system function is H(z) = B(z) P N,1 A(z) = k= b(k)z,k 1, P M j=1 a(j)z,j The output is y(m) = N,1 X k= b(k)x(m, k) M X j=1 a(j)y(m, j) By applying an impulse to the input, the output does not go to zero after a nite number of samples. When B(z) = 1, the output sample y(m) is a linear regression of previous output values. Such a lter is called an autoregressive (AR) lter. DIGITAL FILTERS 1

12 Signal ow graph of an AR IIR lter a(1) a(2) a(m-1) a(m) x(k) z -1 z -1 z -1 z -1 y(k) Direct form I z -1 z -1 z -1 z -1 a(1) a(2) a(m) a(m-1) x(k) y(k) Direct form II DIGITAL FILTERS 11

13 When B(z) 6= 1, the lter is an autoregressive, moving average (ARMA) lter. Signal ow graphs of an ARMA IIR lter a(1) a(2) a(m-1) a(m) x(k) z -1 z -1 z -1 z -1 b() b(1) b(2) b(n-2) b(n-1) y(k) Direct form I DIGITAL FILTERS 12

14 z -1 z -1 z -1 z -1 a(1) a(2) a(m) a(m-1) x(k) h() b() b(1) b(2) b(n-2) b(n-1) y(k) z -1 z -1 z -1 z -1 Direct form II (non-canonical) Note: it is NOT required to have M = N, 1. PROs and CONs of IIR lters no linear phase (only approximation is possi- ^ ^ _ - - ble) _ - - less coecients than FIR lters sharp cut-o in transition band due to nite arithmetics, limit cycles may occur! oscillations DIGITAL FILTERS 13

15 Decimation and Interpolation Decimation by an integer factor M Decimation := reduction of sampling rate The new sampling period is T = MT The new sampling rate is F s = F s M! Sampling theorem requires an ANTI-ALIAS- ING FILTER before re-sampling x(k) h(k) w(k) M y(m) F' F s F s = s F s /M Anti-aliasing Sampling rate filter compressor Sampling rate reduction DECIMATION AND INTERPOLATION 14

16 X(f) 1 -F - F s F s F 2 2 s s W(f) 1 f 1 -F - F s F s F 2 2 s s Y(f) 1 f -MF' s -2F' s 1 1 -F' s - F' s F' F' 2 2 s s 2F' s MF' s f Typical spectra for decimation by M Sampling rate compression is done by taking only one sample out of M. The remaining M, 1 samples are lost. A delay z,r in the input sequence x(k) (or in the sequence w(k)) modies the output sequence y(m), unless r is an integer multiple of M. Therefore, decimation is NOT a time-invariant process. DECIMATION AND INTERPOLATION 15

17 Interpolation by an integer factor L Interpolation := increase of sampling rate The new sampling period is T = T L The new sampling rate is F s = LF s In case of \ideal" sampling, x kt L = if k is not an integer multiple of L (zero padding)! a SMOOTHING FILTER is required after interpolation x(k) w(m) y(m) L h(m) F' F' F s = s = s L F L F Sampling rate s Smoothing s expander filter Sampling rate increase DECIMATION AND INTERPOLATION 16

18 x(k) X(f) w(m) t W(f) 1 F F 2 s s 2F s LF s f y(m) t Y(f) 1 F' s F' s f 2 t 1 F' s F' f 2 s Time-domain and spectral representation of interpolation by L A delay in the input sequence produces the same (delayed) output sequence! interpolation is time-invariant DECIMATION AND INTERPOLATION 17

19 Multistage decimators If the decimation ratio can be factored into the product of integer numbers: M = I Y i=1 M i then the decimator can be realized with I independent stages. x(k) STAGE 1 STAGE 2 STAGE I y(m) h 1 (k) M 1 h 2 (k) M 2 h I (k) M I F F 1 = F 2 = F I = F /M 1 F /M 1 M 2 F /M Multistage decimator DECIMATION AND INTERPOLATION 18

20 Multistage interpolators In a similar way, if the interpolation ratio can be factored: Y L = I i=1 then the interpolator can be realized with I independent stages. L i x(k) L 1 STAGE 1 STAGE 2 STAGE I h 1 (k) L 2 h 2 (k) L I h I (k) y(m) F F 1 = F 2 = F I = L 1 F L 1 L 2 F LF Multistage interpolator PROs and CONs of multistage ^ ^ ^ _ - - _ - - Simple lters with reduced computation Reduced storage Reduced nite word-length eects Increased control structures Choice of optimum number of stages I DECIMATION AND INTERPOLATION 19

21 Filtering stages based on comb lters A comb lter has the impulse response 8 < h(k) = : 1; k N, 1 ; elsewhere Its discrete time Fourier transform (DTFT), i.e. its Z-transform evaluated along the unit circle z = e j, is H(e j ) = sin(n=2) sin(=2) ej(n,1)=2 and the magnitude of the frequency response is H(e j ) sin(n=2) = sin(=2) DECIMATION AND INTERPOLATION 2

22 Comb lter (N = 8) H Impulse response k H (db) 2π/N Frequency response π Ω In decimation, a comb lter extracts the average value from N samples. In interpolation, a comb lter holds the last value for N clock periods. DECIMATION AND INTERPOLATION 21

23 Practical implementation of a comb lter We can observe that H(z) = N,1 X k= z,k = 1, z,n 1, z,1 = 1 1, z,1 (1, z,n )! the lter can be realized with an accumulator and a diererentiator. The dierentiator is required to calculate only values actually sampled at the output. Since this operation does not require intermadiate samples between and N, the dierentiator can operate at the reduced sampling rate F s. F' s = F s /M X(z) F s z -1 Accumulator 1 - z -1 Y(z) Differentiator F' s Decimation with a comb lter DECIMATION AND INTERPOLATION 22

24 By reversing the operation of blocks in the comb decimator, we obtain a comb interpolator. F' s = LF s X(z) 1 - z z -1 Y(z) F s F' s Differentiator Accumulator Interpolation with a comb lter Higher order comb lters can be realized by cascading accumulators and decimators. PROs and CONs of comb lters ^ Simple operations suitable for high frequency operation (rst decimation stage in ADC; last interpolation stage in DAC) ^ _ - - _ - - Minimum storage of samples Good attenuation can be achieved only in a narrow band \sinc" attenuation in base band! need for equalization in other ltering stages DECIMATION AND INTERPOLATION 23

25 Numeric Representations Representation of unsigned numbers Natural number in base r: A = a n,1 a n,2 :::a 1 a value(a) = n,1 X i= a i r i Fractional number in base r: A = a n,1 a n,2 :::a 1 a :a,1 a,2 :::a,m value(a) = n,1 X i=,m In arithmetic processors, r = 2. a i r i Representation of signed numbers The most signicant digit is used as sign: for a positive number (r, 1) for a negative number NUMERIC REPRESENTATIONS 24

26 Thus: A = a n,2 :::a 1 a is a positive number A negative number A can have several representations: signmagnitude (SM): A SM = (r, 1)a n,2 :::a 1 a value( ASM ) =,1 n,2 X i= a i r i r's complement: A r = (r, 1)a n,2 :::a 1 a 1 where a i = (r, 1), a i value( Ar ) = value(a), r n,1 signed digit (SD): the range for each digit is given by a i 2 f,;::: ;,1; ; 1;::: ;g, with l m r,1 2 r, 1. In binary arithmetics (r = 2), a i 2 f,1; ; 1g. value(a SD ) = n,1 X i= a i r i NUMERIC REPRESENTATIONS 25

27 SD representation is redundant! the same number may have several SD representations. The SD representation with minimal number of non-zero digits and without consecutive non-zero digits is called Canonical Signed Digit (CSD) numbers. Advantages of number representations The goal is to process positive and negative numbers together. r's complement: good for addition; requires pre- and post-processing for multiplication SM: good for multiplication; requires pre- and post-processing for addition CSD: good for implementation with minimum hardware; requires ad hoc processing unit NUMERIC REPRESENTATIONS 26

28 Elementary Arithmetics The implementation of a digital lter (with constant coecients) requires: the ROM for coecients, the RAM for input samples, a multiplier, an accumulator, the control circuitry to generate RAM and ROM addresses and accumulator reset. Structure of a generic FIR lter DATA IN RAM ADDRESS X Σ DATA OUT ROM ELEMENTARY ARITHMETICS 27

29 Adder Several possible hardware implementations, with dierent area and speed: Carry propagate adder Carry look-ahead adder Carry select adder Conditional sum adder Pipelined adder structures can be used, when high throughput rate is needed. ELEMENTARY ARITHMETICS 28

30 Multiplier (for unsigned numbers) a 3 a 2 a 1 a b b 1 b 2 b 3 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p c s i s a b c i = A generic 4 4 multiplier made with AND and FULL-ADDER blocks c s i & FA a s b c i Array of n n cells Each cell implements 1-bit multiplication and 1- bit addition (with carry) ELEMENTARY ARITHMETICS 29

31 _ - - _ - - A wide multiplier requires a large area Maximum speed is limited by carry propagation (as for a (2n, 1)-bit carry-propagate adder) Assuming that the two operands a and b have binary digits with equal probability P = P 1 = 1 2, the probability of producing with a 1-bit multiplication is P = 3 4, while P 1 = 1 4. In a generic multiplier, the \cost" (silicon area, time, power) of a is exactly the same as the cost of a 1 but the DO NOT contribute to the nal product! Most lter coecients have very small values, which contain only few bits set to 1 in less signicant positions! in practice, is MUCH more frequent than 1 ELEMENTARY ARITHMETICS 3

32 VLSI-Ecient Digital Processing Let us assume that in the multiplier array the sample x(i) is from top and the coecient h(k) is from right. Multiplication can be realized more eciently by removing all the horizontal lines corresponding to the bits equal to in the coecient h(k). Multiplication! shift & accumulate (only for bits set to 1 in the coecient!) Use of CSD representation (minimum number of non-zero digits) further reduces the number of shifts. VLSI-EFFICIENT DIGITAL PROCESSING 31

33 An example: two stage decimation lter 1st decimation stage (sinc) 2nd decimation stage (generic FIR) bit MHz khz khz The rst stage is a comb lter with M 1 = 64. The second stage is an FIR lter with M 2 = 4, designed with a dedicated architecture. The Remez lter calculated by MATLAB: [N b c d] = remezord([ ], [1 ], [.1.1]); h = remez(n 2, b, c, d); is a 131-taps \ideal" lter, using coecients with innite precision. Truncation error: to reach a 6-dB attenuation in the stopband, the minimum accuracy is 18 bits (17 bits sign). VLSI-EFFICIENT DIGITAL PROCESSING 32

34 CSD representation is used for lter coecients, to replace the generic multiplier with shifter and accumulator. The total number of non-zero terms needed for the whole lter is 482. Since this gure is lower than the overall decimation factor, output samples can be calculated without any need for pipelining stages. If the CSD representation requires more nonzero terms, it is possible: to use two shifters in parallel on the same input sample (SD representation must be arrenged to have an even number of non-zero digits in each coecient) to use pipelining stage (increasing the complexity of control circuit) VLSI-EFFICIENT DIGITAL PROCESSING 33

35 Realized filter -1-2 Response [db] Normalized frequency Frequency response of the decimation lter VLSI-EFFICIENT DIGITAL PROCESSING 34

36 .5 Realized filter: ripple detail Response [db] Normalized frequency Frequency response of the decimation lter (detail) VLSI-EFFICIENT DIGITAL PROCESSING 35

37 Area and maximum frequency of blocks in.8 um CMOS Block area max. freq. shifter m MHz accumulator m MHz shifter accumulator (single channel) m MHz shifter accumulator (two channels) m MHz full multiplier m MHz VLSI-EFFICIENT DIGITAL PROCESSING 36

38 PROs and CONs of lters with dedicated architecture No general architecture (requires ad hoc de- ^ ^ _ - - sign) _ - - Reduced number of blocks and storage elements (area saving) Minimum number of operations (high speed; power saving) Control circuitry depends on specic implementation aspects (e.g. parallelization, pipeling) VLSI-EFFICIENT DIGITAL PROCESSING 37

39 References Books R. E. Crochiere and L. R. Rabiner. Multirate Digital Signal Processing. Prentice-Hall, Englewood Clis, NJ, USA, J. C. Candy and G. C. Temes (Eds.). Oversampling Delta- Sigma Data Converters. IEEE Press, Piscataway, NJ, USA, L. B. Jackson. Signals, Systems, and Transforms. Addison- Wesley, Reading, MA, USA, P. Pirsch. Architectures for Digital Signal Processing. John Wiley & Sons, Chichester, UK, A. V. Oppenheim and A. S. Willsky. Signals & Systems (2nd ed.). Prentice-Hall, Upper Saddle River, NJ, USA, Journal Papers R. E. Crochiere and L. R. Rabiner. \Interpolation and decimation of digital signals { A tutorial review", Proc. IEEE, vol. 69, pp. 3{331, March D. J. Goodman and M. J. Carey. \Nine digital lters for decimation and interpolation", IEEE Trans. Acoust., Speech and Sign. Proc., vol. 25, pp. 121{126, Apr E. B. Hogenauer. \An economical class of digital lters for decimation and interpolation", IEEE Trans. Acoust., Speech and Sign. Proc., vol. 29, pp. 155{162, Apr S. Chu and C. S. Burrus. \Multirate lter designs using comb lters", IEEE Trans. Circ. and Syst., vol. 31, pp. 913{924, Nov REFERENCES 38

Implementation of a Low Power Decimation Filter Using 1/3-Band IIR Filter

Implementation of a Low Power Decimation Filter Using /3-Band IIR Filter Khalid H. Abed Department of Electrical Engineering Wright State University Dayton Ohio, 45435 Abstract-This paper presents a unique