SBG SDG. An Accurate Error Control Mechanism for Simplification Before Generation Algorihms

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1 An Accurate Error Control Mechanism for Simplification Before Generation Alorihms O. Guerra, J. D. Rodríuez-García, E. Roca, F. V. Fernández and A. Rodríuez-Vázquez Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Sevilla, SPAIN Phone: , FAX: , Abstract The use of simplification before eneration techniques to enable the approximate symbolic analysis of lare analo circuits is discussed. This paper introduces an error control mechanism to drive the circuit reduction, which overcomes the accuracy problems of previous approaches. The features and efficiency of the new methodoloy are demonstrated throuh several practical examples. G modelin C d mb v bs C s D m v s S C db ds B C sb 1. Introduction Unlike SPICE-like simulators, in which all circuit parameters are assined a numerical value, symbolic analyzers handle circuits with symbolic parameters. The result of their analysis task is obviously a symbolic expression of the circuit characteristic at hand. One of the main limitations of symbolic analyzers has been traditionally found in the exponential increase of the expression lenth with the circuit size [1]. On the one hand, this makes the symbolic results very difficult to interpret or use. On the other, it constitutes a drastic limitation to the maximum circuit size that can be analyzed. An important advance in the solution of these problems has been achieved by the introduction of simplification before and durin eneration techniques [1]. The role that these techniques play within the symbolic analysis flow is better understood by lookin at Fi. 1. A typical analysis problem starts from the small-sinal model of the circuit. Usin some analysis technique (i.e., sinal flow raphs, MNA, etc.), a set of network equations, either in matrix or raph form, is obtained. Simplification before eneration (SBG) techniques either eliminate entries from the circuit matrix, or eliminate raph branches and contract raph nodes, yieldin a reduced matrix or raph which is much easier to solve. Once approximated, the resultin simplified system of equations must be solved. The complete solution usually * This work has been supported by the EU ESPRIT Proram in the Framework of the Project #21812 (AMADEUS) and the Spanish C.I.C.Y.T. under contract TIC equation formulation sc 1 + m2 + G L ma2 ds3 sc s6 ma2 mb4 ds5 m4 ds3 m6 ds3 + + ds7 sc sa l3 mq2 sc q4 sc eq ds3 + m12 + sc s1 eq + G sc s5 m l3 sc 2 sc 11 m3 m4 m12 sc 5 sc q4 mq5 l2 a1 sc 12 sc 5 sc 3 ds3 + ds5 m12 sc l2 m12 ds4 sc 1 + m2 + G L m8 ds9 sc d3 + sc s6 sc d3 s C s6 mb2 sc d3 sc s6 sc d3 + sc s6 sc 2 + m2a + G L ds3 + ds7 ds8 ds7 a ds12 a3 ds3 l2 + sc 6 b sc a2 ds3 sc s6 sc s6 ds9 sc 1 + m2 sc 2 l3 sc eq m m23 m23 ds3 m12 ds3 sc d3 sc d3 sc s6 + sc s6 s C d3 sc d3 SBG SDG m1 m4 Av= ( ds1 + ds2 )( ds3 + ds4 )+sc c m4 Fi. 1. Combination of simplification strateies in the symbolic analysis flow. contains a hue number of insinificant contributions. Simplification Durin Generation (SDG) techniques aim to calculate directly an approximated solution, which contains only the dominant contributions [1]-[3]. This paper focuses in the most critical part of an SBG alorithm: an efficient and accurate mechanism to control

2 the error induced by the reduction process. Section 2 reviews previous work and introduces a new methodoloy to solve the problems of reported approaches. The methodoloy is extensively tested with practical examples in Section Simplification before eneration 2.1. Backround and previous work The computational complexity of the solution alorithms for a set of network equations rows exponentially with the circuit size. And so does the complexity of the resultin symbolic expressions. However, there are usually lare differences amon the relative contribution of the different circuit parameters to the lobal circuit behavior. Neliible parameters make computationally more expensive the solution of the set of network equations and more difficult the interpretation of the results. Reported SBG approaches simplify the system of equations prior to address its solution. In [4],[5], device parameters are eliminated from the nodal admittance matrix while the error induced is below a iven threshold. In [6], raph branches are pruned or raph nodes are contracted while their contribution to the network function keeps below some iven error. Althouh these techniques exhibit sinificant differences, they share a common feature: the error induced by a matrix entry elimination, or by branch prunin or node contraction in a raph, is evaluated at a sinle or a finite number of frequency points. Therefore, accuracy is not uaranteed at frequencies different from those in the set of samplin frequencies, as the practical example in Fi. 2 illustrates. This fiure shows the manitude and phase errors at 1MHz f 1MHz, induced when samplin-based SBG alorithms, like those in [4]-[6], are applied to the interator in Fi. 3. The manitude and phase error specs were H ± 5dB and φ H ± 5 in the frequency rane 1Hz f 1MHz. As Fi. 2 shows, the error specs are met at the samplin frequencies, but exceeded at intermediate ones. An obvious solution is to use a denser frequency samplin, at least in the neihborhood of the poles and zeros of the system. However, this increases noticeably the computational cost of the alorithm, on the one hand, and there is not a systematic procedure on how dense should be the frequency samplin to uarantee full accuracy in a frequency rane, on the other. The methodoloy presented herein solves this problem by introducin error evaluation mechanisms which uarantee the required accuracy at any frequency within a iven rane frequency (Hz) frequency (Hz) Fi. 2. Manitude and phase errors of Fi. 3 at 1MHz f 1MHz due to the application of an SBG alorithm. Solid trianles denote the samplin frequencies manitude error (db) phase error (de) Fi. 3. Interator New SBG methodoloy Our approach performs the approximation by replacin those elements whose contribution (appropriately measured) to the network function is small, with a zero-admittance (device removal) or zero-impedance element (contraction of nodes). The objective is to find the sequence of node contractions and device removals yieldin the simplest circuit (smallest number of nodes and branches) and whose induced error keeps below some iven threshold. First, it must be decided if node contractions must be prioritized over device removals or viceversa. After the SBG process, the resultin simplified raph must be solved, commonly by the application of a SDG process. The most efficient SDG alorithms reported are based on the two-raph method [7] and their computational complexity rows much faster with the number of circuit nodes than with the number of devices. Therefore, node contractions are prioritized in our alorithm. v in v out

3 Evaluate contribution of each node contraction Try least sinificant contraction Error exceeded? Yes Evaluate contribution of each device removal Try least sinificant removal Error exceeded? The different steps of the simplification alorithm are raphically shown in Fi. 4. First, the contribution to the transfer function of the contraction of the terminal nodes of each device individually is computed individually and a sorted list is built. The least sinificant contraction from the list is picked and the induced manitude and phase errors are evaluated. If the allowed error is not exceeded the node contraction is performed and all devices connected in parallel are removed. The contraction process continues iteratively with the followin one in the sorted list while the accumulated error in manitude and phase does not exceed the specified maximum errors. When the contraction process is finished an analoous operation with device removals is performed Error evaluation No No node contractions Perform contraction device removals Perform removal Fi. 4. Flow diaram of the SBG methodoloy. As shown in Fi. 4, both, the node contraction and the device removal processes start with an evaluation of the contribution of each possible contraction or removal. That means that the difference in manitude and phase behavior between the oriinal circuit and a modified circuit in which a pair of nodes have been contracted or a device has been removed must be evaluated. Also, when each node contraction is tried it must be checked if the difference in manitude and phase behavior between the oriinal circuit and the reduced circuit, in which the contraction at hand, toether with all previously accepted contractions have been performed, exceeds the error specifications. A similar test must be performed when each device removal is tried. Our objective is to evaluate the maximum manitude and phase deviations for any frequency in a iven rane in all error checkin steps described above. Let us denote H ex ( s) = N ex ( s) D ex ( s) the network function of the complete circuit with only the complex frequency s as symbolic parameter, and H ap ( s) = N ap ( s) D ap ( s) the analoous network function of a simplified circuit in which the appropriate node contraction(s) and/or device removal(s) have been performed. The manitude and phase errors are iven by: H φ H N apr + N api H ex ( jω) H ap ( jω) H ex ( jω) 1 D apr + D api = = N exr + N exi (1) D exr + D exi = H ex ( jω) H ap ( jω) N exi D exi N api D api = atan atan atan atan N exr D exr N apr D apr where subscripts r and i denote real and imainary parts. Therefore, the evaluation of the maximum manitude and phase errors requires: a technique to obtain the network functions H ex ( s) and H ap ( s) of (usually lare) analo circuits, and an efficient technique to obtain the maxima of the functions in (1) when ω varies within a iven rane. The first problem can be solved by means of numerical interpolation techniques [7]. An efficient interpolation technique based on adaptive scalin able to handle lare analo circuits can be found in [8],[9]. Our solution for the second problem is based on the use of interval analysis techniques [1]. H and φ H in (1) are univariate functions in ω, which can take any value within the frequency interval [ ω L, ω U ], where ω L and ω U are the lower and upper bounds of the interval, respectively. The problem is solved if accurate estimates of the lower and upper bounds of H and φ H, when ω [ ω L, ω U ], can be calculated. This computation, commonly known as the interval extension of H and φ H, can make use of interval arithmetic operators. Substitution of the real variable ω in (1) and real operators (addition, product, quotient, etc.) by the correspondin interval variables and operators yields the so-called natural interval

4 extension. Unfortunately, this computation usually yields too conservative estimates of the maximum errors [11]. To solve this problem, the natural interval extension is applied to the derivatives of (1). Althouh, the estimates of the derivatives are also very conservative, the zero inclusion in the resultin interval extension is enouh to delimit frequency subranes in which the maximum manitude and phase errors occur. Then, the exact frequency points for which the maximum manitude or phase errors occur in those frequency subranes are easily calculated usin the Newton-Raphson method. 3. Experimental results (a) (b) The efficiency and the complexity reduction capabilities of the proposed SBG methodoloy are illustrated with the circuits in Fi. 5(a)-(d) where the transistor models in Fi. 5(e)-(f) were used. The maximum manitude and phase deviations allowed in the voltae ain were ma ± 3dB and phase ± 5 in the frequency rane f [ 1Hz, 1MHz]. The complexity reduction achieved (measured as the number of devices and nodes in the oriinal circuit versus those in the simplified circuit) and the computation time are listed in Table 1. A lare, hierarchical example is the bandpass filter in Fi. 6a. It is composed of four OTAs, whose transistorlevel schematic is shown in Fi. 6b, and one biasin OTA, shown in Fi. 6c. When expandin the small-sinal models, the resultin circuit model contains 45 nodes and 619 basic devices. The manitude and phase plots of the voltae transfer function of this filter are shown in Fi. 7. A maximum circuit reduction is required with maximum manitude and phase deviations: ma ± 3dB phase ± 5 in f [ 1Hz, 1MHz]. These manitude and phase constraints are shown toether with the manitude and phase plots in Fi. 7. The application of the SBG alorithm yields a reduced circuit model containin only 31 nodes and 161 devices, Table 1. Statistics for the circuits in Fi. 5. Circuits in Fi. 5(a) 5(b) 5(c) 5(d) # nodes in oriinal small-sinal model simplified # devices in oriinal small-sinal model simplified CPU time (s.) (2) B MB1 (d) MB3 MB7 MB2 r π (c) MB6 MI1 MB5 MB4 C π C µ r b r µ B MI4 MI3 MN3 MN2 m MP1 C o M2 MI2 + MN1 M1 r c M3 M4 M11 G C D m ds C db db B E S C sb r C b (e) e (f) sb E Fi. 5. (a) Simple BiCMOS opamp; (b)µa741 opamp; (c) µa725 opamp; (d) CMOS opamp; (e) bipolar transistor model; and (f) MOS transistor model. M7 M5 M9 C s M12 M13 M14 M1 M8 MA8 M6 C d mb MA7 MA1 MA9 MA4 MA3 MA6 MA5 VDD MA2 C C2 OUT C C1 MA1 VSS (a) m 1 n n 1 v in bias m 2 m 2 v BP m1 (b) (c) Fi. 6. (a) Filter; (b) OTA schematic; and (c) biasin OTA.

5 Manitude (db) Phase (deree) upper error bound -6 lower error bound frequency(hz) upper error bound -1 lower error bound frequency(hz) 1 8 Fi. 7. Bode plots before and after the application of the SBG alorithm to the filter in Fi. 6. while the manitude and phase plots of the simplified circuit keep within the specified error limits, as shown in Fi. 7. One important feature is that all devices of the biasin OTA are eliminated in the simplification process. This fact demonstrates the capability of the SBG alorithm to detect and eliminate subcircuits which do not belon to the sinal path and, therefore, do not affect the network function. As illustration of the symbolic expression calculation after the SBG step, Fi. 8 shows the voltae ain provided by the complete SBG+SDG methodoloy applied to the CMOS opamp in Fi. 5(d). This example shows the possibility of eneratin very compact, interpretable expressions for the main behavior characteristics of even lare buildin blocks. Conclusions This paper has introduced an accurate, but efficient, simplification before eneration methodoloy. Based on its cooperative work with simplification durin eneration techniques, very readable and interpretable symbolic analysis is achievable. Its extremely ood behavior allows to address its combination with hierarchical decomposition strateies for very lare circuit analysis. It is also bein used to develop new methodoloies for symbolic pole/zero extraction, with the objective to provide additional insiht into the circuit behavior. A v v OUT = = v v + = G. m14 G. m8 G. m13 (G m6 +G m12 ). (G ma1 +G ma2 ) G. m14 G. m8 G. m6 G. ma2 G m11 = G. ds12 G. ds14 G. m8 (G m5 +G m11 ). (G dsa1 +G dsa2 ) + G. m14 G. ds6 G. ds8 (G m5 +G m11 ). G dsa2 + G. m14 G. m5 G. ds8 G. dsa2 G ds14 + s ((C c1 +C c2 ). G. m14 G. m8 (G m5 +G m11 ). (G ma1 +G ma2 ) Fi. 8. Symbolic expression for the voltae ain of Fi. 5(d). References [1] F.V. Fernández, A. Rodríuez-Vázquez, J.L. Huertas and G. Gielen, Symbolic Analysis Techniques. Applications to Analo Desin Automation, IEEE Press, [2] F.V. Fernández et al.: "Symbolic analysis of lare analo interated circuits by approximation durin expression eneration," Proc. IEEE ISCAS, V. CAD, pp , [3] P. Wambacq, F.V. Fernández, G. Gielen, W. Sansen and A. Rodríuez-Vázquez, "Efficient symbolic computation of approximated small-sinal characteristics of analo interated circuits," IEEE J. Solid-State Circuits, Vol. 3, No. 3, pp , March [4] Jer-Jaw Hsu and C. Sechen, Fully symbolic analysis of lare analo interated circuits, Proc. IEEE Custom Int. Circuits Conf., pp , San Dieo, CA, [5] R. Sommer, E. Henni, G. Droe and E. H. Horneber, Equation-based symbolic approximation by matrix reduction with quantitative error prediction, Alta Frequenza, vol. 5, no. 6, pp , November [6] Q. Yu and C. Sechen, A unified approach to the approximate symbolic analysis of lare analo interated circuits, IEEE Trans. Circuits and Systems I, Vol. 43, No. 8, pp , Au [7] P.M. Lin, Symbolic Network Analysis. Elsevier, [8] I. García-Varas, M. Galán, F.V. Fernández and A. Rodríuez-Vázquez, New alorithms for reference eneration in symbolic analysis of lare analo circuits, Proc. European Desin & Test Conf., pp , [9] F. V. Fernández, O. Guerra, J. D. Rodríuez-García and A. Rodríuez-Vázquez, Symbolic analysis of lare analo interated circuits: the numerical reference eneration problem, IEEE Trans. Circuits and Systems-II, vol. 45, no. 1, pp , Oct [1] R. E. Moore, Methods and Applications of Interval Analysis. SIAM, [11] F.V. Fernández, A. Rodríuez-Vázquez, J.D. Martín and J.L. Huertas, Formula approximation for flat and hierarchical symbolic analysis, Analo Interated Circuits and Sinal Proc., Vol. 3, No. 1, pp , 1993.